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The metal–semiconductor interface is fundamental to any semiconductor device and the success of advanced technology nodes critically depends upon the minimization of the contact resistance at the interface. In this paper, we calculate the electronic structure of a metal–semiconductor interface (TiGe/Ge contact) within the framework of first-principles density functional theory simulations. We report the modulation of the Schottky barrier height with respect to the different phases of TiGe metal and different crystallographic orientations of Ge substrate. We further compute the ${I}$ – ${V}$ characteristics of the TiGe/Ge contact with nonequilibrium Green’s function formalism, using a two-terminal device configuration. The calculated transmission spectrum allows us to extract the contact resistance at the metal–semiconductor interface. Furthermore, the onset of Ohmic contact for p-doped TiGe/Ge interface is identified by studying the ${I}$ – ${V}$ characteristics as a function of increasing active carrier concentration. We find that a doping concentration of 1e21 is sufficient to transform the Schottky contact into Ohmic and thereby achieve a least possible contact resistance at the interfaces. Our paper thus provides useful physical insights into the nanoscale details of the TiGe/Ge interfaces and can guide further process development to minimize the contact resistance.

As the scaling of the device dimensions in CMOS devices runs into physical limitations, new materials beyond Si with high electron and hole mobilities such as Ge, SiGe, and III-V materials are introduced. Challenges of CMP for these materials are reviewed in this paper. First we discussed the challenge of the new integration schemes to CMP. Loading effects can result in different growth rates for varying feature sizes, which results in a critical dimension dependent overburden. This makes it more difficult to meet the targets of the CMP process with respect to oxide loss and Ge/SiGe/III-V dishing. Secondly we discuss the challenge for the reduction of the defects during CMP for these new materials. Finally the challenge that is relevant especially for the introduction of III-V materials is studied. During the polishing of III-V materials, toxic gases as well as III-V containing liquid waste will be created. The chemical mechanism of the waste control is discussed.

We report record low $8.4\times 10^{-10}~\Omega $ -cm2 n-type S/D contact resistivity with laser-induced solid/liquid phase epitaxy of Si:P inside nano-scale contact trenches. Significant reduction of device resistance and resultant great gain of drain current has been demonstrated in scaled n-FinFETs with a contact length of 20 nm.

Fin width scaling is required to improve FinFET electrostatics for future technology nodes. This paper studies the benefits, trade-offs and limitations of aggressive fin width (W) scaling on logic and SRAM device characteristics. TCAD analysis is used to understand the impact of gate length (Lg)scaling along with fin width scaling to optimize AC performance. In this paper, W was scaled from 8nm to 1.6nm. It was found that there is a critical fin width (Wc)at ∼4nm. In the W>Wc region, due to better electrostatics from narrower fin, drain-induced barrier lowering (DIBL), DC performance and SRAM Vt mismatch (Vtmm) were improved. As W was scaled down further to W c ∼ 4nm.

The semiconductor industry continues to drive patterning solutions that enable devices with higher memory storage capacity, faster computing performance, and lower cost per transistor. These developments in the field of semiconductor manufacturing along with the overall minimization of the size of transistors require continuous development of metrology tools used for characterization of these complex 3D device architectures. Optical scatterometry or optical critical dimension (OCD) is one of the most prevalent inline metrology techniques in semiconductor manufacturing because it is a quick, precise and non-destructive metrology technique. However, at present OCD is predominantly used to measure the feature dimensions such as line-width, height, side-wall angle, etc. of the patterned nano structures. Use of optical scatterometry for characterizing defects such as pitch-walking, overlay, line edge roughness, etc. is fairly limited. Inspection of process induced abnormalities is a fundamental part of process yield improvement. It provides process engineers with important information about process errors, and consequently helps optimize materials and process parameters. Scatterometry is an averaging technique and extending it to measure the position of local process induced defectivity and feature-to-feature variation is extremely challenging. This report is an overview of applications and benefits of using optical scatterometry for characterizing defects such as pitch-walking, overlay and fin bending for advanced technology nodes beyond 7nm. Currently, the optical scatterometry is based on conventional spectroscopic ellipsometry and spectroscopic reflectometry measurements, but generalized ellipsometry or Mueller matrix spectroscopic ellipsometry data provides important, additional information about complex structures that exhibit anisotropy and depolarization effects. In addition the symmetry-antisymmetry properties associated with Mueller matrix (MM) elements provide an excellent means of measuring asymmetry present in the structure. The useful additional information as well as symmetry-antisymmetry properties of MM elements is used to characterize fin bending, overlay defects and design improvements in the OCD test structures are used to boost OCDs’ sensitivity to pitch-walking. In addition, the validity of the OCD based results is established by comparing the results to the top down critical dimensionscanning electron microscope (CD-SEM) and cross-sectional transmission electron microscope (TEM) images.

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1–4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1–4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

We demonstrate a technique for selective GeO x -scavenging which creates a GeO x -free IL on Si 1−x Ge x substrates. This process reduces N it by >60% to 2e11 and increases high-field mobility at N inv =1e13 cm−2 by ∼1.3× in Si 0.6 Ge 0.4 pFETs with sub-nm EOT.

Contact engineering of Ge-rich source/drain is of critical importance for the development of advanced nano-scale CMOS technology nodes. Germanosilicide or Germanide contacts with low Schottky barrier height are highly desirable to achieve low contact resistance for a Ge-rich source/drain. However, practical integration of Ge-rich SiGe into devices is complicated by its unique physical and chemical properties as compared to Si-rich epitaxial SiGe. We have observed significant erosion along the SiGe interface with its dielectric cap layer. The N2-H2 remote plasma resist strip process has been shown to trigger this erosion when GeO2 exists together with SiO2 at the interface. The integrity of Ge-rich SiGe contact interface can be preserved by replacing the N2-H2 remote plasma resist strip with an O2-based photoresist ash process. Cross-sectional STEM and EDX elemental analysis have confirmed Germanide and Germanosilicide formation at the Ge-rich SiGe contact interface.

We describe the use of high resolution X-ray diffraction (HRXRD) for inline metrology of strain relaxed buffer (SRB) layers and epitaxial layers grown thereon. The use of SRBs as a virtual substrate is a promising candidate for advanced CMOS logic at the 7 nm technology node and presents some unique challenges to traditional HRXRD measurements. To overcome these challenges, reciprocal space maps (RSMs) were employed to characterize different films on SRBs. We discuss the measurement strategies and recent improvements to X-ray metrology tools that enable these measurements for inline process control. Furthermore, advances in the automated data extraction and analysis are introduced.

The semiconductor industry continues to drive patterning solutions that enable devices with higher memory storage capacity, faster computing performance, and lower cost per transistor. These developments in the field of semiconductor manufacturing along with the overall minimization of the size of transistors require continuous development of metrology tools used for characterization of these complex three-dimensional device architectures. Optical scatterometry or optical critical dimension (OCD) is one of the most prevalent inline metrology techniques in semiconductor manufacturing because it is a quick, precise, and nondestructive metrology technique. However, at present OCD is predominantly used to measure the feature dimensions such as line-width, height, side-wall angle, etc. of the patterned nanostructures. Use of optical scatterometry for characterizing patterning process errors such as pitch-walking, overlay, etc. is fairly limited. Characterization of process-induced errors is a fundamental part of process yield improvement. It provides process engineers with important information about process errors, and consequently helps optimize materials and process parameters. Scatterometry is an averaging technique and extending it to measure the position of local process-induced errors and feature-to-feature variation is extremely challenging. This report is an overview of applications and benefits of using optical scatterometry for characterizing defects such as pitch-walking, overlay, and fin bending for advanced technology nodes beyond 7 nm. Currently, the optical scatterometry is based on conventional spectroscopic ellipsometry and spectroscopic reflectometry measurements, but generalized ellipsometry or Mueller matrix (MM) spectroscopic ellipsometry data provide important, additional information about complex structures that exhibit anisotropy and depolarization effects. In addition, the symmetry–antisymmetry properties associated with MM elements provide an excellent means of measuring asymmetry present in the structure. The useful additional information as well as symmetry–antisymmetry properties of MM elements is used to characterize fin bending, overlay defects, and design improvements in the OCD test structures are used to boost OCDs’ sensitivity to pitch-walking. In addition, the validity of the OCD-based results is established by comparing the results to the top down critical dimension-scanning electron microscope and cross-sectional transmission electron microscope images.

Negative Bias Temperature Instability (NBTI) is assessed in (100)Si planar cSi 0.5 Ge 0.5 Replacement Metal Gate (RMG) gate stacks, with and without high-k nitridation for various post nitridation anneal (PNA) conditions. Observed initial N it was 8∼9×1011 cm−2. Nitrided devices show higher NBTI than non-nitrided devices. Observed time slopes become shallower from ∼0.25 to ∼0.20. Overall, observed NBTI in cSi 0.5 Ge 0.5 stacks are promising making it viable for use in 7nm and below nodes.