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A series of novel externally reconfigurable power electronic modules (RPEMs) are invented to increase the flexibility of power modules and their application purposes. In this article, the concept of RPEMs, their switching arrangements, and power-module-based architectural design are demonstrated. An RPEM is then designed, analyzed through simulations, and compared with the conventional fixed-configuration power electronic modules. The sizes of the power modules and used power terminals are kept similar to avoid any differences in power loop inductance values solely due to various trace pad sizes. In addition, similar gate/source pads and signal pins are used for all of the designed power modules to have constant switching dynamics in all modules. The comparison results show that the internal parasitic inductance and performance are still comparable with the conventional modules despite having high configurability. The designed RPEM and a conventional full-bridge (FB) power module are fabricated and characterized. The experimental tests show that the difference between the overshoot voltages on both RPEM and FB power modules is less than 2%. Such flexibility without compromising the power module performance decreases the engineering time for designing different power modules for various power electronic converters; hence, the production speed can be improved while decreasing the overall module cost. [ABSTRACT FROM AUTHOR]

This paper proposes a packaging method for SiC MOSFETs that provides a feasible solution of implementing press-pack packaging on SiC MOSFETs to extend the application of SiC devices into the high power range. The challenges in realizing press-pack packaging of SiC MOSFETs are addressed, and the solutions are proposed that fit the specific requirements of SiC MOSFET. To achieve pressure contact on SiC MOSFETs, miniature and flexible press pins called “fuzz buttons” are used in a low-profile interposer to realize die top side connection. Since the press-pack does not provide internal insulation between the active device and the heatsink, the heatsink is included in the power loop. To avoid large parasitic loop inductance being introduced by the heatsinks, a microchannel heatsink is developed which has a low thickness while remaining adequate heat dissipation efficiency. The structure and assembly process flow of the press-pack SiC MOSFET are provided. A half-bridge stack prototype with two press-packs and three heatsinks is developed. The thermal and electrical performances of the press-pack and the half-bridge stack are evaluated by simulations and tests to validate the feasibility of the proposed packaging approach. [ABSTRACT FROM PUBLISHER]

Power module heat dissipation with spatial inhomogeneity and induced nonuniform temperature distribution presents a challenging concern for system reliability due to thermo-mechanical stresses. These reliability challenges are especially important for nonplanar designs using 3-D packaging principles. Here, we develop a heat spreader thermal switch capable of actively reducing temperature gradients between silicon carbide (SiC) devices in a three-level T-type power converter, which can change depending on electronic operating conditions. The heat spreader thermal switch consists of a stainless-steel (SS) heat spreader and a copper sliding switch embedded within the spreader. Heat transfer from the SiC devices and within the spreader can be controlled by moving the slider between positions within the spreader. To understand heat transfer mechanisms and design the heat spreader thermal switch, we conducted 3-D finite element method simulations to calculate the minimum attainable temperature difference between SiC devices. We used the finite element simulation to quantify the reduction in junction temperature swing during dynamic operation and coupled the results to the Coffin–Manson reliability model to quantify lifetime to failure. We integrated the heat spreader thermal switch with one phase of a three-phase T-type converter and demonstrated isothermalization at different working conditions. At 2.4-kW converter power, each hot SiC device dissipated 4.7 W of heat, resulting in a device case temperature of 43 °C, with each cold SiC device dissipating 1.7 W at 38 °C. The device-to-device temperature difference was decreased from 5 °C to 0 °C by moving the switch a distance of 20 mm. Finite volume method (FVM) simulations of the conjugate heat transfer problem validate the experimental results and support analysis of key performance parameters. This work demonstrates successful isothermalization of a power converter with an active heat spreader thermal switch and develops simulation and design guidelines for successful electro-thermal codesign and implementation of thermal switches for other electronics applications for which isothermalization and enhanced device reliability is a key issue. [ABSTRACT FROM AUTHOR]

Although LLC converters are attractive in industrial applications due to its advantages of soft switching, high efficiency, and simple control, in wide voltage gain range applications, large switching frequency operating range is required, which may cause the loss of soft switching operation and existence of control instability issue. In this article, a novel LLC converter with two LLC resonant tanks is proposed. The proposed converter has three operation modes, namely, dual full-bridge operation mode, full-bridge operation mode, and half-bridge operation mode, which can cover the high voltage gain range, medium voltage gain range, and low voltage gain range operations, respectively. The operational principles of the proposed converter are presented, and brief design considerations are discussed. A 250 W experimental prototype with six times input voltage range (50–300 V) was built to validate the theoretical analysis of the proposed converter. Comparisons among different LLC topologies for wide voltage gain range applications are made. [ABSTRACT FROM AUTHOR]

This paper presents a three-dimensional (3-D) wire bondless power module using silicon carbide (SiC) power devices. Commercially available SiC power devices are designed for wire bonding. Wire bonds have an inherent parasitic inductance that limits high-frequency switching. This results in an underutilization of the full potential of SiC power devices, which have very low switching losses at high frequencies. Wire-bonded power modules run into a performance ceiling when it comes to ultrafast switching. This paper strives to provide a solution to this issue, which involves reconfiguring a commercially available bare die SiC power device into a flip-chip-capable device. A wire bondless SiC Schottky diode package was demonstrated and its performance was contrasted with a conventional wire-bonded package. A 24% reduction in the ON-state resistance was observed in the wire bondless package. As a next step, wire bondless SiC MOSFET packages were developed and tested in a half-bridge configuration in a highly integrated 3-D arrangement. This approach departs from the conventional concept of a power module—demonstrating a direct-bonded-copper-less and baseplate-less half-bridge switching cell. Double-pulse tests conducted on the cell showed >3× reduction in the parasitic inductance of the 3-D cell as compared with a conventional wire-bonded module. [ABSTRACT FROM AUTHOR]

This article presents the plan and initial feasibility studies for an Integrated Wire Bond-less Power Module. Contemporary power modules are moving toward unprecedented levels of power density. The ball has been set rolling by a drastic reduction in the size of bare die power devices owing to the advent of wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride. SiC has capabilities of operating at much higher temperatures and faster switching speeds compared with its silicon counterparts, while being a fraction of their size. However, electronic packaging technology has not kept pace with these developments. High-performance packaging technologies do exist in isolation, but there has been limited success in integrating these disparate efforts into a single high-performance package of sufficient reliability. This article lays the foundation for an electronic package designed to completely leverage the benefits of SiC semiconductor technology, with a focus on high reliability and fast switching capability. The interconnections between the gate drive circuitry and the power devices were implemented using a low temperature cofired ceramic interposer. [ABSTRACT FROM AUTHOR]

This article puts forward a hybrid model predictive control (H-MPC) for an inner-interleaved hybrid multilevel converter (IHMC). The sign patterns of the original and shifted reference vectors in the original and virtual space vector diagrams (VSVDs) are used, respectively, to realize the phase-disposition pulsewidth modulation (PWM) and determine the low-frequency switching states. Then, the three adjacent vectors are selected in the second-layer VSVD and the optimal current tracking is safeguarded by the duty cycle optimization of the three adjacent vectors. Finally, through applying the phase-shifted PWM to the two interleaved legs, a constant and doubled equivalent switching frequency can be achieved, which further paves the way for dc-link and floating capacitor voltages balancing and circulating current mitigation with the use of the straightforward duty cycle adjustments. The proposed H-MPC enables the decoupling of the low- and high-frequency stages in the IHMC and also reduces both output current ripples and computational burden while achieving a constant switching frequency simultaneously. Comprehensive simulation and experimental studies on an all silicon carbide prototype verify the effectiveness of the proposed control strategy. [ABSTRACT FROM AUTHOR]

This paper reports high-temperature optocouplers for signal galvanic isolation. Low temperature co-fired ceramic (LTCC) technology was used in the design and fabrication of the high-temperature optocoupler package. The optimal coupling behaviors, driving capabilities and response speed of the optocouplers were concentrated and investigated in this paper. Emitters and detectors with different emission and spectral wavelengths were studied to achieve optimal coupling behaviors. Relatively high coupling efficiency is achieved with emitters and detectors of emission and spectral wavelength in the red spectrum (i.e., 620–750 nm), leading to higher current transfer ratios (CTR). To further enhance the electrical performance, optocouplers with multiple detectors in parallel were designed and fabricated. CTR, leakage current and response speed (i.e., propagation delay, rise time and fall time) of the optocouplers were characterized over a range of temperatures from 25 to 250 °C. The CTR degrades at high temperatures, while the leakage current and response speed show little degradation with varying temperatures. Furthermore, the behaviors of the optocouplers with varying temperatures are modeled and analyzed. [ABSTRACT FROM AUTHOR]

This article puts forward a hybrid model predictive control (H-MPC) that enables the decoupling of low- and high-frequency stages in a seven-level hybrid multilevel converter (7L-HMC). It first uses the sign pattern of the reference voltage vector to determine switching states of the low-frequency stage. Next, the reference vector is shifted to the internal hexagon of the original space vector diagram, which is thereby converted to a 120° oblique coordinate system, where the adjacent vectors can be rapidly selected. Then, the optimal current tracking is primarily safeguarded by the duty cycle optimization of the three adjacent vectors. Finally, an optimized symmetric switching sequence minimizing the dc voltage deviation over one control iteration is selected through the assessment of possible switching sequences that are subject to the chosen vectors with optimal duty cycles. The proposed H-MPC method can reduce both the current ripple and computational burden while achieving a constant switching frequency. Comprehensive simulation and experimental comparisons on an all-silicon-carbide 7L-HMC prototype verify the effectiveness of the proposed H-MPC. [ABSTRACT FROM AUTHOR]

This article presents the design and demonstration of an all silicon carbide (SiC) 2×250 kW dual inverter for heavy-duty traction applications. Through the use of a formal electrothermal-control co-design approach, the maximum power density of the proposed inverter system is 60 kW/L, which is accomplished by. More specifically, to analyze the thermal performance of the inverter, a lumped thermal model is developed based on the characteristics of the power modules and the cold plate. To analyze the complicated interaction between the power losses and module junction temperatures, a closed-loop iterative estimation scheme is proposed to estimate the inverter power loss and module junction temperature. Based on the proposed thermal model and estimation scheme, a detailed optimization procedure on the selection of switching frequency and dc-link capacitor is presented to maximize power density. Furthermore, design optimization of the busbar was conducted to minimize the stray inductance, thus reducing the voltage overshoot during switching transients. Comprehensive experimental studies were performed on a physical converter prototype built based on the optimization results, which validate both the effectiveness of the presented design approach. [ABSTRACT FROM AUTHOR]

As a critical energy-conversion system component, power semiconductor modules and their layout optimization has been identified as a crucial step in achieving the maximum performance and density for wide bandgap technologies (i.e., GaN and SiC). New packaging technologies are also introduced to produce reliable and efficient multichip power module (MCPM) designs to push the current limits. The complexity of the MCPM layout is surpassing the capability of a manual, iterative design process to produce an optimum design with agile development requirements. An electronic design automation tool called PowerSynth has been introduced with on-going research toward enhanced capabilities to speed up the optimized MCPM layout design process. As a part of this continuing research, in PowerSynth v1.9, a constraint-aware layout engine has been developed, which enables integrating heterogeneous components, handling complex geometry, exploring a larger solution space, improved success rate, and providing options for multiobjective optimization algorithms. The layout engine is generic, scalable, and efficient in performing electro-thermal optimizations on both 2-D and 2.5-D power modules. To validate these enhanced design capabilities, a 2.5-D full-bridge power module layout is designed, optimized, fabricated, and tested with measurement results matching closely with model prediction. This result closes the loop in the power electronics design process with an experimentally validated module design automation flow. [ABSTRACT FROM AUTHOR]

In this article, an efficiency-oriented hybrid duty modulation (HDM) scheme is proposed for the dual active bridge (DAB) converter that can reduce the inductor root-mean-square (rms) current and extend the switch soft-switching range. First, a complete description of the combination forms of different modulation schemes is presented considering the allocation of the zero-voltage portion. A unified description for these combination forms is obtained in the frequency domain. Second, the symmetric–symmetric duty modulation (SSDM) scheme and asymmetric–symmetric duty modulation (A2SDM) scheme are established to minimize the inductor rms current by considering its fundamental component. Third, the characteristics of SSDM, A2SDM, and the traditional phase shift modulation schemes are compared from several aspects, mainly including the inductor rms current and the soft-switching performance. Furthermore, the loss breakdown analysis results for the three modulation schemes are presented and compared. According to these results, the HDM scheme is proposed to improve the overall efficiency of the DAB converter. Finally, an experimental prototype was built with a peak efficiency of 97%, which validates the effectiveness of the proposed modulation scheme. [ABSTRACT FROM AUTHOR]

The silicon carbide (SiC) devices have faster switching speed than that of the conventional silicon (Si) devices, which however may cause excessive device voltage overshoot. Larger gate resistance can help to restrain the overshoot, it however slows down the switching speed and increases switching losses. There are other methods that can mitigate the voltage overshoot, e.g., using low-inductance busbars, adding snubber circuits, etc. In this article, the busbar design for a 250-kW SiC three-level T-type inverter is investigated. The current commutation loops (CCLs) are first analyzed using a single-phase equivalent circuit. Then the detailed busbar design methods, especially a 3-D busbar design concept, are proposed to select the optimal stacking order for the multilayer laminated busbar and to address constraints posed by the physical terminal arrangements of SiC modules and dc-link capacitors. The stray inductance in each CCL is extracted via a finite element analysis and validated on the actual inverter busbar prototypes using an impedance analyzer. To further minimize the busbar stray inductance, a hybrid busbar structure with printed circuit board based buffer circuit using high-frequency decoupling capacitors is designed and evaluated in this article. Finally, the effectiveness of the designed busbars as well as the buffer circuit are validated using experimental studies. [ABSTRACT FROM AUTHOR]

The cascaded H-bridge (CHB) inverter is one of the most attractive multilevel topologies for renewable energy applications. Due to the fact that CHB inverters employ a large number of components, they suffer from a higher probability of fault, which reduces the system reliability. A fault-tolerant operation for a CHB inverter is described in this article. New features ensure reliable and robust operation of the converter in the event of a fault. The proposed strategy uses an additional cross-coupled CHB (X-CHB) unit in companion with the existing CHB units to support the output voltage and ensure continuity of operation in the event of an open/short-circuit fault. The operation of the proposed X-CHB inverter is described in detail. Simulation and experimental verification of the proposed concept are demonstrated using a seven-level CHB. Both simulation and experimental results confirm the fault-tolerant operation of the X-CHB for a battery energy storage system in case of switch faults. [ABSTRACT FROM AUTHOR]

With high-temperature power devices available, the support circuitry required for efficient operation, such as a gate driver, is needed as part of a complete high-temperature solution. The design of an integrated silicon carbide (SiC) gate driver using a 1.2-μm complementary metal–oxide–semiconductor (CMOS) process is presented. Adjustable drive strength is added to facilitate a minimal external component requirement for high-temperature power modules and lays the groundwork for dynamic adjustment of drive strength. The adjustable drive strength feature demonstrates a capability of reducing overshoot and controlling dv/dt dynamically. Measurement of the gate driver was performed driving a power mosfet gate over temperature, exceeding 500 °C. High-speed and high-voltage room temperature evaluation is provided, demonstrating a system capable of high performance over temperature. The driver accomplishes better than 75 ns of rise and fall time driving the Cree CPM3-0900-0065B from room temperature to over 500 °C indicating that it will be ideal for integration into an all-SiC power module where driver, protection circuits, and power devices are fabricated in SiC. [ABSTRACT FROM AUTHOR]

This paper presents functional high-temperature analog circuits in silicon carbide bipolar technology. The circuits will collectively form the analog signal conditioning block for a wireless telemetry system in an extreme environment (above 400°C). The signal conditioning block is composed of a low dc gain operational amplifier, a negative voltage charge pump (CP), an RC oscillator, and a voltage regulator. The circuits are tested up to 450°C. The measured open-loop gain for the amplifier at 450°C is 30 dB. The regulator provides approximately 9-V output at 450°C for a fixed load current of up to 18 mA and an applied reference of 4.5 V. The negative voltage CP requires an oscillating signal at its input, which is provided by the RC cross-coupled oscillator. The CP provides about −5 V at 450°C. [ABSTRACT FROM AUTHOR]

This paper presents a practical strategy for utilizing the submodule (SM) redundancy of a modular multilevel converter (MMC) for its fault tolerance. This strategy provides a systematic framework for balancing the tradeoff between two conventional methods for using the active redundancy and, thus, achieves operational flexibility. One of the existing methods improves SM reliability owing to less voltage stress on the SM components by employing all of the SMs to form the ac or dc voltages (voltage-sharing mode). The other avoids transients by keeping the average SM voltage constant at the cost of slightly increased stress on the SM components (fixed-level mode), which, however, can be controlled to provide the grid-adaptive operation by reserving the energy of the SMs not in service. We, thus, develop a new redundancy management scheme by integrating these two methods and exploiting their technical benefits to meet the PQ requirements and MMC control performance. This research provides a theoretical basis and a technical guide to determining the number of SMs, which can further increase the voltage steps as per the MMC and grid conditions. This paper also connects the remaining PQ capability of the MMC at a particular operating point with the SM redundancy concept by defining a potential redundancy, especially useful when the physical redundancy is exhausted. The theoretical findings and efficacy of the proposed strategy are validated through PSCAD/EMTDC time-domain simulations followed by experiments using a nine-level single-phase MMC system. [ABSTRACT FROM AUTHOR]

This paper describes a silicon carbide pulse width modulation (PWM) signal generator in the 1.2 μm HiTSiC CMOS process developed by Raytheon Systems Ltd. The design features a 6-b binary input, which allows for setting a system's duty cycle. The results presented in this paper utilize a field programmable gate array board in the test setup to dynamically set the duty cycle by controlling each bit. A control current is also available to give the user added flexibility for tuning the duty cycle. Experimental results show the duty cycle range of the PWM generator to be between 4.7% and 95.2% at 400 °C. Sustained operation of the circuit is demonstrated over a period of 50 h at 300 °C. Finally, the PWM generator is evaluated in the operation of a boost converter. [ABSTRACT FROM PUBLISHER]

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxidesemiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications. [ABSTRACT FROM AUTHOR]

A new design of stripline transition structures and flip-chip interconnects for high-speed digital communication systems implemented in low-temperature cofired ceramic (LTCC) substrates is presented. Simplified fabrication, suitability for LTCC machining, suitability for integration with other components, and connection to integrated stripline or microstrip interconnects for LTCC multichip modules and system on package make this approach well suited for miniaturized, advanced broadband, and highly integrated multichip ceramic modules. The transition provides excellent signal integrity at high-speed digital data rates up to 28 Gbits/s. Full-wave simulations and experimental results demonstrate a cost-effective solution for a wide frequency range from dc to 30 GHz and beyond. Signal integrity and high-speed digital data rate performances are verified through eye diagram and time-domain reflectometry and time-domain transmissometry measurements over a 10-cm long stripline. [ABSTRACT FROM AUTHOR]

Thin-film microstrip transmission lines fabricated using a Ti adhesion layer followed by layered Cu, Pt, and Au films are measured to determine tradeoffs between manufacturability issues and microwave performance. Since Ti metal has approximately 25 times the resistance of Cu, and currents in a microstrip line flow mainly at the interface with the substrate where the Ti is located, there is the possibility of increased RF signal losses with this structure. It is found that Ti adhesion layers of $\le 200$ -nm thickness cause minimal loss through 40 GHz on DuPont 9K7 low-temperature cofired ceramic substrates, so there is no significant electrical penalty for employing a metal stackup optimized for mechanical durability. These measurements, together with analysis and simulations suggest this will hold in general as long as the thinner, higher resistance adhesion metal is well below one skin depth in thickness at the operating frequency. [ABSTRACT FROM PUBLISHER]