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In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and scalable communication. Worth recalling in this regard is that our research team has already designed, verified and evaluated Multistage Interconnection Networks (MIN) in this field. With respect to the present work, we consider proceeding with further exploring our thoughts on this research area. Firstly, we propose the design and performance evaluation of a hybrid (wireless/wired) MIN, analysing how this augmented network can potentially improve not only the average delay, but also energy consumption. Secondly, we continue with examining the implementation of our advanced DELTA-based MIN architecture on Deep Neural Network (DNN) accelerators, while accounting for its potential regularity and scalability in simultaneously maintaining an effective power efficiency and lower latency throughout the DNN operating process. In this context, several metrics have been evaluated in regard to three DNN application cases through implementation of their main respective modules. [ABSTRACT FROM AUTHOR]

In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and scalable communication. Worth recalling in this regard is that our research team has already designed, verified and evaluated Multistage Interconnection Networks (MIN) in this field. With respect to the present work, we consider proceeding with further exploring our thoughts on this research area. Firstly, we propose the design and performance evaluation of a hybrid (wireless/wired) MIN, analysing how this augmented network can potentially improve not only the average delay, but also energy consumption. Secondly, we continue with examining the implementation of our advanced DELTA-based MIN architecture on Deep Neural Network (DNN) accelerators, while accounting for its potential regularity and scalability in simultaneously maintaining an effective power efficiency and lower latency throughout the DNN operating process. In this context, several metrics have been evaluated in regard to three DNN application cases through implementation of their main respective modules.

In the past few decades, the demand for high-performance computing has been increasingly growing. These systems usually employ many processing elements working together via interconnection networks to solve complicated problems. Due to the efficiency and cost productivity, multistage interconnection networks (MINs) are recommended for use in such systems. At the same time, shuffle-exchange networks (SENs) have extensively been used as a suitable solution to multistage interconnection networks, given the size of their switching elements and simple configurations. In this paper, parallel SEN (PSEN) is proposed to enhance the reliability of these networks. Moreover, PSENs with one and two more stages (PSEN+ and PSEN+2) are utilized to optimize the reliability factor. The reliability analysis of the proposed network is performed through the reliability block diagram. According to the evaluation results, PSEN achieved higher reliability compared to SEN in different aspects of reliability, such as terminal, broadcast, and network. The proposed network also improves the cost-effectiveness in comparison with other MINs. [ABSTRACT FROM AUTHOR]

Terminal reliability of multistage interconnection network (MIN) is the probability of at least one fault free path between any source–destination nodes pair. MIN is used to interconnect processors and memory modules in multi-processor system. In this paper, terminal reliability is estimated and validated for existing MINs (i.e., SEN, SEN+, SEN+2, GIN, CGIN, PCGIN, 3D-GIN, 4D-GIN-1, 4D-GIN-2, 4D-GIN-3, and SEGINs). The comparison and performance analysis of MINs based on various indices are also presented. [ABSTRACT FROM AUTHOR]

Interconnection networks provide communication among processors, memory modules, and other devices in parallel computer systems. The number of stages, interconnection topology, and the types of SE used in the network configuration differentiate each interconnection network. As an illustration, there are numerous aspects that are important in the development of interconnection networks. Reliability can be considered as an important factor to measure the performance in the network. The reliability for interconnection network depends on the reliability of its components. In this paper, we examine the various topologies of interconnection, communication protocol, and discuss reliability issues related to interconnection network. [ABSTRACT FROM PUBLISHER]

Interconnection networks are used for communication between nodes in multi-processor systems as well as super-systems. These systems require effective communication between the processor and memory blocks and therefore, interconnection networks are considered as the heart of the parallel processing and multi-processor systems. Multistage interconnection networks (MINs) are the main option for use in supercomputer environments that consist of thousands of processing elements. In this paper, a regular class of fault-tolerant MINs named Pars network along with its routing algorithm are presented. Analytical results demonstrate that the Pars network outperforms known regular networks, namely ABN, ASEN, EGN, and IEGN in terms of cost, fault-tolerance, terminal reliability, mean time to failure, and permutation capability. [ABSTRACT FROM AUTHOR]