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In recent years, digital pre-distortion has emerged as a powerful approach to compensate linear and non-linear imperfections of the transmitter. Previous solutions are either based on factory calibration or use a local auxiliary receiver. Here, we present a digital pre-distortion architecture to compensate transmitter frequency response and I/Q skew, which relies upon a feedback from the far-end receiver and uses the signal propagated over the optical link. The effectiveness of the proposed solution is validated over different transmission systems for dual-polarization 64 QAM net 400 Gb/s and 16 QAM net 200 Gb/s signals.

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm2.

In this paper, a cross-layer design for communication and control layers for wireless feedback control systems is considered, and an optimized receiver design for state feedback is proposed. The proposed receiver is designed on the basis of a maximum a posteriori probability decision and utilizes the control layer’s information, namely, the estimated state information of a Kalman filter-based state observer, as the a priori information of the transmitted state feedback. In addition, the proposed receiver provides the error covariance information of the received state feedback for the control layer. The recursive structure of the receiver and state observer is simple and suitable for the feedback control loop. The improvement in the channel error probability is supported by the control accuracy and vice versa. Numerical results show that the proposed receiver can effectively reduce the number of channel errors in the received state feedback and improve the control performance.

Complexity and computation effective design of multiport-based receiver system is proposed in this paper, and a simple calibration algorithm based on modified memory polynomial for the five-port receiver is used to demodulate the desired baseband signals from the received radio frequency signals. The theoretical foundation for the baseband signal recovery for the multiport system, basic circuit theory of the five-port receiver, and the proposed algorithm about how to retrieve the baseband signals from three output voltage signals are discussed. Finally, common modulated signals are used in the five-port receiver to validate the proposed calibration algorithm, and the measured performance in terms of error vector magnitude between the transmitted and the received signals are all less than 2%. Also, the performance comparison with the state-of-the-art multiport receivers is made to conclude that the five-port receiver with the proposed model can be one of the best cost and computation effective choices to accurately complete the signal recovery.

This paper presents a new all-digital transceiver architecture fully integrated into a single field-programmable gate array chip. Both the radio frequency (RF) receiver and the transmitter were entirely implemented using a digital datapath from the baseband up to the RF stage without the use of conventional analog-to-digital converter, digital-to-analog converter, or analog mixer. The transmitter chain uses delta-sigma modulation and digital upconversion to produce a two-level RF output signal. The receiver uses a high-speed comparator and pulsewidth modulation to convert the RF signal into a single-bit data stream, which is digitally filtered and then downconverted. Both the transmitter and the receiver are agile with flexible carrier frequency, bandwidth, and modulation capabilities. The transceiver error vector magnitude and the signal-to-noise ratio figures of merit were analyzed in a point-to-point transmission to evaluate the transmitter’s performance. The results show the feasibility of this approach as a more flexible alternative to common radio architectures.

A composite radio receiver back-end and digital front-end, made up of a delta-sigma analog-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter, are proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator (LO), followed by a rate-adjustable fractional sample rate converter for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A fractional sample rate converter is modeled and simulated with a cubic polynomial interpolator based on Lagrange method and its spectral-domain view is examined in order to verify its effect on al...

This brief presents an ultralow-power wake-up receiver using ultrasound for Internet of Things applications. To achieve both high sensitivity and low power consumption, we propose a Colpitts-oscillator-based super-regenerative receiver (COSR). Owing to the simple architecture of the proposed COSR, a lowest supply voltage operation of 0.3 V and a smallest area are achieved. Furthermore, the power consumption of the proposed wake-up receiver is scalable and is determined by the input signal sensitivity and data rate, which are configurable by the user. In a field test, the proposed wake-up receiver consumes $1~\mu \text{W}$ , which is smaller by 77% than that of a conventional ultrasound wake-up receiver at a comparable communication distance and data rate.

A novel tri-detector structure and signal processing method to suppress the local oscillator noise for optical heterodyne receiver is proposed. The tri-detector receiver adds a negative feedback loop and a photodetector compared with the traditional dual-detector receiver. Theoretical analysis shows: By use of proper signal processing technique the intensity noise of the local oscillator, which is not only in the direct current component but also in the intermediate frequency component, has been canceled completely.

An ultralow-power direct active RF detection wake-up receiver (WuRx) is presented. In order to reduce the power consumption and system complexity, a differential RF envelope detector is implemented in a complementary current-reuse architecture. The detector sensitivity is enhanced through an embedded matching network with signal passive amplification. A prototype receiver is fabricated in 0.18- $\mu \text{m}$ CMOS technology with a core size of 0.46 mm2. At the operating frequency of 2.4 GHz, the receiver achieves a −50 dBm sensitivity [10−3 bit error rate (BER)] at a data rate of 200 kbps while consuming $4.5~\mu \text{W}$ from a 0.8 V supply voltage. The WuRx is capable of achieving a 10−3 BER for 200 kb/s data rate with a signal to interference ratio greater than −30 dB at ±10 MHz offset.

We propose a crystal-free radio receiver exploiting a free-running oscillator as a local oscillator (LO) while simultaneously satisfying the 1% packet error rate (PER) specification of the IEEE 802.15.4 standard. This results in significant power savings for wireless communication in millimeter-scale microsystems targeting Internet of Things applications. A discrete time simulation method is presented that accurately captures the phase noise (PN) of a free-running oscillator used as an LO in a crystal-free radio receiver. This model is then used to quantify the impact of LO PN on the communication system performance of the IEEE 802.15.4 standard compliant receiver. It is found that the equivalent signal-to-noise ratio is limited to ~8 dB for a 75- ${\mu }\text{W}$ ring oscillator PN profile and to ~10 dB for a 240- ${\mu }\text{W}$ LC oscillator PN profile in an AWGN channel satisfying the standard’s 1% PER specification.

This paper presents an impulse-radio ultra-wideband (IR-UWB) receiver design for precise wireless ranging using a newly proposed direct sampling with time-extension (DTE) method. To overcome the problems encountered in high-speed sampling for impulse signals, the DTE method, which exploits the characteristics of an impulse, is proposed. The proposed method performs high-speed sampling only during the period when short pulses exist, and quantizes the sampled signal during the dead time where no pulses exist. The high-speed impulse signal can be easily digitized using low-speed analog-to-digital converter. We designed and fabricated the IR-UWB receiver using a 65-nm CMOS process. The measurement result shows a 1.9-mm resolution for indoor wireless ranging within a 1-m range. The receiver has a power consumption of 70 mW at 1.2 V and energy efficiency of 1554 nJ/pulse.

In multi-Gbps chip-to-chip signalling, the transmitter clock jitter limits the maximum possible data speed for a required Bit Error Rate (BER). If the communicating channel between transmitter and receiver is lossy and noisy, the waveform of the driven signal, detected at the receiver chip changes completely due to the properties of channel made of copper interconnect. The reflection noise, generated at various points of the channel due to impedance mismatch, makes identification of the signal very difficult at the receiver. Due to that, it is challenging to send high frequency signals (pulse width of 100 psec corresponding to > 10 Gbit / sec data rate) between two chips in manufacturable environment for high volume products with various process parameters. In this work, we have discussed two methods of defining threshold voltage of receiver chip by which it is possible to send a square pulse of 15 picoseconds or less width (that may corresponds to 66 Gbit/sec or more) over a unmatched lossy channel. The receiver chip of proposed method uses a comparator, which is fed by the received oscillatory signal (Signal-A) and RC delayed version (Signal-B) of it. In order to avoid needless switching at the output, we also have incorporated conventional comparator hysteresis loop such that the feedback path will control the threshold depending on the comparator output.

Pulse position modulation (PPM) has been used in the radio-frequency (RF) domain to achieve both low-dissipation requirements and provide precision ranging. In ultrawideband (UWB) architectures, it underpins an asynchronous receiver, multiple access environments, and interference-resistant transmission. When combined with frequency hopping (FH), it allows for an additional level of immunity to jamming and low probability of intercept. Realization of a FH-PPM transceiver poses a practical challenge, particularly in the UWB RF range. With UWB pulses reaching the multi-gigahertz range, FH adds to the effective bandwidth at which the receiver must be operated, exceeding the performance of a modern quantizer and digital demodulation backplane. This study describes a new photonics-assisted FH-PPM receiver architecture that rests on mutually coherent frequency combs. The performance of the new receiver was characterized by receiving and decoding an 80–Mb/s rate FH-PPM UWB signal.

This paper describes the design of a 25 Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current-boosting preamplifier with a dual-path time-interleaved integrating-type optical receiver, it provides 1:2 demultiplexing operation with a tolerance to lower bandwidth photodiodes. The bandwidth of current amplifier is chosen as $0.35\times $ operating data rate for maximizing the receiver signal-to-noise ratio. Experimental results show that the receiver can achieve 25 Gb/s operation when integrated with a 9 or 17 GHz GaAs photodiode. Input sensitivities in the two cases are -7.2 dBm (w/i a 9 GHz photodiode) and -10.8 dBm (w/i a 17 GHz photodiode), respectively, for a bit error rate of less than $10^{-12}$ . In addition, a single-tap decision-feedback equalizer (DFE) is embedded to compensate photodiode bandwidth and improve input sensitivity. Integrated with a low-cost 9 GHz photodiode, the input sensitivity and timing margin of the receiver are improved by 2 dB and 0.25 UI, respectively, after DFE compensation. By utilizing a current integrator and time-interleaved comparators, its energy efficiency is 1.13 pJ/b at 25 Gb/s under a 1.2 V power supply. Fabricated in a 40 nm bulk-CMOS technology, the core circuit occupies a chip area of 0.007 mm 2 only.

We consider a single-input-multiple-output (SIMO) system where power radiated from the transmitter is received and harvested at the receiver. In the proposed algorithm, we study the influence of Channel State Information (CSI) on the maximum harvestable power at the receiver along with the optimization of receiver architecture, adaptive transmit beam forming, and receiver operation policy. On keen observation of the output response, our simulations results show that adaptive transmit beam forming with optimal time allocation for channel estimation will be favourable for maximization of harvested energy.

The single-event transient (SET) response of a W-band (75–110 GHz) radar receiver front-end is investigated in this paper. A new technique to facilitate the SET testing of the high frequency transceivers is proposed and demonstrated experimentally. The entire radar receiver front-end, including the high frequency signal sources and modulators, were designed and fully integrated in 90 nm 300 GHz SiGe process technology (Global Foundries SiGe 9HP). Two-photon absorption (TPA) laser pulses were utilized to induce transient currents in different devices in various circuit blocks. The study shows how short transient pulses from the high frequency tuned circuits are propagated throughout the receiver and are broadened while passing through low-pass filters present at supply nodes and the low-pass filter following the down-conversion mixer, thus affecting the digital data at the output of the receiver. The proposed methodology allows the study of the effect of SETs on the recovered digital data at the output of the high frequency receivers, thus allowing bit error rate calculations. Comprehensive device and circuit level simulations were also performed, and a close agreement between the measurement results and simulation data was demonstrated. To the authors’ best knowledge, this is the first study of SET on full receiver at millimeter-wave (mmW) frequencies.

In this letter, we consider the control of an energy self-sufficient receiver in a multi-access network with simultaneous wireless information and energy transfer. Multiple trans- mitters send data to a common receiver whose only source of energy is a finite size battery which is recharged only from the energy harvested from incoming RF signals. The nodes access the channel randomly resulting in a packet collision when multiple transmitters simultaneously access the channel. The receiver takes samples from the received RF signal to calculate the probability of a collision. The objective is to maximize the receiver goodput subject to the instantaneous availability of receiver energy. We develop an asymptotically optimal dynamic control algorithm, where the receiver makes an energy harvesting or decoding decision according to the current channel measurements and battery level.

Large-scale multiple-input-multiple-output(MIMO) technology is drawing significant interest for the next-generation wireless networks. Traditional MIMO receiver architectures use multiple parallel receiver front ends with digitization at every element to support digital space-time array processing. The absence of analog/RF spatial interference mitigation in traditional digital MIMO receiver arrays results in a high dynamic-range requirement, and consequently, power-hungry analog and RF receiver front ends and analog-to-digital converters. This paper presents a scalable 65 nm CMOS 0.1–1.7 GHz spatio-spectral-filtering four-element MIMO receiver array with spatial notch suppression that protects the analog/RF circuits and analog-to-digital converters from spatial interference early in the signal chain. The combination of spatial and spectral filtering results in more than 19 dB rejection irrespective of the frequency at which the spatial blocker is located. The proposed spatial notch suppression technique improves the measured in-band OIP3 from –10 to +24 dBV, and the measured out-of-band IIP3 from +11 to +18 dBm. Furthermore, turning on the spatial notch suppression leads to minimal noise figure degradation. The proposed chip architecture is scalable on board without the need for RF interconnections. A wireless imaging demo shows two of the implemented integrated circuits tiled on board to form an eight-element MIMO receiver array that is able to detect a weak desired signal in the presence of an in-band 15 dB stronger spatial blocker.

This paper proposes a technique to characterize and postcompensate for the dynamic nonlinearity exhibited by radio frequency (RF) receivers employed in passive intermodulation (PIM) and weakly nonlinear devices characterization (low gain compression of the order of 0.1 dB). The proposed technique begins by accurately characterizing the RF receiver’s nonlinearity using two-tone and multitone stimuli with swept frequency spacing and input power level. Then, a pruned Volterra series-based postcompensation model is devised to mitigate the dynamic weak nonlinear distortions exhibited by the receiver. The technique was validated in two steps. First, the capacity of the postcompensation technique to separate the RF receiver’s intermodulation from the device under test’s intermodulation was assessed. Second, its capacity to postcompensate for the dynamic nonlinearity exhibited by the RF receiver and to enhance its spurious-free dynamic range (SFDR) was assessed using digitally modulated stimuli. The application of the proposed technique reduced the third-order intermodulation (IMD3) of the RF receiver by an average of 10 dB. This technique can significantly relax the requirements on duplexers and tone injection techniques used to enhance the accuracy of PIM measurements. Furthermore, the receiver’s SFDR was extended by up to 15 dB.

Passive RF identification (RFID) readers transmit a continuous wave (CW) powering signal to remotely power up batteryless transponders, while simultaneously receiving a backscattered signal at the same frequency [1]. To separate the transmitter and receiver paths, readers use either a bistatic or monostatic antenna configuration. The first configuration employs two separate antennas, one to transmit and one to receive; in the second, the transmitter and receiver share a common antenna by means of a coupler or circulator. Both cases, however, suffer from poor transmitter-to-receiver isolation: strong CW signals can leak into the receiver, degrading its sensitivity to the weak transponder backscattered signals. Receiver sensitivity degradation occurs due to the leaked local oscillator (LO) phase noise [1] and also to the saturation of the front end caused by strong CW leakage. This requires high-dynamic-range capability in the RF stage [the low-noise amplifier (LNA) and mixer] as well as in the baseband stage [the amplifiers and analog-to-digital converters (ADCs)].

A low-power low-voltage CMOS receiver architecture with a combined LNA-VCO-mixer structure is proposed. An inversion-coefficient (IC) based design procedure is presented that facilitates finding a power-efficient operating point for the low-noise amplifier (LNA) and the voltage-controlled oscillator (VCO) blocks. At the architecture level, the bias currents of LNA and mixer are combined, filtered, and reused for the VCO. This approach facilitates lowering the supply voltage and improves the power efficiency of the system. As a proof of concept, a 2.4GHz receiver suitable for wireless sensor network applications is designed and fabricated in a 0.13-m CMOS process. The receiver has an intermediate frequency (IF) of 50MHz. The RF-to-IF gain of the receiver is 30.1dB and its noise figure (NF) is 8.3dB. The combined LNA-VCO-mixer receiver consumes 510W from a 0.8-V supply.

The Direct RF-to-Digital $\Delta\Sigma$ receiver has emerged as an attractive solution for multi-band multi-standard wireless applications. This architecture is a direct RF to baseband digitizer with RF feedback from baseband to RF stages. The presence of the RF blocks such as the low noise amplifier and down-conversion mixer inside the loop filter significantly relaxes their linearity requirements and also improves the noise transfer function of the loop filter. However, the RF feedback poses several challenges, especially making the design methodology more complex. In contrast to classical receiver architectures, the blocks of the Direct RF-to-Digital $\Delta\Sigma$ receiver cannot be designed, analyzed, and simulated independently. Besides, conventional design methodologies for $\Delta\Sigma$ Modulators cannot be applied for this kind of receiver due to the presence of the RF blocks and the RF feedback inside the loop. This paper presents a new design methodology suited for this family of receivers. The proposed methodology covers simulation approaches, system design, and non-ideality impacts on the receiver. A design example of a multi-band multi-standard receiver for GSM/WCDMA/LTE is considered throughout the paper to demonstrate this design methodology.

A highly efficient receiver architecture for intraband contiguous carrier aggregation (CA) is described. The downconversion architecture is done in two stages; the first stage is done in the analog domain using a direct-conversion receiver, whereas the second stage is done in the digital domain using offset frequency digital mixing to separate the carriers. The novelty in the architecture stems from its ability to compensate for the different carrier frequency offsets (CFOs) between the two transmitted carriers, and unlike traditional approaches, the receiver uses a single complex digital mixer for baseband carrier separation. The receiver architecture also compensates for in-phase and quadrature gain and phase imbalance (IQI) inherent in direct-conversion receivers. It is shown that, in our new architecture, IQI compensation can be done post the digital mixer, thus enabling a low-power implementation to this impairment.

A 2.4 GHz interferer-resilient wake-up receiver for ultra-low power wireless sensor nodes uses an uncertain-IF dual-conversion topology, combining a distributed multi-stage N-path filtering technique with an unlocked low-Q resonator-referred local oscillator. This structure provides narrow-band selectivity and strong immunity against interferers, while avoiding expensive external resonant components such as BAW resonators or crystals. The 65 nm CMOS receiver prototype provides a sensitivity of −97 dBm and a carrier-to-interferer ratio better than −27 dB at 5 MHz offset, for a data rate of 10 kb/s at a 10−3 bit error rate, while consuming 99 $\mu \text{W}$ from a 0.5 V voltage supply under continuous operation.

In this paper, the injection-locked oscillator (ILO)-based receiver is investigated. The key design considerations of the ILO including the phase difference between the input and output signals and its impact on the ILO-based receiver are analysed in detail. Different strategies for both the narrow and wide-band applications are discussed and simulated. As a design example, a 2.4 GHz ILO-based receiver is implemented using a standard 40 nm CMOS technology, where a three-stage inverter-based ILO is optimised to maintain a good balance among working range, sensitivity and power consumption, etc. Measurement results show that the proposed receiver is able to demodulate an input signal at a 2.4 GHz carrier frequency with the data rate up to 1 Mbps while consuming $${

The effects of the electrode interface on a receiver sensitivity in a body channel communication (BCC) are studied to clarify the characteristics of the electrode interface in the BCC, and revisit the noise and sensitivity analysis against the conventional method exploited in a radio frequency (RF) communication. First, the paper describes the noise characteristics in the electrode interface and examines the relationship between the noise and the contact impedance in the BCC frequency region. Then, we introduce a sensitivity analysis method dedicated to the BCC receiver by means of a receiver gain and an output noise spectral density. To verify the sensitivity analysis method, we implemented a direct conversion BCC receiver in 0.18µm CMOS technology. By measuring the gain, output spectral density, and sensitivity of the receiver with respect to the various source impedance values, we found that the calculated value through the proposed analysis method agrees well with the theoretical value within 2.5dB difference.

This paper presents a wideband quadrature radio receiver employing $\Delta \Sigma $ -based A/D-converting channel-select filters (ADCSFs). The output of the quadrature passive mixer is directly connected to the input of the ADCSFs, where a first-order $\Delta \Sigma $ modulator is incorporated into a fourth-order Butterworth channel-select filter (CSF) to provide sufficient dynamic range for a cellular system. A design methodology for the ADCSF is derived, where the transfer function of the CSF is preserved. The 65 nm CMOS receiver has a frequency range of 0.6–3.0 GHz and can be programmed to support the 2xLTE20, LTE20, and LTE10 bandwidths. The receiver noise figure varies from 2.3 to 3.9 dB, with a current consumption in 2xLTE20 mode between 33 mA at 0.6 GHz and 44 mA at 3.0 GHz from a 1.2 V supply, including 10–21 mA for LO phase generation and distribution. The SNDR is 47–51 dB at an LO frequency of 1.8 GHz.

In simultaneous wireless information and power transfer (SWIPT), practical receiver architectures consisting of an information receiver and an energy harvester have been proposed in place of an ideal receiver capable of performing two tasks simultaneously using the same circuits. In this paper, we present a novel receiver architecture design incorporating an interplay between the information receiver and the energy harvester to enhance the performance of the practical SWIPT receiver. In particular, the energy level of the received signal monitored at the energy harvester is fed back to the information receiver to assist information decoding at the information receiver. The symbol-error-rate (SER) and diversity analyses show that the proposed receiver architecture could yield a higher diversity order for unconventional constellations where any two distinct symbols have distinct energy levels, and the same diversity order for conventional modulations. Simulation of PAM and QAM modulations verifies the analysis, shows the improved SER performance of the proposed receiver architecture, and illustrates the energy-dimension-augmented decision regions. Some insights into designing enhanced practical SWIPT receivers are provided as a result.

The design of a fully integrated multi-standard UHF receiver front-end to be embedded in environmental data collection satellites is proposed. The circuit operates under the requirements of both SBCDA and the ARGOS 3. For that, the specifications of a multi-standard receiver front-end are firstly derived and then the implementation of a 70.4 dB voltage gain, 2.3 dB NF, 48 mW energy consumption, single-ended input and differential quadrature output receiver front-end in 130-nm CMOS standard technology is presented. The design is validated through post-layout simulation.

This work presents a receiver capable of receiving three simultaneous cellular channels with an aggregate bandwidth of 60 MHz, enabling a 300 Mb/s downlink rate. The receiver has 16 RF LNA ports covering the cellular bands within the 572–2700 MHz frequency range. It supports LTE-advanced Rel-12 Cat6, HSPA+ Rel-11, TD-SCDMA Rel-9, and GSM/EDGE Rel-9. The 40 nm CMOS receiver consumes 13.7 and 17.6 mA of battery current in 3G and LTE modes, respectively, including the PLL, DCXO, and biasing for a single channel.

International audience; This article presents a novel visible light communications receiver architecture, designed for automotive applications. A central problematic in this area is the design of a suitable receiver able to face the problems caused by the dynamic situations, by the long distances and also by the environmental conditions. In such circumstances, a solution would be to adapt the communication's data rate to channel conditions, meaning that the communication would take place using different data rates depending on the signal to noise ratio (SNR) and the message priority. Considering the digital filtering better performances, the proposed architecture considers the usage of digital signal processing (DSP) as an alternative to the analog signal treatment. The visible light communication receiver proposed in this article addresses the upper mentioned issues and enables a robust communication even at low SNR.

A pulsed ultrawideband (UWB) transceiver with four-element receiver beamforming is described. Multiband signaling with frequency hopping is employed to efficiently utilize spectrum from 6 to 8.5 GHz to achieve a high data rate of 1 Gbps. A pulse-based signaling approach with low implementation complexity is utilized. Frequency-hopping reduces the overhead for multiband implementation by sharing multiple circuit blocks in the transmitter and receiver paths. The sinusoids for pulse-shaping and single-sideband mixing are synthesized using multiphase LOs to avoid high-speed DACs. The receiver channelizes the spectrum with cascaded mixers for which the LO signals are derived from a single PLL. A single-input multi-output (SIMO) beamforming architecture is employed to increase the sensitivity of the receiver. Beamforming is performed at baseband to avoid the requirement for a wideband delay circuit. The prototype is implemented in 65 nm CMOS and meets the ECC mask. The measured power dissipation of the transmitter is 221 mW, while that of the receiver is 211 mW. A receiver sensitivity of $-$ 69 dBm is achieved and Gbps communication over 2 m is demonstrated.

In an access network based on a passive optical network architecture, coherent detection is attractive since it allows for high receiver sensitivity coupled with inherent frequency selectivity. Nevertheless, solutions employed in core networks are prohibitively complex and costly, requiring the optical complexity of the coherent receivers to be reduced to make them feasible for access networks. For monolithic integration, a key challenge is posed by the polarization beam splitter (PBS). If, however, the PBS is removed, the receiver needs to be redesigned to be insensitive to the incoming polarization state of the received signal. In this paper, we experimentally demonstrate a polarization-insensitive (i.e., polarization-independent) coherent receiver for the optical network unit in passive optical networks (PONs). The receiver consists of only a 3-dB coupler and a single-balanced photodiode such that the complexity is comparable to a direct detection receiver. The proposed cost-effective coherent receiver is implemented by using the Alamouti polarization-time block coding scheme combined with heterodyne detection. To verify the technique, the Alamouti-coded orthogonal frequency division multiplexing (OFDM) signal is rotated over the full Poincare sphere. Compared to the dual-polarization-OFDM signal operating at a net bit rate of 10 Gb/s per polarization (a gross bit rate of 10.7 Gb/s including a 7% FEC overhead), only a 0.6 dB sensitivity degradation is observed. The sensitivity at the FEC threshold, assumed to be $4\times 10^{-3}$ , is measured to be $-$ 41.5 dBm (56 photons-per-bit) on a 25-GHz grid. Following this, different channel spacings are investigated and the signal is transmitted over 80 km of standard single-mode fiber in a long-reach wavelength division multiplexed PON system. The loss budgets are found to be 43.0 and 42.8 dB for 50- and 25-GHz grids, respectively.

Modern wireless devices require a compact wireless receiver that can access all the available services with fewer bulky off-chip passive components. This advocates the need for multi-band multi-standard receivers. This paper proposes a reconfigurable such receiver front-end controlled by its driving clocks. The receiver adopts charge sampling and impedance translation techniques. Its driving clocks are adjusted based on the targeted frequency. The receiver is tested over the existing standards specifications: GSM 2G (850MHz, 900MHz, 1.8GHz and 1.9GHz), UMTS 3G (850MHz, 1.8GHz, 1.9GHz and 2.1GHz), Bluetooth (2.4GHz) and LTE (700MHz?5GHz) and Wi-Fi (2.4GHz and 5GHz). The proposed front-end architecture achieves NF of 8dB, out-of-band IIP3 of 0dBm and in-band IIP3 of -5dBm across the tested frequencies in 65nm CMOS technology. The design occupies 0.45mm2.

This paper introduces an optimized receiver architecture using the current-reuse technique to improve receiver sensitivity while minimizing power consumption. An ISM band wireless receiver with OOK modulation was implemented in the TSMC 0.18-µm CMOS process. The receiver contains an RF front end, an LC-tank based LO VCO, an IF amplifier and an OOK demodulator. In addition, the IF amplifier features a self-mixing elimination mechanism which allows the BER to upgrade more than one order of magnitude. Measurement results show a sensitivity of -63dBm given a BER of 10-3. Using the gain-improving method, the sensitivity is improved by 4dB 100-kbps data rate. Including the bias circuit, overall power consumption is less than 383µW under a 1.2-V supply, providing an alternate solution for wireless radio applications. Copyright © 2016 John Wiley & Sons, Ltd.

In this paper, a receiver for wireless power transfer is proposed. The receiver consists of a 100 W rectifier in 1.8 MHz frequency band, and a constant current charger. In particular, two kinds of protection circuits are installed in the rectifier. They are a over-voltage protection circuit which block the input voltages greater than 30 V and a active-dummy load which maintains the receiver input impedance by automatically consuming the remaining input power. The constant current charger is designed to charge the battery with a charging current of up to 1 A. A wireless charging system is fabricated using the proposed receiver. The system is composed of a 130 W transmitter, two magnetic resonator, and proposed receiver for charging a 48 V Li-Ion battery using the coupled magnetic resonance method. By the measurement result, the system efficiency is about 54 %.

The paper proposes a low power non-volatile baseband processor with wake-up identification (WUI) receiver for LR-WPAN transceiver. It consists of WUI receiver, main receiver, transmitter, non-volatile memory (NVM) and power management module. The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique, which increases the robustness and energy efficiency of receiver. The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver. The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode. The baseband processor is designed and verified on a FPGA board. The simulated power consumption of processor is 5.1μW for transmitting and 28.2μW for receiving. The WUI receiver technique reduces the average power consumption of transceiver remarkably. If the transceiver operates 30 seconds in every 15 minutes, the average power consumption of the transceiver can be reduced by two orders of magnitude. The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

Accurately characterizing the wireless small-scale fading channel has been a challenging task in the wireless communication era due to the surrounding environment. Therefore, this paper introduces a new technique to experimentally characterize the small-scale fading taking under consideration real environmental conditions. By conducting a two dimensional measurement while the mobile receiver is moving; a more accurate channel will be achieved. Two-dimensional measurement refers to collecting data from the receiver along the x and y direction. The two-dimensional measurement data contain far more information than a one-dimensional data collected. In order to represent the small-scale channel along with the real environmental conditions, new approaches are necessary to configure the two-dimensional system and to analyze the 2D data. The new approach this paper introduces for the characterization is that the measurements are conducted on a receiver while it is moving in a two dimensional manner, under different scenarios, Line-of-sight, Non-line-of-sight, and Two-wave-Diffuse Power. The experiment was conducted in a 7 meters long by 4 meters wide room, wherein the distance between the transmitter antenna and receiver is about 3 meters. Those scenarios represent different real-time conditions where obstacles differ from one scenario to another. For example, the line of sight scenario assumes there a clear line of sight between transmitter and receiver, Non line of sight assumes many obstacles between the transmitter and receiver, i.e. walls, cabinets, etc. and Two Wave Diffuse Power assumes a metallic reflector surrounding the receiver. The experiment showed more accurate results when compared to the one dimensional measurement that has been done in the past where receiver is moving in one direction and also receiver being fixed where a constructive and destructive interference is not captured. The two dimensional measurement technique, i.e. capturing data while receiver moving in both x and y directions, provided essential information regarding the constructive and destructive interference patterns caused by the interaction between the receiver while moving and the obstacles surrounding the receiver.

A simple and effective technique is presented to reduce the limit-cycle oscillation (LCO) in the reconfigurable rectifier for wireless power receiver. It is theoretically analysed that only one switching edge of the switching signal is needed to be synchronised and a phase-shift circuit is proposed for synchronisation. Simulation results in commercial 0.18 µm CMOS technology show that the LCO is greatly suppressed with the proposed synchronisation circuit and the output voltage ripples are much smaller compared to the conventional circuit.

This letter presents a wideband 240-GHz direct-conversion receiver manufactured in a 130-nm SiGe:C BiCMOS technology with $f_{T}/f_{\text {max}}=300$ /500 GHz. A mixer-first receiver is implemented, with a new dc offset cancellation loop architecture to compensate for the mixer dc offsets and biasing purposes. A transimpedance amplifier is utilized as a load for the mixer, optimized with the dc offset cancellation loop to maximize the bandwidth. A local oscillator (LO) chain that multiplies by 8 a 30-GHz input signal drives the mixer. The proposed receiver achieves the widest 3-dB bandwidth among the published works of 55 GHz, with a conversion gain of 13 dB. The measured average single-sideband noise figure is 18 dB. It dissipates 500 mW, while occupying 1.25 mm2, requiring LO input signal of only −10 dBm.

For high speed ultra-wideband (UWB) communication systems, the multipath interference exhibits a primary obstacle to improve transmission performance. In order to enhance the signal to interference plus noise ratio (SINR) in the receiver, a partial template receiver is proposed in this paper. Instead of using the conventional template, the model in this paper adopts a partial template to demodulate signals. To analyze the performance of the proposed receiver, bit error rate (BER) formulation of IR-UWB systems in the presence of multipath interference, multiuser interference and addictive white Gaussian noise (AWGN) is derived in IEEE 802.15.4a channel models. Simulation results show that, compared with the conventional correlation receiver, the proposed receiver can achieve a better BER performance for high Eb/N0, which falls in the conventional used Eb/N0 range., 4 pages, 5 figures, Communications and Networking in China (CHINACOM), 2011 6th International ICST Conference on

This paper presents an ultra-low power, high-sensitivity, and interference-resistant receiver suitable for IoT applications. By the combination of sliding-IF based low-power down-conversion and relative-power-detection based FSK demodulation, the proposed receiver achieves multi-channel operation and minimizes power consumption. Cascaded N-path filter and 4th-order hybrid-PPF are adopted to improve the sensitivity and carrier-to-interference ratio. Implemented in a 65nm CMOS, the receiver achieves −102dBm sensitivity at 0.1% BER and 25kb/s data rate while consuming 466μW from a 0.6V supply.

Most of the optoelectronic integrated circuits (OEICs) described in this book are analog circuits. We, therefore, will restrict ourselves to the design of analog integrated circuits. The exclusion of the design of digital integrated circuits, furthermore, seems to be justified because there are many books describing this topic (for instance [232–234]). The design of analog integrated circuits is, for instance, described in [235]. It will be, therefore, sufficient to give here an overview on the aspects being most relevant for the design of analog OEICs. Since photocurrents have to be converted to signal voltages in most applications, the transimpedance amplifier will be discussed in some detail, especially with respect to its implementation in OEICs. A new π model for such a transimpedance amplifier also will be introduced. Furtehrmore, the basics of electronic noise and sensitivity of optical receivers are applied to point out the possibilities of silicon OEICs.

A software-defined radio receiver that is suitable for intra-band carrier aggregation is demonstrated. The RF front-end frequency selectivity is enhanced by the combination of the passive mixer and a proposed reconfigurable transimpedance amplifier. High order bandpass filtering function with frequency notches can be achieved at the front-end. Current domain complex signal processing is explored to select and separate multiple channels concurrently. The receiver contains a variety of functional building blocks that can be connected in different ways to form various architectures. The fine-grained programmability of component parameters and reconfigurability of receiver schemes enable optimum performance under varying signal and blocker scenarios. A proof-of-concept CMOS chip fabricated in a 65 nm CMOS technology is presented that supports up to three-channel aggregation. The receiver operates at any frequency between 0.5 to 3 GHz. The frequency separation between the concurrent RF channels can be tuned anywhere between 0 to +100 MHz. The concurrent receiver scheme can also be explored to reject large near-band blockers for high dynamic range.