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This article deals with the monolithic integration in silicon of a multiphase static power converter (dc/ac or ac/dc) for medium power applications, from few kilowatts to few tens of kilowatts with power devices’ blocking capability in the range of 600–1200 V. This article presents an original three-chip integration approach that combines both monolithic integration in silicon and printed circuit board (PCB) packaging process and takes advantage of both silicon-level technology and PCB-level technology within a limited and well-mastered complexity. The converter is integrated within only three new multiterminal power chips, which are then judiciously packaged on a PCB so as to minimize the switching cell stray inductance and the impact of voltage variations (dv/dt) across the common-mode stray capacitance of the assembly. The static and the dynamic operating modes of the proposed multiterminal power chips were validated using 2-D-Sentaurus TCAD simulations. The realized chips were packaged on a PCB to realize both classical and three-chip-based H-bridge inverters. First characterization results validate the electrical operating modes of the H-bridge inverter realized according to the three-chip approach. [ABSTRACT FROM AUTHOR]

This paper deals with a hybrid fault-tolerant converter topology. It is performed through the connection of a classical three-phase three-level neutral-point-clamped (3L-NPC) converter with a fourth three-level flying capacitor (3L-FC) leg. The 3L-FC leg actively balances the 3L-NPC neutral-point voltage. For normal operation mode, this paper proposes a mathematical design of the filter needed to connect these two different topologies. Experimentally, and thanks to the already existing decoupling capacitors of the 3L-NPC converter, this filter requires the addition of only one low size inductance. When one fault of the power switch of the 3L-NPC occurs, this paper proposes a hardware reconfiguration technique based on only two fuses and one thyristor per leg allows a safe postfault operation recovery. This is achieved thanks to a simple fault-detection method and a new technique that combines fault leg isolation and corresponding phase postfault connection to the neutral point. Also, a dedicated field-programmable gate array (FPGA)-based control of the reconfigured converter is synthetized to ensure power system availability under fault operation mode. The converter fault-tolerant capabilities are addressed through simulation results and original overall experimental validations of the fault detection and isolation and the postfault operation steps, carried out on a 15-kW prototype converter. [ABSTRACT FROM AUTHOR]

This paper deals with the monolithic integration of a multiphase generic static power converter (dc/ac or ac/dc). The integration aims at minimizing wire bonds in order to improve the electrical performance as well as the reliability of power converters. To that end, three multiterminal monolithic power Si chips are devised and extensively studied by 2-D simulations. The first power chip integrates the reverse-conducting IGBT devices that compose the high-side part of the converter circuit. This chip is called the common anode and is validated through experimental realizations. The second power chip integrates the reverse-conducting IGBT devices that compose the low-side part of the converter. This chip is called the common cathode chip. The common anode and cathode power chips are judiciously packaged on a Printed Circuit Board substrate over which an insulating Kapton film is laid and through which window openings are realized. The partial flip-chip packaging, of the two power chips, enables the realization of a compact power H-bridge converter with the lowest stray inductance. The third chip integrates the power converter within a single silicon chip and, consequently, eliminates wire bonds. It is considered as the ultimate integration approach. The latter is validated on a monolithic H-bridge inverter by using Sentaurus mixed-mode 2-D numerical simulations. [ABSTRACT FROM AUTHOR]

This article shows both theoretical and experimental analyses of a fully integrated CMOS active gate driver (AGD) developed to control the high dv/dt of GaN transistors for both 48 and 400 V applications. To mitigate negative effects in the high-frequency spectrum emission, an original technique is proposed to reduce the dv/dt with lower switching losses compared to classical solutions. The AGD technique is based on a subnanosecond delay feedback loop, which reduces the gate current only during the dv/dt sequence of the switching transients. Hence, the dv/dt and di/dt can be actively controlled separately, and the tradeoff between the dv/dt and EON switching energy is optimized. Since GaN transistors have typical voltage switching times on the order of a few nanoseconds, introducing a feedback loop from the high voltage drain to the gate terminal is quite challenging. In this article, we successfully demonstrate the active gate driving of GaN transistors for both 48 and 400 V applications, with initial open-loop voltage switching times of 3 ns, due to a full CMOS integration. Other methods for dv/dt active control are further discussed. The limits of these methods are explained based on both experimental and simulation results. The AGD showed a clear reduction in the peak dv/dt from –175 to –120 V/ns for the 400 V application. [ABSTRACT FROM AUTHOR]