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This paper presents radiation hardened SRAM (namely LPDNUR and HSDNUR), both of which can self-recover from single-node and double-node upsets. LPDNUR uses a two-input C-element structure, which reduces the average power consumption because the stacked effect. Moreover, in order to reduce read access time (RAT) and write access time (WAT), the paper proposes HSDNUR, which uses a combination of NMOS and PMOS as the transistor for one-node data transmission, an approach that increases the current drive capability and reduces transmission delays. Compared to the state-of-the-art radiation-hardened SRAM design, such as QUCCE10T, QUCCE12T, We-Quatro, etc. The model results show that the average power consumption of LPDNUR is reduced by 24.59% on average, and the RAT and WAT of HSDNUR are reduced by an average of 35.71% and 24.14% respectively. • LPDNUR and HSDNUR fully achieve SNU and DNU recovery. • Average power of LPDNUR is 24.59% lower on average than other SRAM hardened since stack structure. • WAT and RAT of HSDNUR are 24.14% and 35.71% lower than other SRAM hardened on average by using TG. [ABSTRACT FROM AUTHOR]

Content addressable memory (CAM) is a hardware search engine (HSE) used for accelerating lookup functions in tagged cache, translation lookaside buffers (TLBs) and network routers. Despite its speedy search feature, augmentation of compare-evaluate blocks to storage units costs additional area. Activation of cells and matchlines (MLs) during search operations is responsible for huge dynamic-power dissipation. This paper proposes a shared ML scheme (SMS) based on a two-step evaluation CAM cell, in order to reduce ML transitions per word besides improving density in the comparison units. A 64 × 32-bit proposed SMS-CAM, using 45-nm CMOS technology, dissipates 1.06 fJ/bit/search and achieves 100.77-ps search time. At the cost of 6.55% sacrificial delay over a conventional CAM, the proposed CAM reduces 12.38% – 30.48% energy over a self-power off gating, the conventional and an early terminate ML precharge designs. Low energy-delay results better trade-off budget besides decreasing macro area in the SMS-CAM, which could be useful in search applications of network devices. • A 2-bit storage with common evaluation (2B-CE) involving two-step comparison • Two side-by-side CAM cells (one 2B-CE based cell) share one matchline (ML) node • Shared matchline scheme limits ML discharge to only 1 path per 2-bit mismatches • Lesser ML discharge paths with shared matchline scheme (SMS) saves dynamic power • N/2 proposed 2B-CE cells are designed in NOR-type ML to form an N-bit CAM word • SMS-CAM sustains high-speed searches owing to the parallel cells in NOR-type ML • Comparison of SMS-CAM with referred CAMs verifies performance and reliability [ABSTRACT FROM AUTHOR]

This paper proposed a 12-bit 2.5-bit/phase two-stage cyclic Analog-to-Digital Converter (ADC) with phase scaling and low-power Sub-ADC for CMOS image sensors. The phase scaling technique reduces the performance requirements of operational amplifiers for the cyclic ADC. Furthermore, the Sub-ADC architecture based on tri-state comparators reduces the power consumption of the Sub-ADC. The implemented cyclic ADC is designed with 110 nm process. Simulation results demonstrate that the proposed 12-bit, 1 MS/s, 2.5-bit/phase, two-stage cyclic ADC achieves an effective number of bits (ENOB) of 11.4-bit with a power consumption of 0.185 mW per column. Compared with the traditional fixed phase structure, the power consumption of the phase scaling structure is reduced by 22.3 %. Additionally, the cyclic ADC attains a Figure of Merit (FoM) of 68.5fJ/step. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient CMOS image sensor (CIS) for always-on object detection by using 1-bit log-gradient feature extraction in analog current domain. Compared with traditional image sensors with high-resolution ADCs, the proposed CIS extracts gradients in ratio form and generates feature maps at 1-bit resolution, which eliminates unnecessary background information and illumination-related data, and reduces the data computation in the later detector. The system containing the proposed CIS and back-end ANN detector is modeled with python and the simulation achieves an accuracy of 93.2 % for person detection. The CIS employs current mode divider and comparator to compute the gradient ratios. An accurate and configurable muti-input and muti-output (MIMO) current divider is proposed, composed of two cascaded modified second generation current controlled conveyors (M-CCCIIs). The proposed CIS was fabricated in a 0.18 μm standard CMOS process and realized a frame rate of 170 fps and an energy efficiency of 337 pJ/pixel in a power consumption of 1.1 mW. Experimental results show that the proposed CIS can realize the function of extracting log-gradients. [ABSTRACT FROM AUTHOR]

This paper proposes a 4th-order class-AB low-pass filter (LPF) for wearable biological healthcare applications designed by cascading two 2nd-order LPFs. The proposed class-AB LPF uses quasi-floating gate (QFG), flipped source follower (FSF) and level-shifter (LS) techniques to boost its performance. The LPF is designed and validated in CMOS 180 nm technology which emulates the post-layout gain of −0.212 dB, bandwidth of 100 Hz, dynamic range (DR) of 50.26 dB, total harmonic distortion (THD) of −52.5 dB and figure of merit (FOM) of 1.71 × 10-15 J. The class-AB QFG FSF LPF consumes power and area of 0.224 nW and 0.0196 mm2, respectively. Furthermore, the statistically determined coefficient of variation for proposed LPF with 1000 iterations for gain is −0.035, THD is −0.172 and DR is 0.04, respectively. The class-AB QFG FSF LPF is compared with other LPFs which establishes its advantage in terms of low-power consumption and least figure of merit thus confirming its suitability for wearable healthcare applications. [ABSTRACT FROM AUTHOR]

This paper presents a 10 bits low-power direct digital IF to RF digital-to-analog (RF-DAC) fabricated in a 110 nm CMOS technology with a core area of 0.08 mm 2. The DAC uses sixteen current mode double balanced mixers designed without a tail transistor with different weights to convert IF output to RF output. The digital IF signal is modulated by a digital Σ − Δ modulator with 1-bit IF output. The RF-DAC with a bandwidth of 300 KHz consumes 17.3 mA from a 1.5 V supply. [ABSTRACT FROM AUTHOR]

In this paper, a new low-power full-adder circuit based on the proper combination of dynamic logic style and Gate Diffusion Input (GDI) low-power technique is proposed in Carbon Nanotube Field Effect Transistor (CNFET) technology. Using the proposed approach, the basic logic circuits such as XOR and XNOR gates are implemented which results in a full-swing, full-adder cell in the CNFET technology. The proposed circuit is simulated in HSPICE using CNFET model parameters. Finally, the simulation results justify a good improvement in the major circuit performances such as power consumption, delay and power-delay product (PDP) parameters for the proposed full-adder circuit. • A new Dynamic-GDI Low-Power Full-Adder circuit in CNFET technology is presented. • The design is based on the proper combination of Dynamic and GDI logic design techniques. • The proposed design not only significantly reduces the power consumption, but also reduces the PDP and layout area considerably. • The performance of the proposed circuit is simulated in HSPICE, using the STANFORD CNFET model parameters. [ABSTRACT FROM AUTHOR]

Modern battery-enabled systems, such as IoT, require SRAM cells that can maintain data and respond quickly to requests. However, achieving low-power and stable SRAM cells, which are essential for IoT systems, is not possible with CMOS technology due to scaling issues. As a result, new nanoscale devices, such as FinFET, have been introduced as a potential replacement for CMOS in SRAM design. This paper presents a new FinFET-based 8 T SRAM cell with separate reading and writing paths. The cell uses read-decoupling and write-assist pull-down path cut techniques to improve read stability and writability, respectively. Single-ended reading and writing structures reduce power consumption, and stacking transistors, along with read bitline leakage elimination, reduces leakage power dissipation. The proposed cell's efficiency is evaluated using HSPICE simulator with 10-nm FinFET technology and is compared with conventional 6 T, single-bitline 7 T (SB7T), single-ended 8 T (SE8T), and transmission gate read-decoupled 9 T (TRD9T) SRAM cells at V DD = 0.35 V. The proposed cell improves read stability by 2.59×/1.04 × and enhances writability by 1.38×/1.01 × compared to 6 T/TRD9T and 6 T/SB7T, respectively. It also reduces read power by 28.25 %/19.60 % compared to the 6 T/SB7T and reduces write power by at most 33.40 % and at least 5.46 %. Moreover, the leakage power is reduced by at least 5.80 %. However, the proposed cell increases read/write delay by 1.77×/1.40 × and shows 1.23 × larger layout area compared to 6 T. [ABSTRACT FROM AUTHOR]

In this paper, a high current efficiency two-stage amplifier using multipath nested feedforward compensation (MNFC) method is proposed. For the purpose of achieving the high current efficiency, the first stage of the amplifier uses a recycling folded cascode amplifier (RFC) and a nested small-gain stage is added between the two stages of the amplifier so that there are two paths in the feedforward path. This two-stage amplifier improves the phase margin (PM) and extends the gain bandwidth (GBW) by using the MNFC technique which can eliminate the non-dominant pole. The chip area of this two-stage MNFC amplifier which using 0. 18 μ m CMOS process is 0.01272 mm 2. The simulated and measured results shows that the phase margin(PM), DC gain, gain-bandwidth(GBW), average 1% settling time, slew rate- (SR-) and slew rate+ (SR+) is 72.7°, 104.4 dB, 4.29 MHz, 246.2 ns, 16 V/ μ s , and 6.15 V/ μ s , respectively, when the load capacitance is 120 pF. The supply voltage of this circuit is 1.8 V and the power consumption is 0.13 mW. • This multipath nested feedforward compensation (MNFC) method has higher current efficiency. • The frequency compensation effect is better than that of traditional feedforward compensation methods. • The gain-bandwidth is extended and the phase margin is improved. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient dynamic-time current comparator for current mode signal processing. The proposed circuit utilizes a switched feedback-based inverter and a clock-shaping circuit. The switched feedback-based inverter can detect the polarity of the sensed current from the current subtraction circuit. While the clock-shaping circuit can manage the power consumption. Since the proposed current comparator exhibits a high sensitivity to ultra-low input current with a low input offset, it can be exploited in a current mode successive-approximation-register analog-to-digital converters for a wide range of wearable applications. Moreover, a design methodology for an efficient and robust current comparator is presented. The circuit is designed and simulated in TSMC 0.13 µm CMOS technology, and occupies a silicon area of 7834 µm2. The proposed current comparator consumes a power of 14 µW with a single power supply of 1.2 V. It provides a resolution of 2 nA, and a delay of 4.6 ns. Moreover, the post-layout simulation results indicate a good agreement compared to the prior art. [ABSTRACT FROM AUTHOR]

This paper presents a fourth-order sigma-delta (ΣΔ) ADC applied to a micro-electro-mechanical system (MEMS) gyroscope system. First, a system-level model of ΣΔ modulator containing non-ideal factors is established, and the optimal system performance of the ΣΔ modulator is determined by optimizing the feedforward path and the feedback coefficient of the feedback path. Then, the operational transconductance amplifier (OTA) with chopping technique and clock timing to control bias current in the first stage integrator of the circuit design is able to reduce not only the flicker noise of the modulator, but also reduce the system power consumption. Third, the design of other essential circuit modules is presented, and the circuit performance meets the requirements and low-power consumption is achieved. The designed ΣΔ ADC uses a 0.18 μm CMOS BCD process, with a ΣΔ modulator area of 0.64 mm2 and a digital filter area of 2.03 mm2. When the sampling frequency is 2 MHz and the signal bandwidth is 7.8 kHz, the experimental measurement results show that the proposed ΣΔ modulator with the fourth-order CIFF structure can achieve a signal-to-noise ratio (SNR) of 66.3 dB and an effective number of bits (ENOB) of 10.07 bits, with a dynamic range (DR) of 89 dB and a power consumption of 9 mW. The SNR of ΣΔ ADC after filtering is 63 dB, which meets the requirements of high DR and low-power consumption of MEMS digital gyroscope sensors. [ABSTRACT FROM AUTHOR]

This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator. The advantages of the proposed circuit are low kickback noise and offset. Moreover, low-power and high-speed characteristics are obtained by avoiding direct connection between the pre-amplifier and latch stages using another stage between them. The power-delay product (PDP) of the comparator is reduced due to the reduction in charging and discharging delays at the latching nodes. The proposed comparator consumes only 244.19 µW using a 1 V supply voltage. Furthermore, the bandwidth, delay, offset, and kickback noise of the proposed comparator are 4 GHz, 26.91 ps, 3 mV, and 38 mV, respectively. Results indicate the proper performance of the proposed comparator in low-power applications. [ABSTRACT FROM AUTHOR]

The split-radix fast Fourier transform (SRFFT) is attractive for low-power FFT processors as it has the lowest numbers of multiplication operations among all FFT algorithms. FFT algorithms differ from one another by the location of the twiddle factor. The irregular locations of the twiddle factors in the SRFFT lead to complex address generators for the memory containing the twiddle factors. This paper proposes a novel twiddle factor addressing architecture for the split-radix FFT processor, which can effectively reduce its power consumption. This is then used to design a simple memory address generator and a low-power pipelined SRFFT. The proposed algorithm is used to implement a 1024-point pipelined circuit. Post-layout simulation shows that the proposed 1024-point design achieves over 24% and 14.7% lower power consumption for the multiplications and ROM, respectively, compared to a traditional radix-2 single delay feedback (SDF) FFT architecture. • In this paper, a novel twiddle factor addressing architecture is proposed, which can reduce the power consumption of the SRFFT processor. • Under the TSMC 65 nm process, we compared the newly proposed SRFFT processor with the traditional radix-2 FFT processor. • SRFFT processor can reduce the power consumption of the multiplier by 24% and the power consumption of the ROM by 14.7%. [ABSTRACT FROM AUTHOR]

For the processing of signals in battery-powered and portable biological healthcare systems, there is a huge requirement for low-pass-filter (LPF) architecture. However, it's challenging to achieve low-power operation of LPF with improved figure-of-merit (FOM). This paper presents a 4th-order cascoded flipped source follower filter (CFSF) which consumes ultra-low power of 0.4 nW from 0.5 V supply. The proposed architecture has been designed in 180 nm technology using BSIM3V3 MOS models. The post-layout simulation result shows that the proposed architecture delivers a gain of −4.7 dB, bandwidth (BW) of 100 Hz, dynamic range (DR) of 57.141 dB, input referred noise (IRN) of 97 μV rms , Total harmonic distortion (THD) of −40.833 dB and FOM of 1.39 × 10−15 J. The proposed architecture occupies an area of 0.052 mm2. Further, the statistically determined values for gain, DR, and THD with 200 Monte Carlo samples indicate mean values of −7.594 dB, 48.482 dB and −48.335 dB with standard deviation values of 7.063 dB, 5.779 dB and 12.316 dB, respectively. The proposed CFSF LPF architecture can be used in portable as well as wearable biological healthcare systems. [ABSTRACT FROM AUTHOR]

• Effect of channel epilayer thickness on Analog/RF-linearity performance of a U-TFET. • Optimization of channel epilayer thickness of a U-TFET in three low-power regimes. • Impact of process-induced variation in three low-power regimes for the U-TFET. In this paper, the impact of vertical channel epilayer thickness (T epi) of a unique U-TFET has been investigated in the RF domain along with its linearity aspect. Then, a glance has been thrown to the analog domain as well. The entire study has been carried out for the three low-power performance zones. After scrutinizing the linearity vs. analog/RF performance, it has been observed that the most enhanced device in the analog/RF domain is the worst performer with respect to the linearity aspect and vice-versa. This calls for optimization. The 6-nm-T epi device turns out to be the one. Next, for the first time, a unique process-induced variation study in terms of the deviated T epi from its optimized value has been introduced to find out the degree of sensitivity of different linearity parameters with respect to the deviation. Intriguingly, no single trend has been observed in terms of the dominance of linearity parameters for the said three zones – the result remains application specific. [ABSTRACT FROM AUTHOR]

This paper presents a low-power two-step double-data-rate (TS-DDR) counter without calibration for column-parallel single-slope analog-to-digital converter (SS ADC) in CMOS image sensor. A resolution alterable TS counting logic, which drives counting circuit to operate as a (N + M)-bit counter for the fine quantization and a M-bit MSB counter for the coarse quantization, is proposed to reduce the dynamic power consumption. As no calibration is required, the proposed counter is compatible with both digital correlated double sampling (D-CDS) and digital correlated multiple sampling (D-CMS). Moreover, a DDR structure without phase matching required for TS counter is employed to further reduce the power consumption. The proposed TS-DDR counter is implemented in 12-bit column-parallel SS ADCs for a CMOS image sensor. As a result, the proposed TS-DDR counter achieves a power consumption saving of at least 55.2% compared to a traditional one. The proposed SS ADC consumes 47.6 μW and has a DNL of +0.45/-0.55 LSB and an INL of +0.73/-2.36 LSB each column at 6.1 μs conversion time. [ABSTRACT FROM AUTHOR]

Approximate multipliers are widely used in error-tolerant applications to improve circuit performance. For signed multiplication, previous approximate Booth multipliers usually have a large relative error with operands around "0", while approximate leading one detector based (LOD-based) multipliers are not energy-efficient due to the extra preprocessing module. In this paper, a low relative error leading one/zero detector based approximate multiplier (LOZDAM) is proposed for signed multiplication, which dynamically truncates the operands according to the location of their most significant bits for signed complement data. Its accuracy can be configured to suit fault-tolerant applications with different accuracy requirements. A compensation strategy is proposed to reduce the calculation error of LOZDAMs at a low cost. All proposed designs are evaluated in 28nm/0.9 V/TT/25 °C CMOS. Compared with the exact design, the proposed LOZDAM6/7/8/9 with the width of Booth multiplier being 6/7/8/9-bit reduces average power by 64%/43%/33%/21%, with the mean relative error distance by 2.94%/1.46%/0.73%/0.36%, respectively. Case studies of image sharpening and serial Fast Fourier Transform system both show acceptable error and good power/area savings, which verifies the feasibility of our designs. In general, our proposed LOZD-based approximate multipliers achieve both high accuracy and low power. [ABSTRACT FROM AUTHOR]

This paper presents a capacitor sample-hold oscillator architecture which realizes temperature-stabilized operation without a precise reference generator by using a capacitor to sample-hold the peak charge voltage of the previous phase as the reference for the current phase. Due to its dual-way charging and discharging structure, the peak charge voltage for each phase will eventually stabilized around half the supply voltage. The frequency of the oscillator depends on the RC time constants of capacitors charging (discharging) across passively-temperature-stabilized resistive elements and the comparator delay time. By analyzing the temperature characteristics of the comparator delay time and using temperature compensated bias currents to achieve temperature stabilization of the delay time, this architecture improves the overall temperature stability. This architecture has been designed and verified in 0.18-μm CMOS technology. The simulation results demonstrate this design consumes 7.99 μW from a 1.8 V supply voltage at 58.9 kHz and achieves a temperature stability of best 22.19 ppm/℃(TT Corner) from −40◦C to 90◦C, and frequency variations of ± 0.3 % for supply changes from 1.25 to 1.8 V. [ABSTRACT FROM AUTHOR]

Static random access memory (SRAM) is a critical cell of VLSI, which is sensitive to the charge generated by high-energy particles and susceptible to logical errors. In this paper, the cross-coupled 18T SRAM cell (CC18T) is proposed, which uses the NMOS stack structure to reduce average power consumption, and employs redundant transistors to build a feedback loop to improve reliability. The model simulation results show that CC18T can fully achieve single-node-upset recovery and partial double-node-upset recovery. Compared with RHMD10T, QUCCE10T, QUCCE12T, We-Quatro, S4P8N, S8P4N, DNUCTM, DNUSRM, SESRS and SEA14T, the average power consumption of CC18T is reduced by 30% on average, the read access time and write access time are also reduced by 9.27% and 10.35% on average. [ABSTRACT FROM AUTHOR]

This paper presents a high-stability low-power 10 T (HSLP10T) sub-threshold SRAM cell with single-ended operations. The HSLP10T cell uses a decoupled read path, formed by a transmission gate and a dynamic inverter, thereby, resulting in read stability improvement. In addition, it employs a feedback-cutting transistor to facilitate the write operation, which increases writability. Due to single-ended operations, direct-write on complementary node, floated bitline, and use of more p-type transistors, the power consumption reduces in the proposed cell. Simulated results in the 7-nm FinFET technology indicate that at a 300 mV supply voltage, the read stability/writability of the proposed HSLP10T cell is 2.06X/1.31X as that of the conventional 6 T cell. Moreover, the dynamic/leakage power consumption is reduced by 1.82X/2.92X when compared with the conventional 6 T SRAM. The proposed HSLP10T SRAM bitcell has a layout area of 0.047 µm2, which is 1.67 × larger than the conventional 6 T SRAM. However, the highest ON-to-OFF currents ratio related to the proposed design compensates for this area overhead by connecting more number of cells to the same bitline in the columns of the SRAM array. Moreover, the minimum operation voltage is reduced by 48.28 % using proposed design compared to the conventional 6 T SRAM. [ABSTRACT FROM AUTHOR]

In this paper, a fully-differential low-power low-noise neural recording amplifier with a novel recycling telescopic-cascode (RTC) operational transconductance amplifier (OTA) is presented. In the proposed RTC OTA, the current recycling and cross-coupled transistors with local positive feedback are utilized to significantly improve the OTA's parameters like small-signal DC gain and unity-gain bandwidth. The gain enhancement also improves the linearity in the closed-loop structure. Extensive analytical calculations and simulation results using TSMC 0.18-µm CMOS process are provided to examine the usefulness of the proposed OTA. The simulated neural recording amplifier achieves 3.55 µV rms input-referred noise over 1 Hz-10 kHz bandwidth with 3.03 and 1.22 noise efficiency factor for local field potential (LFP) and action potential (AP) bands, respectively. The total harmonic distortion (THD) is −41.7 dB for a 1 mV pp , 1 kHz sinusoidal input signal. The total power consumption is 1.70 µW from a single 1.8-V power supply. [ABSTRACT FROM AUTHOR]

This paper presents a low-power conditional analog correlated multiple sampling (CACMS) circuit based on the passive switched-capacitor (SC) correlated multiple sampling (CMS) technique. The bright pixel output noise is dominated by photon shot noise, which cannot be reduced by CMS within one readout. Therefore, in the CACMS, the CMS operation is performed for a dark pixel output and turned off for a bright pixel output. As a result, the power consumption of the CACMS circuit under the bright pixel output is reduced by 28%. The transfer function and noise reduction effect of the CACMS circuit are also analyzed. The simulation results show that the CACMS circuit achieves an input-referred random noise of 70.3μV rms. In addition, the proposed SC CMS scheme provides designers with a free trade-off on the number of capacitors and the readout time. In the CACMS, the readout time of the SC CMS circuit is reduced by 16.7% at the cost of an extra capacitor. [ABSTRACT FROM AUTHOR]