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Summary: A high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched‐capacitor (SC) ladder and a low‐coupled eight‐shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on‐chip transformer, thus reducing quantization noise and phase noise. An eight‐shaped transformer designed using two coils cross‐connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180‐nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is −120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is −191 dBc/Hz. The chip size is 0.294 mm2. [ABSTRACT FROM AUTHOR]

Two RF CMOS voltage-controlled oscillators (VCOs) with source damping resistors to suppress 1/ ${f}$ noise up-conversion are presented in this letter. Two important parameters: the phase deviation from the first harmonic term of the ideal impulse sensitivity function (ISF), and the initial phase of the first harmonic term of channel current, dominate the 1/ ${f}$ noise up-conversion. Based on the outcome, the effects of the source damping resistors on the two phases are analyzed and two VCO prototypes are designed. Implemented in Taiwan Semiconductor Manufacturing Company 180 nm RF CMOS process, the VCOs achieve 64.7% and 50% frequency tuning range at 2.3–4.5 and 3–5 GHz, respectively, and perform phase noise (PN) of −131.03, −129.28, and −124.98 dBc/Hz at 1 MHz offset from output frequencies of 2.33, 3.057, and 4.57 GHz separately. [ABSTRACT FROM AUTHOR]

This paper presents a fractional- N all-digital phase-locked loop (ADPLL). A 4-bit multi-delay line time-to-digital converter (MDL-TDC) using path selection technique is proposed to achieve a 4-ps resolution with 0.24-mW power consumption at 52 MS/s. A TDC offset calibration method is used to eliminate TDC metastability. An isolated constant-slope digital-to-time converter (ICS-DTC) is utilized to cancel the quantization noise (Q-noise) and achieve true-fractional delay. By tuning DTC compensation, spur and Q-noise are suppressed by 14 dB. To speed up the locking process of the ADPLL, a counter-based coarse PLL is integrated to monitor and compensate for large frequency and phase jump while consuming almost zero power. The proposed ADPLL is implemented in a 40-nm standard CMOS process, occupying a silicon area of 0.36 mm2. When TDC offset calibration is turned on, the in-band noise is suppressed by 20 dB. The measured results show 0.78-ps rms jitter and −40-dBc in-band fractional spur are achieved, corresponding to a figure of merit (FOM) of −235 dB. [ABSTRACT FROM AUTHOR]

This paper presents an accurate ISF-based phase noise analysis method for LC/Ring oscillators. The proposed method can simultaneously quantify the effect of flicker noise and thermal noise on phase noise. The impulse sensitivity function (ISF) tool is used to evaluate the effect of flicker noise sources. An equivalent thermal noise resistor is utilized to assess the thermal noise contribution and simplify the analysis process. Based on the proposed method, the phase noise performance of a voltage-controlled oscillator (VCO) with source damping resistors is discussed. Simulated in 180-nm TSMC and 110-nm HHGRACE CMOS processes, the accuracy of the proposed method is verified. The predicted phase noise performance is consistent with the simulation results in 1/ f 3 and 1/ f 2 region, achieving 1-dB accuracy in diverse oscillator topologies. [ABSTRACT FROM AUTHOR]