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Detection of vector magnetic fields at nanoscale dimensions is critical in applications ranging from basic material science and fundamental physics to information storage and medical diagnostics. So far, nanoscale vector magnetic field sensing is achieved solely by exploiting a single nitrogen‐vacancy (NV) center in a diamond, by evaluating the Zeeman splitting of NV spin qubits by using the technique of an optically‐detected magnetic resonance. This protocol requires a complex optical setup and expensive detection systems to detect the photoluminescence light, which may limit miniaturization and scalability. Here, a simple approach with all‐electric operation to sensing a vector magnetic field at 200 × 200 nm2 dimensions is experimentally demonstrated, by monitoring a stochastic nanomagnet's transition probability from a metastable state, excited by a driving current due to spin‐orbit torque, to a settled state. [ABSTRACT FROM AUTHOR]

Power losses of switches and inductors are consistent challenges that hinder the development of high-frequency power supply in package (PSiP). This paper investigates the roadmap for power loss optimizations of switches and inductors in high-frequency PSiPs. Firstly, a size and parallel quantity design method to reduce power loss in an integrated Si LDMOSFET is provided with comprehensive consideration of switching frequency and power levels. Secondly, quality factors of different air-core inductors are analyzed with consideration of geometric parameters and skin effect, which provides the winding structure optimization to reduce power losses. The power losses of the integrated Si LDMOSFET and air-core inductors are both reduced to less than 10% of the output power at 1~100 MHz switching frequency and 0.1~10 W power level. Finally, based on the above optimizations, power losses of switches and inductors are calculated with switching frequency and power level. Combining the calculated results, this paper predicts the efficiency boundaries of PSiPs. Upon efficiency normalization with consideration of input and output voltage levels, all the predictions are consistent with the published literature. The efficiency predication error is 1~15% at 1~100 MHz switching frequency and 0.1~10 W power level. The above power loss optimizations improve the efficiency, which provides potential roadmaps for achieving high-frequency PSiPs. [ABSTRACT FROM AUTHOR]

An increasing amount of attention has been focused on the issue of the low recruitment and retention of male teachers in early childhood education worldwide. Previous research has indicated that personal perceptions of male preservice teachers' personal regarding early childhood education could have a major influence on their decision of a future career. This qualitative study aims at promoting the significance of early childhood preservice preparation programs by exploring the perspectives and experiences of male preservice teachers working with infants in China. Using the purposeful sampling method, two male interns in an infant classroom were interviewed individually, and each of them was interviewed three times in total: at the beginning of their professional studies, during their internship, and after completing their studies. Participants' reflections were also considered as supplementary data. The results underscore the necessity of a comprehensive early childhood preservice preparation program for prospective male teachers, particularly regarding infants' development. Additionally, the study highlights the crucial role of male preservice teachers' involvement and perspectives before entering the early childhood education field. The study was limited to one location and may not apply to others. Despite the small sample, it offers valuable perspectives. Future focus should be on attracting males to early childhood education area and exploring useful strategies. [ABSTRACT FROM AUTHOR]

Summary: A high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched‐capacitor (SC) ladder and a low‐coupled eight‐shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on‐chip transformer, thus reducing quantization noise and phase noise. An eight‐shaped transformer designed using two coils cross‐connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180‐nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is −120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is −191 dBc/Hz. The chip size is 0.294 mm2. [ABSTRACT FROM AUTHOR]

The long-term evolution characteristics of the heat reservoir of soil have been analyzed by 15 years of simulation test with periodic indoor and outdoor air temperature conditions. A scale model test of the soil in the subway station sidewalls and software ANSYS fluid-structure coupling heat transfer model are built in this study, which are complementary and mutual authentication. In 1∼15 years, the results show that the maximal temperature rise of soil at 2 m buried depth is 3.9 °C, at 7 m buried depth is 1.6 °C, and at 12 m buried depth is 1.5 °C. On the sidewalls surface the average maximal endothermic heat flow density is 6.8 W/m2 in summer, and the average maximum exothermic heat flow density is 11.3 W/m2 in winter. It provides theoretical reference for the reasonable use of heat storage of the soil in the sidewalls of subway stations.

Featured Application: This paper proposes virtual admittance feedforward compensation and phase correction for average-current-mode-controlled totem-pole PFC converters. It can effectively reduce total harmonic distortion (THD) and improve the power factor (PF) of the converter. The proposed control strategy can be directly used in on-board chargers (OBCs) for electric vehicles, power supplies for server clusters, communication equipment, industrial equipment, etc. This paper explores a current distortion problem in totem-pole bridgeless power factor correction (PFC) converters with average current mode (ACM) control. With in-depth modeling for the current and voltage loops, it was found that the current distortion is caused by the limited current loop bandwidth and input filter capacitor. These factors lead to the presence of a susceptance component in the input admittance, which degrades the power factor (PF) and total harmonic distortion (THD) of the PFC converter. To solve this problem, this paper proposes virtual admittance feedforward compensation (VAFC) and phase correction methods to adjust the input admittance to pure conductance. The VAFC can generate virtual admittance that compensates for susceptance components in the input admittance, while phase correction can generate an equivalent current source that offsets the current in input capacitors. Furthermore, a phase lock loop (PLL) is introduced to realize the VAFC, which reduces the feedforward interference caused by input voltage sampling noise. Finally, an experimental prototype was built to verify the effectiveness of the proposed strategies. According to the test results, the proposed compensation strategy improves the PF by 1.23%, while reducing the THD by 2.52% and achieving a peak efficiency of 98.69%. [ABSTRACT FROM AUTHOR]

Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable cryptographic accelerators with relatively low efficiency and high latency, this paper presents design and analysis of a reconfigurable cryptographic accelerator consisting of a reconfigurable cipher unit and a reconfigurable hash unit to support widely used cryptographic algorithms for IoT Devices, which require block ciphers and hash functions simultaneously. Based on a detailed and comprehensive algorithmic analysis of both the block ciphers and hash functions in terms of basic algorithm structures and common cryptographic operators, the proposed reconfigurable cryptographic accelerator is designed by reusing key register files and operators to build unified data paths. Both the reconfigurable cipher unit and the reconfigurable hash unit contain a unified data path to implement Data Encryption Standard (DES)/Advanced Encryption Standard (AES)/ShangMi 4 (SM4) and Secure Hash Algorithm-1 (SHA-1)/SHA-256/SM3 algorithms, respectively. A reconfigurable S-Box for AES and SM4 is designed based on the composite field Galois field (GF) GF(((22)2)2), which significantly reduces hardware overhead and power consumption compared with the conventional implementation by look-up tables. The experimental results based on 65-nm application-specific integrated circuit (ASIC) implementation show that the achieved energy efficiency and area efficiency of the proposed design is 441 Gbps/W and 37.55 Gbps/mm2, respectively, which is suitable for IoT devices with limited battery and form factor. The result of delay analysis also shows that the number of delay cycles of our design can be reduced by 83% compared with the state-of-the-art design, which shows that the proposed design is more suitable for applications including 5G/Wi-Fi/ZigBee/Ethernet network standards to accelerate block ciphers and hash functions simultaneously. [ABSTRACT FROM AUTHOR]

Simultaneous localization and mapping (SLAM) is the major solution for constructing or updating a map of an unknown environment while simultaneously keeping track of a mobile robot's location. Correlative Scan Matching (CSM) is a scan matching algorithm for obtaining the posterior distribution probability for the robot's pose in SLAM. This paper combines the non-linear optimization algorithm and CSM algorithm into an NLO-CSM (Non-linear Optimization CSM) algorithm for reducing the computation resources and the amount of computation while ensuring high calculation accuracy, and it presents an efficient hardware accelerator design of the NLO-CSM algorithm for the scan matching in 2D LiDAR SLAM. The proposed NLO-CSM hardware accelerator utilizes pipeline processing and module reusing techniques to achieve low hardware overhead, fast matching, and high energy efficiency. FPGA implementation results show that, at 100 MHz clock, the power consumption of the proposed hardware accelerator is as low as 0.79 W, while it performs a scan match at 8.98 ms and 7.15 mJ per frame. The proposed design outperforms the ARM-A9 dual-core CPU implementation with a 92.74% increase and 90.71% saving in computing speed and energy consumption, respectively. It has also achieved 80.3% LUTs, 84.13% FFs, and 20.83% DSPs saving, as well as an 8.17× increase in frame rate and 96.22% improvement in energy efficiency over a state-of-the-art hardware accelerator design in the literature. ASIC implementation in 65 nm can further reduce the computing time and energy consumption per scan to 5.94 ms and 0.06 mJ, respectively, which shows that the proposed NLO-CSM hardware accelerator design is suitable for resource-limited and energy-constrained mobile and micro robot applications. [ABSTRACT FROM AUTHOR]

For very high frequency (VHF) class Φ2 inverter, conventional design method requires complex tuning for parameters. Without fully quantitative calculations, the tuning highly depends on experience that cannot achieve optimal design. In this article, a target function design strategy is proposed based on quantitative harmonic weighting, which simplifies the design procedures and minimizes the switch voltage stress. First, the target switch voltage with minimized peak value is derived by optimizing the harmonic weighting. With the result, the power switch is modeled as a voltage source to simplify the calculations, where the branch currents are solved to provided fully quantitative analysis. Based on the analysis, optimal features of switching node impedance are derived to achieve the target switch voltage. In addition, basic constrains of the resonant tank are analyzed to reduce circling currents. Combining the optimal features and basic constrains of the resonant tank, the circuit parameters are calculated directly, which minimizes the switch voltage stress and improves power efficiency. Compared with conventional design, a 27.12 MHz prototype demonstrates 10.2% reduction in average switch voltage stress and 7.2% improvement in average efficiency. [ABSTRACT FROM AUTHOR]

Analog arithmetic operations are the most fundamental mathematical operations used in image and signal processing as well as artificial intelligence (AI). In‐memory computing (IMC) offers a high performance and energy‐efficient computing paradigm. To date, in‐memory analog arithmetic operations with emerging nonvolatile devices are usually implemented using discrete components, which limits the scalability and blocks large scale integration. Here, a prototypical implementation of in‐memory analog arithmetic operations (summation, subtraction and multiplication) is experimentally demonstrated, based on in‐memory electrical current sensing units using spin‐orbit torque (SOT) devices. The proposed structures for analog arithmetic operations are smaller than the state‐of‐the‐art complementary metal oxide semiconductor (CMOS) counterparts by several orders of magnitude. Moreover, data to be processed and computing results can be locally stored, or the analog computing can be done in the nonvolatile SOT devices, which are exploited to experimentally implement the image edge detection and signal amplitude modulation with a simple structure. Furthermore, an artificial neural network (ANN) with SOT devices based synapses is constructed to realize pattern recognition with high accuracy of ≈95%. [ABSTRACT FROM AUTHOR]

This article proposes a unified pulsewidth-cycle (UPWC) control strategy to achieve mixed-mode operation and consistent valley switching (VS) for boost power factor correction converter. Compared with conventional single-mode controllers, it has a unified scheme to achieve single discontinuous conduction mode (DCM), single critical conduction mode (CRM), or mixed DCM/CRM operations in each half-line cycle. To regulate the input current as a sinusoid, the UPWC controller adopts a variable pulsewidth and a near-constant switching cycle under DCM, while adopts a constant pulsewidth and a variable switching cycle under CRM. To facilitate analysis, normalized mapping of operation modes is provided, along with the final pulsewidth and switching cycle. Furthermore, to ensure consistent VS, a controlled zero current detection method is proposed to fix the turn-on point of the power switch. No matter in DCM or CRM, consistent VS reduces both the switching loss and current distortion caused by parasitic resonance. To further reduce the current distortion caused by fixing the turn-on point, a compensation gain is provided that reshapes the input current as a sinusoid. Finally, through mixed DCM/CRM operation and consistent VS, the proposed UPWC controller achieves preferable performances in the power range, efficiency, power factor, and current distortion. [ABSTRACT FROM AUTHOR]

Two RF CMOS voltage-controlled oscillators (VCOs) with source damping resistors to suppress 1/ ${f}$ noise up-conversion are presented in this letter. Two important parameters: the phase deviation from the first harmonic term of the ideal impulse sensitivity function (ISF), and the initial phase of the first harmonic term of channel current, dominate the 1/ ${f}$ noise up-conversion. Based on the outcome, the effects of the source damping resistors on the two phases are analyzed and two VCO prototypes are designed. Implemented in Taiwan Semiconductor Manufacturing Company 180 nm RF CMOS process, the VCOs achieve 64.7% and 50% frequency tuning range at 2.3–4.5 and 3–5 GHz, respectively, and perform phase noise (PN) of −131.03, −129.28, and −124.98 dBc/Hz at 1 MHz offset from output frequencies of 2.33, 3.057, and 4.57 GHz separately. [ABSTRACT FROM AUTHOR]

By using metal blocks as the protective coating, placing the sensitive signals in last but second metal (LSM), integrating a low-cost one-time programming (OTP) cell in each PUF unit, the proposed switched-capacitor (SC) PUF can both provide sensitive anti-invasive-attack protective coating and stable key for the security chip. Moreover, the circuit parameters and the layout implementation of the SC PUF unit are all compatible with other digital standard cells, which greatly facilitates the integration of SC PUF unit in the security chip by using digital design flow when its function, timing, power, and layout views are characterized using commercial timing and layout extraction tools. The anti-invasive-attack ability, stability, and digital design flow compatibility of the proposed SC PUF standard cell are verified in a security chip by using a standard 0.18- $\mu \text{m}$ CMOS process. The measured bit error rate, bias, average intra-die HD, and average inter-die HD of output keys after OTP is <10−4, 46.72%, 0%, and 50.38% respectively. Finally, the failed probing and destruction attack attempts to the coating also verify the invasive-attack-resistant property of the proposed SC PUF standard cell. With the help of SC PUF standard cell, the whole security chip can easily obtain stable keys and sensitive anti-invasive-attack ability by using digital design flow. [ABSTRACT FROM AUTHOR]