43 results on '"Kuroda, Tadahiro"'
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2. Wireless Interface Technologies for 3D IC and Module Integration
3. A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum
4. Hydrophilic Bonding of SiO2/SiO2 and Cu/Cu using Sequential Plasma Activation
5. Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS
6. Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application
7. A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application
8. A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network
9. Micron-to-Submicron Cu electroplating in view of Agile-X LSI Chips Fabrication using Open Facility
10. A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS
11. A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network
12. 1.2 nJ/classification 2.4 mm2 asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18 μm CMOS
13. A183.4-nJ/Inference 152.8-μW 35-Voice Commands Recognition Wired-Logic Processor Using Algorithm-Circuit Co-Optimization Technique
14. A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA
15. A 12.8-Gb/s 0.5-pJ/b Encoding-less Inductive Coupling Interface Achieving 111-GB/s/W 3D-Stacked SRAM in 7-nm FinFET
16. A Deep Metric Learning-Based Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion
17. A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-stacked SRAM in 7-nm FinFET
18. Proximity Wireless Communication Technologies: An Overview and Design Guidelines
19. A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic
20. A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias
21. 3D-Stacked SRAM Using Near-Field Wireless Communication
22. A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network
23. A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers
24. An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique
25. Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format
26. A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System
27. A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC
28. A bonding-less 5-GHz RFID module using inductive coupling between IC and antenna
29. A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation
30. A 7-nm FinFET 1.2-TB/s/mm$^{2}$ 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
31. A 5-GHz 0.15-mm² Collision-Avoiding RFID Employing Complementary Pass-Transistor Adiabatic Logic With an Inductively Connected External Antenna in 0.18-μm CMOS
32. Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface
33. mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications
34. A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network
35. A Physical Verification Methodology for 3D-ICs Using Inductive Coupling
36. A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net
37. A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna
38. Wireless Interface Technologies for 3D IC and Module Integration
39. A bonding-less 5-GHz RFID module using a 300um x 500um IC chip
40. A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
41. Hydrophilic Bonding of SiO2/SiO2 and Cu/Cu using Sequential Plasma Activation.
42. Hydrophilic Bonding of SiO2/SiO2and Cu/Cu using Sequential Plasma Activation
43. 1.2 nJ/classification 2.4 mm2asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18 µm CMOS
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