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Thin gadolinium metallic layers were deposited by high-pressure sputtering in pure Ar atmosphere. Subsequently, in situ thermal oxidation was performed at temperatures ranging from 150 to 750 $^\circ$C. At an oxidation temperature of 500 $^\circ$C the films show a transition from monoclinic structure to a mixture of monoclinic and cubic. Regrowth of interfacial SiO$_x$ is observed as temperature is increased, up to 1.6 nm for 750 $^\circ$C. This temperature yields the lowest interface trap density, 4e10 eV$^{-1}$ cm$^{-2}$, but the effective permittivity of the resulting dielectric is only 7.4. The reason of this low value is found on the oxidation mechanism, which yields a surface with located bumps. These bumps increase the average thickness, thus reducing the capacitance and therefore the calculated permittivity., Comment: 22 pages, 7 figures, 1 table

AmorphousGd2O3 and Sc2O3 thin films were deposited on Si by high-pressure sputtering (HPS). In order to reduce the uncontrolled interfacial SiOx growth, firstly a metallic film of Gd or Sc was sputtered in pure Ar plasma. Subsequently, they were in situ plasma oxidized in an Ar/O2 atmosphere. For post-processing interfacial SiOx thickness reduction, three different top metal electrodes were studied: platinum, aluminum and titanium. For both dielectrics, it was found that Pt did not react with the films, while Al reacted with them forming an aluminate-like interface and, finally, Ti was effective in scavenging the SiO2 interface thickness without severely compromising gate dielectric leakage., Comment: 14 pages, 6 figures

In this paper, the time-dependent dielectric breakdown (TDDB) in sub-1-nm equivalent oxide thickness (EOT) n-type bulk FinFETs is studied. The gate stacks consist of an IMEC clean interfacial layer, atomic layer deposition HfO2 high-k and TiN metal electrode. For the 0.8-nm EOT FinFETs, it is found that TDDB lifetime is consistent with results of planar devices for areas around 1e-8 cm2, implying that the FinFET architecture does not seem to introduce new failure mechanisms. However, for devices with smaller area, the extrapolated voltage at a ten-year lifetime for soft breakdown (SBD) does not meet the specifications, and as a consequence, the SBD path wear-out will have to be included in the final extrapolation. Furthermore, it is shown that for EOTs smaller than 0.8 nm, the TDDB reliability on n-type FinFETs is challenged by the high leakage currents., Comment: 15 pages, 7 figures