123 results on '"Wong, H.-S. Philip"'
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2. Complementary carbon nanotube metal–oxide–semiconductor field-effect transistors with localized solid-state extension doping
3. Improved Gradual Resistive Switching Range and 1000x On/Off Ratio in HfOx RRAM Achieved with a $Ge_2Sb_2Te_5$ Thermal Barrier
4. Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies
5. A compute-in-memory chip based on resistive random-access memory
6. A disposable reader-sensor solution for wireless temperature logging
7. Resistive Random Access Memory (RRAM) Technology: From Material, Device, Selector, 3D Integration to Bottom-Up Fabrication
8. Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework
9. Device Engineering and Benefit Maximization for Advanced Cryo-CMOS
10. Resistive Random Access Memory (RRAM) Technology: From Material, Device, Selector, 3D Integration to Bottom-Up Fabrication
11. Dimensional Scaling of Ferroelectric Properties of Hafnia-Zirconia Thin Films: Electrode Interface Effects.
12. Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory
13. Design Guidelines for Oxide Semiconductor Gain Cell Memory on a Logic Platform
14. Forming-Free Selectors Based on Te in an Insulating SiO xMatrix
15. Barrier Booster for Remote Extension Doping and its DTCO for 1D & 2D FETs
16. Low N-Type Contact Resistance to Carbon Nanotubes in Highly Scaled Contacts through Dielectric Doping
17. Multi-gate FeFET Discriminates Spatiotemporal Pulse Sequences for Dendrocentric Learning
18. Gain Cell Memory on Logic Platform – Device Guidelines for Oxide Semiconductor Transistor Materials Development
19. Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel
20. High-Endurance MoS2 FeFET with Operating Voltage Fess Than IV for eNVM in Scaled CMOS Technologies
21. Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors
22. Effect of Back-Gate Dielectric on Indium Tin Oxide (ITO) Transistor Performance and Stability
23. Intracellular detection and communication of a wireless chip in cell
24. Future Directions Workshop: Materials, Processes, and R&D Challenges in Microelectronics
25. Small Molecule Additives to Suppress Bundling in Dimensional‐Limited Self‐Alignment Method for High‐Density Aligned Carbon Nanotube Array.
26. Area-Selective Atomic Layer Deposition for Resistive Random-Access Memory Devices
27. Tso-Ping Ma (1945−2021)
28. Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities [Point of View]
29. Probing the Melting Transitions in Phase-Change Superlattices via Thin Film Nanocalorimetry
30. Hybrid 2T nMOS/pMOS Gain Cell Memory With Indium-Tin-Oxide and Carbon Nanotube MOSFETs for Counteracting Capacitive Coupling
31. Reigniting the U.S. Chip Industry.
32. Neural Network Compression for Noisy Storage Devices
33. The Path to a 1-Trillion-Transistor GPU: AI's Boom Demands New Chip Technology
34. Forming-Free Selectors Based on Te in an Insulating SiOx Matrix
35. Comprehensive Study of Contact Length Scaling Down to 12 nm With Monolayer MoS2 Channel Transistors
36. Big problems that demand bigger energy.
37. Comprehensive Study of Contact Length Scaling Down to 12 nm With Monolayer MoS$_{\text{2}}$ Channel Transistors
38. Technology Prospects for Data-Intensive Computing
39. Ab Initio Computational Screening and Performance Assessment of van der Waals and Semimetallic Contacts to Monolayer WSe$_{\text{2}}$ P-Type Field-Effect Transistors
40. pMOSFET with CVD-grown 2D semiconductor channel enabled by ultra-thin and fab-compatible spacer doping
41. Carbon nanotube transistors: Making electronics from molecules
42. Nanocrystallite Seeding of Metastable Ferroelectric Phase Formation in Atomic Layer-Deposited Hafnia–Zirconia Alloys
43. (Digital Presentation) Low Dimensional Channel Materials for Logic Transistors
44. Understanding Interface-Controlled Resistance Drift in Superlattice Phase Change Memory
45. Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors
46. Impact of Metal Hybridization on Contact Resistance and Leakage Current of Carbon Nanotube Transistors
47. Unveiling the Effect of Superlattice Interfaces and Intermixing on Phase Change Memory Performance
48. Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties
49. First Demonstration of Top-Gated ITO Transistors: Effect of Channel Passivation
50. Does lithography still matter after high NA EUV?
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