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Summary: A high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched‐capacitor (SC) ladder and a low‐coupled eight‐shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on‐chip transformer, thus reducing quantization noise and phase noise. An eight‐shaped transformer designed using two coils cross‐connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180‐nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is −120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is −191 dBc/Hz. The chip size is 0.294 mm2. [ABSTRACT FROM AUTHOR]

Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable cryptographic accelerators with relatively low efficiency and high latency, this paper presents design and analysis of a reconfigurable cryptographic accelerator consisting of a reconfigurable cipher unit and a reconfigurable hash unit to support widely used cryptographic algorithms for IoT Devices, which require block ciphers and hash functions simultaneously. Based on a detailed and comprehensive algorithmic analysis of both the block ciphers and hash functions in terms of basic algorithm structures and common cryptographic operators, the proposed reconfigurable cryptographic accelerator is designed by reusing key register files and operators to build unified data paths. Both the reconfigurable cipher unit and the reconfigurable hash unit contain a unified data path to implement Data Encryption Standard (DES)/Advanced Encryption Standard (AES)/ShangMi 4 (SM4) and Secure Hash Algorithm-1 (SHA-1)/SHA-256/SM3 algorithms, respectively. A reconfigurable S-Box for AES and SM4 is designed based on the composite field Galois field (GF) GF(((22)2)2), which significantly reduces hardware overhead and power consumption compared with the conventional implementation by look-up tables. The experimental results based on 65-nm application-specific integrated circuit (ASIC) implementation show that the achieved energy efficiency and area efficiency of the proposed design is 441 Gbps/W and 37.55 Gbps/mm2, respectively, which is suitable for IoT devices with limited battery and form factor. The result of delay analysis also shows that the number of delay cycles of our design can be reduced by 83% compared with the state-of-the-art design, which shows that the proposed design is more suitable for applications including 5G/Wi-Fi/ZigBee/Ethernet network standards to accelerate block ciphers and hash functions simultaneously. [ABSTRACT FROM AUTHOR]

Simultaneous localization and mapping (SLAM) is the major solution for constructing or updating a map of an unknown environment while simultaneously keeping track of a mobile robot's location. Correlative Scan Matching (CSM) is a scan matching algorithm for obtaining the posterior distribution probability for the robot's pose in SLAM. This paper combines the non-linear optimization algorithm and CSM algorithm into an NLO-CSM (Non-linear Optimization CSM) algorithm for reducing the computation resources and the amount of computation while ensuring high calculation accuracy, and it presents an efficient hardware accelerator design of the NLO-CSM algorithm for the scan matching in 2D LiDAR SLAM. The proposed NLO-CSM hardware accelerator utilizes pipeline processing and module reusing techniques to achieve low hardware overhead, fast matching, and high energy efficiency. FPGA implementation results show that, at 100 MHz clock, the power consumption of the proposed hardware accelerator is as low as 0.79 W, while it performs a scan match at 8.98 ms and 7.15 mJ per frame. The proposed design outperforms the ARM-A9 dual-core CPU implementation with a 92.74% increase and 90.71% saving in computing speed and energy consumption, respectively. It has also achieved 80.3% LUTs, 84.13% FFs, and 20.83% DSPs saving, as well as an 8.17× increase in frame rate and 96.22% improvement in energy efficiency over a state-of-the-art hardware accelerator design in the literature. ASIC implementation in 65 nm can further reduce the computing time and energy consumption per scan to 5.94 ms and 0.06 mJ, respectively, which shows that the proposed NLO-CSM hardware accelerator design is suitable for resource-limited and energy-constrained mobile and micro robot applications. [ABSTRACT FROM AUTHOR]

For very high frequency (VHF) class Φ2 inverter, conventional design method requires complex tuning for parameters. Without fully quantitative calculations, the tuning highly depends on experience that cannot achieve optimal design. In this article, a target function design strategy is proposed based on quantitative harmonic weighting, which simplifies the design procedures and minimizes the switch voltage stress. First, the target switch voltage with minimized peak value is derived by optimizing the harmonic weighting. With the result, the power switch is modeled as a voltage source to simplify the calculations, where the branch currents are solved to provided fully quantitative analysis. Based on the analysis, optimal features of switching node impedance are derived to achieve the target switch voltage. In addition, basic constrains of the resonant tank are analyzed to reduce circling currents. Combining the optimal features and basic constrains of the resonant tank, the circuit parameters are calculated directly, which minimizes the switch voltage stress and improves power efficiency. Compared with conventional design, a 27.12 MHz prototype demonstrates 10.2% reduction in average switch voltage stress and 7.2% improvement in average efficiency. [ABSTRACT FROM AUTHOR]

Analog arithmetic operations are the most fundamental mathematical operations used in image and signal processing as well as artificial intelligence (AI). In‐memory computing (IMC) offers a high performance and energy‐efficient computing paradigm. To date, in‐memory analog arithmetic operations with emerging nonvolatile devices are usually implemented using discrete components, which limits the scalability and blocks large scale integration. Here, a prototypical implementation of in‐memory analog arithmetic operations (summation, subtraction and multiplication) is experimentally demonstrated, based on in‐memory electrical current sensing units using spin‐orbit torque (SOT) devices. The proposed structures for analog arithmetic operations are smaller than the state‐of‐the‐art complementary metal oxide semiconductor (CMOS) counterparts by several orders of magnitude. Moreover, data to be processed and computing results can be locally stored, or the analog computing can be done in the nonvolatile SOT devices, which are exploited to experimentally implement the image edge detection and signal amplitude modulation with a simple structure. Furthermore, an artificial neural network (ANN) with SOT devices based synapses is constructed to realize pattern recognition with high accuracy of ≈95%. [ABSTRACT FROM AUTHOR]

—In this paper, a class-F 23 VCO using nonlinear-capacitance transforming technique to simultaneously achieve low phase noise and a wide tuning range is proposed. The phase noise degradation due to the nonlinearity of the switched capacitor in the class-F 23 oscillator is analyzed and quantitatively derived. The phase noise contributed by the nonlinear capacitance can be suppressed by using the proposed nonlinear-capacitance transformation technique. In order to achieve low phase noise over a wide bandwidth, the asymmetric-toggling method is utilized to achieve optimal capacitance ratios across the entire frequency range. Implemented in a 40-nm CMOS process, the proposed oscillator exhibits 41.2 % tuning range from 2.58 GHz to 3.92 GHz while consuming 13.8 mW–14.9 mW power dissipation. The phase noises at 2.58 GHz and 3.92 GHz oscillation frequencies are −136.4 dBc/Hz and −129.6 dBc/Hz at 1-MHz offset. The minimum phase noise is −157.2 dBc/Hz at 10 MHz offset, corresponding to an FoM of 194.1 dBc/Hz and FoM T of 206.4 dBc/Hz. [ABSTRACT FROM AUTHOR]

This paper presents a fractional- N all-digital phase-locked loop (ADPLL). A 4-bit multi-delay line time-to-digital converter (MDL-TDC) using path selection technique is proposed to achieve a 4-ps resolution with 0.24-mW power consumption at 52 MS/s. A TDC offset calibration method is used to eliminate TDC metastability. An isolated constant-slope digital-to-time converter (ICS-DTC) is utilized to cancel the quantization noise (Q-noise) and achieve true-fractional delay. By tuning DTC compensation, spur and Q-noise are suppressed by 14 dB. To speed up the locking process of the ADPLL, a counter-based coarse PLL is integrated to monitor and compensate for large frequency and phase jump while consuming almost zero power. The proposed ADPLL is implemented in a 40-nm standard CMOS process, occupying a silicon area of 0.36 mm2. When TDC offset calibration is turned on, the in-band noise is suppressed by 20 dB. The measured results show 0.78-ps rms jitter and −40-dBc in-band fractional spur are achieved, corresponding to a figure of merit (FOM) of −235 dB. [ABSTRACT FROM AUTHOR]

This article proposes a unified pulsewidth-cycle (UPWC) control strategy to achieve mixed-mode operation and consistent valley switching (VS) for boost power factor correction converter. Compared with conventional single-mode controllers, it has a unified scheme to achieve single discontinuous conduction mode (DCM), single critical conduction mode (CRM), or mixed DCM/CRM operations in each half-line cycle. To regulate the input current as a sinusoid, the UPWC controller adopts a variable pulsewidth and a near-constant switching cycle under DCM, while adopts a constant pulsewidth and a variable switching cycle under CRM. To facilitate analysis, normalized mapping of operation modes is provided, along with the final pulsewidth and switching cycle. Furthermore, to ensure consistent VS, a controlled zero current detection method is proposed to fix the turn-on point of the power switch. No matter in DCM or CRM, consistent VS reduces both the switching loss and current distortion caused by parasitic resonance. To further reduce the current distortion caused by fixing the turn-on point, a compensation gain is provided that reshapes the input current as a sinusoid. Finally, through mixed DCM/CRM operation and consistent VS, the proposed UPWC controller achieves preferable performances in the power range, efficiency, power factor, and current distortion. [ABSTRACT FROM AUTHOR]

Nowadays, deep learning algorithm has been widely used for automatic electrocardiogram (ECG) classification. However, most algorithms can only classify single heartbeat, which requires complex heartbeat extraction preprocessing. In addition, the traditional software implementation on CPU or GPU platform faces the challenge of low computing efficiency and high resource consumption. In this work, a deep one-dimensional (1D) U-net is proposed, which can classify the original continuous ECG segment at the pixel level. And an efficient hardware architecture is presented to implement the 1D U-net. A two-stage pipeline Winograd structure is designed to increase computing efficiency. A 3D processing element (PE) array is developed to improve resource utilization and overall throughput. Implemented on Xilinx Zynq ZC706 board, experimental results show that the proposed 1D U-net achieves an average accuracy of 95.55% for the pixel-level classification of five heartbeats. In terms of hardware performance, resource efficiency and computing efficiency reach 8.27 GOPS/kLUT and 123% respectively at 200 MHz clock frequency. [ABSTRACT FROM AUTHOR]

This paper presents an accurate ISF-based phase noise analysis method for LC/Ring oscillators. The proposed method can simultaneously quantify the effect of flicker noise and thermal noise on phase noise. The impulse sensitivity function (ISF) tool is used to evaluate the effect of flicker noise sources. An equivalent thermal noise resistor is utilized to assess the thermal noise contribution and simplify the analysis process. Based on the proposed method, the phase noise performance of a voltage-controlled oscillator (VCO) with source damping resistors is discussed. Simulated in 180-nm TSMC and 110-nm HHGRACE CMOS processes, the accuracy of the proposed method is verified. The predicted phase noise performance is consistent with the simulation results in 1/ f 3 and 1/ f 2 region, achieving 1-dB accuracy in diverse oscillator topologies. [ABSTRACT FROM AUTHOR]