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In recent years, there has been a growing interest in codes that can correct adjacent bit errors in memories. This is due to the increasing percentage of radiation induced errors that affect multiple cells due to technology scaling. The cells affected by the errors are physically close and in many cases adjacent. This means that in the absence of interleaving, adjacent bits will be likely to be affected by an error. A number of Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes have been proposed to deal with those errors. These codes have a low overhead in terms of number of additional parity check bits compared to Double Error Correction (DEC) codes. A problem is that they can introduce a significant penalty in terms of delay compared to a Single Error Correction (SEC) or a Single Error Correction and Double Error Detection (SEC-DED) code. This is due to the more complex decoding that needs to check approximately twice the number of syndrome patterns. In this paper, low delay SEC-DAEC codes are presented and the parity check matrices for 16, 32 and 64 bit data words are provided. To reduce the delay, a number of techniques are used in the construction of the code and in the implementation of the decoder. The evaluation shows that this results in significant savings compared to existing SEC-DAEC codes. Therefore, the proposed codes can be useful for high speed designs on which adjacent error correction is required. [ABSTRACT FROM AUTHOR]

Abstract Phase change memory (PCM) is a promising alternative to conventional DRAM main memories, due to its read performance, density, and nonvolatility and resulting low static energy. Unfortunately, reliability is still a significant challenge as limited write endurance, exacerbated by process variation, leads to increasing numbers of stuck-at faults over the memory's lifetime. This includes a significant number of stuck-at faults that appear early in the memory's service. Error-correcting Pointers (ECP) is a popular proposal to mitigate stuck-at faults in PCM by recording the addresses and the values of faulty bits in order to extend the lifetime of the memory. We propose a method to extend the effectiveness of ECP coverage called Yoda, which utilizes a small number of additional encoding bits in order to dramatically improve the effectiveness and fault correction capability of ECP. By adding one additional bit to ECP which corrects f faults, Yoda can correct 2 f +1 faults. Further improvements are possible introducing small numbers additional bits. Our simulation results demonstrate that Yoda has a 3.0× improvement in fault coverage compared to a fault-aware ECP with a similar overhead, while also providing a 2.5–3.0× improvement over state-of-the-art schemes with comparable complexity. Furthermore, Yoda provides a method to protect the auxiliary bits, also with a small overhead. By adding one auxiliary bit to protect the auxiliary bits, Yoda can achieve extra improvement. Highlights • Extending pointers with partition and flip methods improve guaranteed correction capabilities. • Using small additional computational overhead decreases the number of required encoding bits. • Applying partition and flip to the auxiliary bits can allow them to operate reliably in faulty memory. • Yoda improves tolerated faults by 2.5–3.0× compared to state-of-the-art designs. [ABSTRACT FROM AUTHOR]

Error correction coding is extensively used to achieve reliability in digital communication especially in Physical Layer. In this paper, construction of concatenated kernel code defined over algebraic structure group is discussed. Minimal trellis representation is given for constructed concatenated kernel codeword. Constructed code is tested in cognitive radio network environment subjected to continuous interference due to the behavior of primary users. Proposed code is tested through simulations and its performance is analyzed in terms of Bit Error Rate (BER) in mitigating the effect of continuous interference. Maximum likelihood graph Viterbi decoding technique is used to decode the concatenated kernel code. [ABSTRACT FROM AUTHOR]

The design and implementation of an error detection and correction scheme in a MODBUS-RTU network based on the REED-SOLOMON code is presented. The transmission of the parity bits is made respecting the parameters of the MODBUS protocol, so the bus can be used by common devices without the error detection/correction scheme. The error detection–correction is performed by means of specialized repeating devices in the receiver and transmitter. This method respects the parameters of the MODBUS-RTU protocol, so the bus enhanced with retransmitter devices can be used along with common devices. Finally, the implementation of an experimental network is described and the practical results obtained are given. [ABSTRACT FROM AUTHOR]

Resistive memories are affected by significant error rates tied to structural relaxation and wear out of the resistive memory devices. A way to reduce the need for strong error-correcting codes (ECCs) is to improve error correction based on the weak bits, i.e., potentially faulty bits, identified in sensed memory words. Here, it is formally proven that conventional ECC decoders reinforced with weak-bit-flipping may achieve similar error correction capability as theoretical generalized-minimum-distance decoders. It is shown that weak-bit-flipping may reduce the uncorrectable bit error rate (UBER) by orders of magnitude when applied in conjunction with single-error-correcting and double-error-detecting (SEC-DED) or double-error-correcting and triple-error-detecting (DEC-TED) codes. In particular, weak-bit-information extracted from a 2T2R memory and used to reinforce a DEC-TED code with a conventional decoder may enable an UBER that is one order of magnitude better than the UBER achieved with a triple-error-correcting (TEC) code and a conventional decoder. • A conventional errors-only decoder with weak-bit-flipping can outperform an erasures-and-errors decoder • A conventional errors-only decoder with weak-bit-flipping can outperform a generalized-minimum-distance decoder • The impact of weak-bit-flipping on error correction is estimated starting from resistance state distributions • The formalism used to estimate the efficiency of weak-bit-flipping is independent of the weak-bit-identification scheme [ABSTRACT FROM AUTHOR]

We present the first model of optimal voting under adversarial noise. From this viewpoint, voting rules are seen as error-correcting codes: their goal is to correct errors in the input rankings and recover a ranking that is close to the ground truth. We derive worst-case bounds on the relation between the average accuracy of the input votes, and the accuracy of the output ranking. Empirical results from real data show that our approach produces significantly more accurate rankings than alternative approaches. [ABSTRACT FROM AUTHOR]

In pebbling problems, pebbles are placed on the vertices of a graph. A pebbling move consists of removing two pebbles from one vertex, throwing one away, and moving the other pebble to an adjacent vertex. We say a distribution D is solvable if starting from D , we can move a pebble to any vertex by a sequence of pebbling moves. The optimal pebbling number of a graph G is the smallest number of pebbles in a solvable distribution on G . It is known that every solvable distribution on the n -dimensional hypercube Q n contains at least ( 4 3 ) n pebbles. Fu, Huang, and Shiue, building on the work of Moews, used probabilistic methods to show that there are solvable distributions where the number of pebbles is in O ( ( 4 3 ) n n 3 2 ) , but hitherto, the number of pebbles in the best constructed distributions was in O ( 1.37 7 n ) . We use error-correcting codes to construct solvable distributions of pebbles on Q n in which the number of pebbles is in O ( 1.3 4 n ) . [ABSTRACT FROM AUTHOR]

Eighteen error field correction coils (EFCCs) consisting of copper conductor and epoxy resin are installed in the vacuum vessel of JT-60SA in order to correct magnetic fields caused by manufacturing and installation errors of superconducting coils. The EFCCs are supported by pedestals made of stainless steel 316 L, and the pedestal has spring bars made of NCF625. The pedestals need to withstand electromagnetic force induced by EFCC current and magnetic field during plasma operations. They also need to allow relative displacement between the EFCC and the vacuum vessel during baking operations caused by the temperature difference between the vacuum vessel of 200 °C and EFCC of 40 °C. Diameter of the spring bars and connection structure for fixing the spring bars were designed through FEM analysis. [ABSTRACT FROM AUTHOR]

Quadratic residue (QR) codes have a high prospect on error correction for reliable data conveyance over channel with noise. This paper presents a fast algebraic scheme for decoding the binary (41, 21, 9) QR code for correcting up to 4 errors on an one-case-by-one-case basis, in which the calculation of unknown syndromes is eliminated and the conditions for checking for the various numbers of errors that exist in the received word are also simplified compared to those from Lin T. C. et al.'s algorithm, which is a traditional algebraic decoding algorithm (ADA). The computational complexity of the decoder performing the binary (41, 21, 9) QR code is analyzed thoroughly, which demonstrates that the proposed decoding scheme is faster, simpler, and more suitable for implementation than Lin T. C. et al.'s algorithm. Numerical emulation results demonstrate that the proposed decoding scheme achieves the same error-rate performance as Lin T. C. et al.'s algorithm, but it has a significantly decreased the complexity of this decoder in terms of the CPU time. [ABSTRACT FROM AUTHOR]