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This paper presents an optimization framework for sequential reconfiguration using an assortment of switching devices and repair process in distribution system restoration. Compared to existing studies, this paper considers types, capabilities and operational limits of different switching devices, making it applicable in practice. We develop a novel multi-phase method to find the optimal sequential operation of various switching devices and repair faulted areas. We consider circuit breakers, reclosers, sectionalizers, load breaker switches, and fuses. The switching operation problem is decomposed into two mixed-integer linear programming (MILP) subproblems. The first subproblem determines the optimal network topology and estimates the number of steps to reach that topology, while the second subproblem generates a sequence of switching operations to coordinate the switches. For repairing the faults, we design an MILP model that dispatches repair crews to clear faults and replace melted fuses. After clearing a fault, we update the topology of the network by generating a new sequence of switching operations, and the process continues until all faults are cleared. To improve the computational efficiency, a network reduction algorithm is developed to group line sections, such that only switchable sections are present in the reduced network. The proposed method is validated on the IEEE 123-bus and 8500-bus systems. [ABSTRACT FROM AUTHOR]

This paper presents the effect of stray capacitances in bipolar (negative and/or positive) pulses generated by the two different topologies of the solid-state Marx modulators. According to the analysis, the stray capacitances influence the energy transfer from the Marx modulator capacitors to the load affecting the bipolar (negative and/or positive) pulse rise time. This paper deals with the structure design to reduce the influence of the stray capacitance and to improve the pulse rise time of these bipolar solid-state Marx modulators. A four-stage laboratory prototype of the two topologies has been assembled using 1200-V insulated gate bipolar transistors and diodes, operating with 1000-V dc input voltage and 1-kHz frequency, producing 4-kV bipolar pulses, with 5- \mu \texts pulse duration and 120-ns rise time, into a resistive load. [ABSTRACT FROM PUBLISHER]

A hybrid switched-capacitor/interleaved boost converter able to provide a high voltage gain and to cancel the input current ripple at a preselected duty cycle was recently presented in the literature. This paper extends that work by proposing an optimized switching strategy for operating conditions at other values of duty cycle. The switching strategy effect on the converter's voltage gain and input current ripple is quantified and compared against the performance under the conventional switching strategy. The approach is validated in the laboratory through hardware prototyping. [ABSTRACT FROM PUBLISHER]

A circuit configuration, a circuit topological family, a buck-mode active clamped circuit, and an instantaneous output voltage feedback control strategy of combined bidirectional buck–boost dc–dc chopper-mode inverter with high-frequency (HF) link (HFL) were proposed and fully investigated in this paper. The steady principle characteristic and the design criteria for the key circuit parameters were given in this paper. The circuit configuration is composed of two identical isolated bidirectional buck–boost dc–dc choppers with the same input and output filters. These two choppers in parallel at input end and in series at output end generate unipolarity sinusoidal pulsewidth modulation current waveforms with positive and negative half low-frequency cycles separately. The circuit topological family includes four circuit topologies, such as one-transistor mode. Taking the one-transistor mode circuit topology as an example, the 750VA48VDC/220V50HzAC prototype is designed and implemented. The theoretical analysis and principle test show the inverters have excellent performance. [ABSTRACT FROM PUBLISHER]

In applications that demand single-input dual-output (SIDO) or dual-input single-output (DISO) dc–dc converters, employing two separate single-input single-output (SISO) converters is a solution. However, the number of components is doubled, resulting in high overall cost. In order to reduce costs, this paper proposes a novel topology synthesis methodology, with which a variety of SIDO and DISO dc–dc converters with reduced components can be derived. The principle of topology synthesis states that integrated SIDO and DISO dc–dc converters can be easily developed from conventional SISO converters by replacing a diode with a basic cell inclusive of additional input/output port. The principle is effective for many SISO dc–dc converters, and as an example, topology synthesis based on buck, boost, buck–boost, Cuk, sepic, and zeta SISO converters is performed in this paper. In order to achieve better understanding of the proposed converters, the integrated SIDO Cuk converter is specifically analyzed and experimentally verified. In comparison with the conventional scheme of two separate SISO Cuk converters, good cross regulation is retained while the number of diodes, inductors, and capacitors is reduced in the proposed SIDO Cuk converter. In addition, zero-voltage-switching operation of one switch is achieved, contributing to lower switching losses. Finally, a prototype circuit with 48-V input and 156 V/1 A, 24 V/4 A outputs is built to validate the theoretical analysis. [ABSTRACT FROM PUBLISHER]

In this paper, direct torque control (DTC) of five-phase induction motor (FPIM) is implemented using three-level neutral point clamped (TL-NPC) inverter. One of the advantages of three-level inverter over two-level one for DTC operation is the low torque ripple. Also TL-NPC inverter through space vector modulation technique gives low $ dv/dt$ transition with better voltage waveform. By applying conventional lookup table for DTC, the TL-NPC inverter does not ensures lower $dv/dt$ transition. In this paper, a novel switching scheme for DTC of FPIM using TL-NPC inverter is proposed that ensures the low $ dv/dt$ transition and balancing of dc-link capacitor voltages of TL-NPC inverter. To form the lookup table for DTC operation, instead of using voltage vectors directly, virtual vectors (VVs) are utilized. Two switching states are used in one sample time to generate a VV in $\alpha \beta$ plane, which gives zero resultant voltage in $ xy$ plane. The switching strategy ensures low number of transitions to reduce the switching losses. The switching state redundancies are used in a novel way to balance the dc-link capacitor voltages without using any additional hardware. The proposed technique to balance the dc-link capacitor voltage gives lower switching frequency. The MATLAB/Simulink environment is used for the simulation and the results are validated through experiments. [ABSTRACT FROM AUTHOR]

This paper presents the performance analysis and comparison of two types of bidirectional dc–dc converters—cascaded buck–boost capacitor in the middle and cascaded buck–boost inductor in the middle for use in plug-in electric and hybrid electric vehicles. The comparison of the two converters is based on device requirements, rating of switches and components, control strategy, and performance. Each of the converter topologies has some advantages over the other in certain aspects. Efficiency analysis has been carried out for specific scenarios in vehicle applications. The simulation and experimental results are provided for both converter types. [ABSTRACT FROM PUBLISHER]

This paper presents an asymmetrical cascaded multilevel inverter based on a five-level transistor-clamped H-bridge power cell. A two-cell configuration with a dc link voltage ratio of 4 : 1 is presented. The modulation method is based on the fundamental frequency switching. An analysis of the inverter output voltage and harmonics is presented. Injection of the third harmonic voltage as to maximize the output voltage and the issue of the inverse power flow or regeneration in the low-voltage cell are presented. The prototype of the proposed inverter was built, and its functionality was verified through experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a new T-type inverter topology based on multistate switching cell is proposed. The topology presents five-level voltage before the output $LC$ filter, providing high-order harmonics that are easily filtered. In this topology, the output filter ripple frequency is twice the switching frequency, therefore reducing the magnetic weight and volume. Other characteristics of the inverter are current sharing through the devices, facilitating its losses' dissipation, due to increased contact area and few involved components in the current flow path. In order to verify its feasibility, a design example, as well as experimental results, for a 5-kW prototype is presented in this paper. [ABSTRACT FROM AUTHOR]

The emergence of applications which require high-voltage switches has created a tendency to use semiconductor device series stacks. These series stacks permit operation at blocking voltages above semiconductor elements’ nominal voltage. Insulated-gate bipolar transistors (IGBT) are currently utilized for controllability and switching speed, when these topologies are employed. The main challenge therewith is guaranteeing voltage balance between IGBTs, both when blocked and when switching transistors. Most of the methods which have been proposed to mitigate static and dynamic voltage unbalances increase transistor losses. The series stack loss-less high voltage switch (LHVS) which mitigates voltage unbalances, thus reducing switching losses, is presented in this paper. LHVS consists of a circuit, which ensures soft IGBT switching, an energy recovery circuit, and a gate delay compensation circuit. Additionally, the insulation voltage level is guaranteed to be equal between control circuit and high-voltage side of each IGBT. The operating principle of the LHVS is detailed in this paper, as is experimental validation which has been performed for three series stack modules. Static unbalances are reduced to 1%, while the differences between collector–emitter voltage curves in switching “on” do not surpass 8 ns, and switching losses are reduced by 41%, as compared to the hard-switching topology. [ABSTRACT FROM AUTHOR]

This paper introduces a novel five-level nested neutral point piloted (NNPP) converter and analyzes the operating principle of five-level NNPP converter. This paper presents a novel space vector pulse width modulation (SVPWM) algorithm based on gh coordinate for five-level NNPP converter. First, the common-mode voltage is reduced by choosing the appropriate redundant switching states. After that, the floating-capacitor voltage balance control strategy is presented. The appropriate switch combinations of each phase are determined by the control requirements of floating-capacitor voltages respectively and the hardware mapping method of the switching states is presented. Furthermore, the neutral-point voltage balance control strategy is presented. In order to balance the dc-link capacitor voltages, the seven-segment switching sequence is selected according to the control requirements of dc-link capacitor voltages and the neutral-point voltage regulatory factor is introduced to regulate the durations of the redundant switching states in a switching cycle. Finally, the validity of the novel SVPWM algorithm with decoupling control strategies of floating-capacitor voltages and dc-link capacitor voltages is verified by the experimental results of five-level NNPP converter under steady-state and dynamic conditions. [ABSTRACT FROM AUTHOR]

The performance of a novel three-phase four-leg fault-tolerant T-type inverter topology is introduced in this paper. This inverter topology provides a fault-tolerant solution to any open-circuit and certain short-circuit switching faults in the power devices. During any of the fault-tolerant operation modes for these device faults, there is no derating required in the inverter output voltage or output power. In addition, overload capability is increased in this new T-type inverter compared to that in the conventional three-level T-type inverter. Such increase in inverter overload capability is due to the utilization of the redundant leg for overload current sharing with other main phase legs under healthy condition. Moreover, if the redundant phase leg is composed of silicon carbide metal-oxide-semiconductor field-effect transistors, quasi-zero-voltage switching, and zero-current switching of the silicon insulated-gate bipolar transistors (IGBTs) in the conventional main phase legs can be achieved at certain switching states, which can significantly relieve the thermal stress on the outer IGBTs and improve the whole inverter efficiency. Simulation and experimental results are given to verify the efficacy and merits of this high-performance fault-tolerant T-type inverter topology. [ABSTRACT FROM PUBLISHER]

Switched boost inverter (SBI) is a single-stage power converter derived from Inverse Watkins Johnson topology. Unlike the traditional buck-type voltage source inverter (VSI), the SBI can produce an ac output voltage that is either greater or less than the available dc input voltage. Also, the SBI exhibits better electromagnetic interference noise immunity when compared to the VSI, which enables compact design of the power converter. Another advantage of SBI is that it can supply both dc and ac loads simultaneously from a single dc input. These features make the SBI suitable for dc nanogrid applications. In this paper, the SBI is proposed as a power electronic interface in dc nanogrid. The structure and advantages of the proposed SBI-based nanogrid are discussed in detail. This paper also presents a dq synchronous-reference-frame-based controller for SBI, which regulates both dc and ac bus voltages of the nanogrid to their respective reference values under steady state as well as under dynamic load variation in the nanogrid. The control system of SBI has been experimentally validated using a 0.5-kW laboratory prototype of the SBI supplying both dc and ac loads simultaneously, and the relevant experimental results are given in this paper. The low cross regulation and the dynamic performance of the control system have also been verified experimentally for a 20% step change in either dc or ac load of SBI. These experimental results confirm the suitability of the SBI and its closed-loop control strategy for dc nanogrid applications. [ABSTRACT FROM AUTHOR]

Switching power supplies are sources of noise for sensitive circuits. Converters should comply with electromagnetic compatibility (EMC) rules so that the electromagnetic interference (EMI) caused by switching cannot interfere with the normal operation of adjacent circuits and also the converter itself. The produced interference can be in the form of conduction or radiation. In this paper, some techniques are used in switching converters to suppress EMI with emphasis on the conduction form. EMI analysis and evaluation of a conventional flyback converter and a proposed zero-current transition (ZCT) flyback converter is achieved by simulation and experimental results. In addition to evaluating some EMI suppression techniques, the main objective of this paper is to improve EMI in the topology design stage. The operating modes of the improved ZCT flyback are discussed. In addition to the efficiency improvement, the amount of EMI reduction of this ZCT flyback and the effectiveness of some EMI reduction techniques are shown by practical implementation. [ABSTRACT FROM AUTHOR]

This paper presents an analytical and experimental comparison of a two-phase buck converter and a two-phase, series capacitor buck converter. The limitations of a conventional buck converter in high-current (10 A or more), and high-frequency (HF, 3–30 MHz) point-of-load voltage regulators with large voltage conversion ratios (10-to-1) are highlighted. The series capacitor buck converter exhibits desirable characteristics at HF, including lower switching loss, less inductor current ripple, automatic phase current balancing, duty ratio extension, and soft charging of the energy transfer capacitor. Analysis of the topologies indicates that switching loss and inductor core loss can dominate at HF. Results from side-by-side 12 V input, 1.2 V output hardware prototypes demonstrate that the series capacitor buck converter has up to 12 percentage points higher efficiency at 3 MHz and reduces power loss by up to 33% at full load (10 A). Some guidelines for inductor selection are provided, and a switch stress comparison reveals that the maximum converter switch stress is reduced by 30%. [ABSTRACT FROM AUTHOR]

Parallel ac-link universal power converters are a relatively new class of power converters that can be configured as dc–dc, dc–ac, ac–dc, and ac–ac. These converters are extensions of a buck–boost converter in which the current of the inductor is alternating and the input and output can have any number of phases with any forms, voltage amplitude, or frequency. By placing a small capacitor in parallel with the link inductor, all the switches can benefit from soft switching. The main limitation of the parallel ac-link universal power converter is its large number of switches. A three-phase ac–ac configuration requires 24 unidirectional switches. This paper proposes two topologies based on the parallel ac-link universal power converters that significantly reduce the number of switches. One of the proposed topologies reduces the number of switches in a three-phase ac–ac configuration to 16. The other topology reduces the number of switches to 10. The latter can offer galvanic isolation with only a single-phase high-frequency transformer. This paper presents the principles of the operation of the proposed topologies and evaluates them through simulation and experiments. [ABSTRACT FROM AUTHOR]

With the expansion and enhancement of the power transmission network, short-circuit current (SCC) has become a major concern in grid operations. While transmission switching is one effective solution to reduce the SCC without investing in additional equipment, switching lines could threaten system N-1 security. To find an efficient, and secure, yet economic switching solution, this paper proposes an optimal transmission switching model with SCC limitation and N-1 reliability. As the relationship between SCC and integer variables associated with the line states is coupled, nonlinear and difficult to explicitly express, an effective linearization method is proposed. Theoretical analysis of the linearization error is performed using an illustrative example. Case studies have shown that the linearization error is generally small and decreases rapidly with the increase of electrical distance. Based on the linearized expression for SCC, a transmission switching model with SCC limitation and N-1 reliability constraints is proposed. Furthermore, to assure the calculation accuracy for the SCC, an iterative algorithm is designed to compensate for the linearization error. Case studies on the modified IEEE 30-bus, 118-bus and practically-sized 300-bus systems validate the effectiveness of the proposed model and algorithm. The solving efficiency of the model is investigated and discussed as well. [ABSTRACT FROM PUBLISHER]

Multilevel converters (MLCs) have emerged as standard power electronic converters for medium-voltage high-power industrial applications. Owing to dominating device switching losses in high-power applications, it is preferable to use low device switching frequency (LDSF) modulation techniques. Then, it is possible to achieve higher device utilization, higher converter efficiency, and reduced cooling requirements. However, there exists a tradeoff between device switching frequency and harmonic distortion of converter output currents. Therefore, the main challenge for LDSF modulation techniques is to minimize the harmonic distortion of the output currents. The goal of this paper is to provide a review of various LDSF modulation techniques proposed in the literature and also discuss in detail about one of the emerging LDSF control techniques known as synchronous optimal pulsewidth modulation. Finally, challenges to LDSF modulation techniques for emerging multilevel topologies and future trends in applications of MLCs are discussed to motivate further research, to enhance the proposed LDSF techniques, and to explore for new alternatives. [ABSTRACT FROM PUBLISHER]

This paper presents a unified framework for the modeling, analysis, and design of load-independent Class E and Class EF inverters and rectifiers. These circuits are able to maintain zero-voltage switching and, hence, high efficiency for a wide load range without requiring tuning or use of a feedback loop, and to simultaneously achieve a constant amplitude ac voltage or current in inversion and a constant dc output voltage or current in rectification. As switching frequencies are gradually stepping into the megahertz (MHz) region with the use of wide-bandgap (WBG) devices such as GaN and SiC, switching loss, implementing fast control loops, and current sensing become a challenge, which load-independent operation is able to address, thus allowing exploitation of the high-frequency capability of WBG devices. The traditional Class E and EF topologies are first presented, and the conditions for load-independent operation are derived mathematically; then, a thorough analytical characterization of the circuit performance is carried out in terms of voltage and current stresses and the power-output capability. From this, design contours and tables are presented to enable the rapid implementation of these converters given particular power and load requirements. Three different design examples are used to showcase the capability of these converters in typical MHz power conversion applications using the design equations and methods presented in this paper. The design examples are chosen toward enabling efficient and high-power-density MHz converters for wireless power transfer (WPT) applications and dc/dc conversion. Specifically, a 150-W 13.56-MHz Class EF inverter for WPT, a 150-W 10-MHz miniature Class E boost converter, and a lightweight wirelessly powered drone using a 20-W 13.56-MHz Class E synchronous rectifier have been designed and are presented here. [ABSTRACT FROM AUTHOR]

Several single-stage topologies have been introduced since kicking off the three-phase Z-source inverter (ZSI), and among these topologies, the quasi-ZSI (qZSI) is the most common one due to its simple structure and continuous input current. Furthermore, different modulation strategies, utilizing multiple reference signals, have been developed as well. However, prior art modulation methods have some demerits, such as the complexity of generating the gate signals, the increased number of switch commutations with continuous commutation at high current level during the entire fundamental cycle, and the multiple commutations at a time. Hence, this paper proposes two modified space vector modulation strategies, aimed at the reduction of the qZSI number of switch commutations at high current level for shorter periods during the fundamental cycle, i.e., reducing the switching loss, simplifying the generation of the gate signals by utilizing only three reference signals, and achieving a single-switch commutation at a time. These modulation strategies are analyzed and compared to the conventional ones, where a reduced-scale 1-kVA three-phase qZSI is designed and simulated using these different modulation strategies. Finally, the 1-kVA three-phase qZSI is implemented experimentally to validate the performance of the proposed modulation strategies and verify the reported analysis. [ABSTRACT FROM PUBLISHER]

This paper presents the concept of three-phase module-integrated converters (MICs) incorporated in grid-tied large-scale photovoltaic (PV) systems. The current-source converter with dc voltage boost capability, namely the single-stage power conversion system, is proposed for the three-phase PV MIC system. A model predictive scheme with low switching frequency is designed to control the proposed topology in such a way that provides a certain amount of active and reactive power in steady-state operation and also provides a proper ratio of reactive power under transient conditions to meet the low-voltage ride through regulations. To predict the future behavior of current control values and switching states, a discrete-time model of the MIC is developed in the synchronous reference frame. It is demonstrated that the injected active and reactive power can be controlled by minimizing the cost function introduced in the predictive switching algorithm. The proposed structure is simulated in MATLAB/SIMULINK software. An experimental verification is provided to justify the performance of the proposed control method through a 300-VA laboratory prototype. The results verify the desired performance of the proposed control scheme for exchanging both active and reactive powers between the PV MIC and the grid within different operating conditions. [ABSTRACT FROM AUTHOR]

In this paper, a soft-switching topology is proposed for the bidirectional dc–dc converter. In order to achieve soft-switching conditions, the auxiliary circuits including a small inductor and two capacitors are introduced to the bidirectional dc–dc converter. By generating and keeping a recycle current in the auxiliary circuits, the proposed topology can provide soft-switching conditions for both switches of the bidirectional dc–dc converter in fixed frequency control application. Meanwhile, no auxiliary switches are introduced. Due to the existence of the auxiliary circuits, the proposed topology can also reduce the current ripple in the main inductor. Based on this soft-switching method, a family of bidirectional soft-switching dc–dc topologies is derived. These topologies have the similar structures and the same characteristics. The topology deduction, operating principles, and design guidelines are presented in detail. Finally, an experimental prototype is built to verify the analysis and characteristics of the proposed topologies. [ABSTRACT FROM PUBLISHER]

The series-resonant dc–dc converter (SRC) is widely applied in a large range of voltage and power. In most applications, fault tolerance is a highly desired feature and it is obtained through redundancy. This paper proposes a fault-tolerance solution for the SRC, which could drastically reduce the need of redundancy. Using the proposed scheme, the full-bridge-based SRC or multilevel-based SRC can be reconfigured in a half-bridge topology, in order to keep the converter operational even with the failure (open circuit or short circuit) of one switch. Since the proposed scheme can be applied to the full-bridge-SRC and multilevel SRC, a family of fault-tolerant converter is proposed in this work. The advantages of the proposed approach are minimum of additional hardware and no deterioration of the converter efficiency. The proposed fault-tolerance solution was experimentally tested in a 10 kW SRC prototype with input voltage of 700–600 V. A short-circuit fault in a semiconductor is tested and the results confirm the effectiveness of the proposed approach. [ABSTRACT FROM PUBLISHER]

Transformer-less grid-connected photovoltaic (PV) systems face the challenge of keeping low leakage current due to their nonisolation configurations. To better attenuate the leakage current in the single-phase systems, a few neutral-point-clamped (NPC) topologies have been proposed. This paper further proposes an active NPC method by only employing one additional switch to connect the midpoint dc link and the freewheeling circuit of traditional single-phase PV inverters. After exploring the operational principles of freewheeling circuits, the construction method and the implementation of active NPC circuits in transformer-less single-phase inverters are elaborated in detail. Since only the leakage current flows through the additional NPC switch, the presented single-phase NPC inverters could still maintain the high operational efficiency with the further attenuated leakage current. The experimental results verified the theoretical findings. [ABSTRACT FROM PUBLISHER]

This paper presents a generalized multilevel direct power control (ML-DPC) scheme for grid-connected multilevel power converters. The proposed method extends the original DPC operating principle by considering only the closest subset of two-level voltage vectors to the present switching state. The implementation of this principle requires the power derivatives for feedback, which can present numerical problems when applied experimentally, mainly due to high measurement noise sensitivity. Therefore, a derivative estimator is proposed based on the converter-grid model in the synchronous reference frame. In addition, a virtual flux observer is developed to achieve synchronization and improve robustness in the presence of grid voltage harmonics. The proposed method is applicable to any multilevel converter topology of any number of levels. In this paper, simulations and experimental results are presented for a seven-level cascaded H-bridge converter. [ABSTRACT FROM AUTHOR]

This paper introduces load shed recovery actions for transmission networks by presenting the dc optimal load shed recovery with transmission switching model (DCOLSR-TS). The model seeks to reduce the amount of load shed, which may result due to transmission line and/or generator contingencies, by modifying the bulk power system topology. Since solving DCOLSR-TS is computationally difficult, the current work also develops a heuristic (MIP-H), which improves the system topology while specifying the required sequence of switching operations. Experimental results on a list of N-1 and N-2 critical contingencies of the IEEE 118-bus test case demonstrate the advantages of utilizing MIP-H for both online load shed recovery and recurring contingency-response analysis. This is reinforced by the introduction of a parallelized version of the heuristic (Par-MIP-H), which solves the list of critical contingencies close to 5x faster than MIP-H with 8 cores and up to 14x faster with increased computational resources. The current work also tests MIP-H on a real-life, large-scale network in order to measure the computational performance of this tool on a real-world implementation. [ABSTRACT FROM AUTHOR]

In this paper, we show a new bandstop filter circuit topology. Unlike conventional bandstop filter circuit topologies, the new circuit topology has inter-resonator coupling structures. The presence of these inter-resonator coupling structures enables convenient switching from a bandstop to a bandpass filter. Using the new bandstop filter topology, this paper demonstrates a design of a frequency-agile bandstop-to-bandpass switchable filter. The filter is composed of tunable substrate-integrated cavity resonators and can be switched to have either a bandstop or bandpass response. Switching is achieved by turning on and off switches placed within the filter structure. A prototype of the proposed design is fabricated and the concept is verified experimentally. [ABSTRACT FROM AUTHOR]

In conventional integrated circuit technologies, a grounded metal guard ring (MGR) is widely used to mitigate the coupling effect between any pair of inductors. Full-wave electromagnetic (EM) simulation results indicate that the guard ring size can significantly affect the inductance value of a single-turn planar inductor. This paper proposes a switchable artificial grounded MGR technique that can not only serve as a guard ring but also change the inductance. Accordingly, an inductor, featuring switchable inductance and high quality factor, is developed for a 60-GHz millimeter-wave wide-frequency tuning range (wide-FTR) and low phase-noise voltage-controlled oscillator (VCO) in 90-nm bulk CMOS technology. The VCO testkey achieves a total tuning range of 9.43 GHz (17%). The measured phase noise levels are -92.2 and -119 dBc/Hz at 1- and 10-MHz offsets, respectively. The experimental results demonstrate that the proposed inductor topology offers the VCO an increase of 36% in the FTR and a competitive performance in phase noise, as contrasted with a conventional varactor-tuned VCO. This VCO achieves a record of -188 dBc/Hz for the \FOMT. [ABSTRACT FROM PUBLISHER]

Photovoltaic (PV) systems having rechargeable batteries are prone to be complex and costly because multiple converters are necessary to individually regulate a load, PV panel, and battery. This paper proposes novel nonisolated multiport converters (MPCs) integrating a bidirectional pulsewidth modulation (PWM) converter and phase-shift-switched capacitor converter (PS-SCC) for standalone PV systems. A PWM converter and PS-SCC are integrated by reducing the total switch count, realizing the simplified system and circuit. In the proposed MPCs, two control freedoms of duty cycle and phase shift angle are manipulated to individually regulate the load, PV panel, and/or battery. The detailed operation analysis was performed to mathematically derive gain characteristics and zero voltage switching operation boundaries. For the battery discharging mode, in which the PV panel is not available and the MPC behaves as a single-input–single-output converter with two control freedoms available, the optimized control scheme achieving the lowest rms current is also proposed to maximize power conversion efficiencies. Various kinds of experimental verification tests using a 200-W prototype were performed to verify the theoretical analysis and to demonstrate the performance of the proposed MPC. [ABSTRACT FROM AUTHOR]

Recently multilevel inverters (MLIs) have received wide attention from industry and academia, as they are changing into a viable technology for diverse applications. To produce high-quality output using less switch count, development of novel reduced switch MLI (RS MLI) topologies has been a focus of current research theme. This paper presents design and control of a switched-diode dual source single switch MLI (SDDS MLI). The generalized SDDS MLI is first designed using an asymmetric basic unit. Proposed SDDS MLI requires less switch count and driver circuit count compared with the few recently developed RS MLI topologies. To improve the voltage quality by eliminating targeted low-order harmonics, a modified version of fish swarm optimization algorithm is examined for computing optimum switching angles required to control the SDDS MLI. Moreover, suitability and superiority of the derived algorithm are established by comparing with traditional selective harmonic elimination techniques. The developed topology is investigated through several MATLAB simulations as well as experimental tests in the laboratory applying the modified control approach. [ABSTRACT FROM AUTHOR]

Pulse-width-modulated (PWM) converters have been widely applied for power processing, and they are typically the stems of other types of converters, such as quasi-resonant, Z-source, and switched-inductor hybrid converters. Development of PWM converters has been spanning over a century, starting from the buck converter. The well-known PWM converters include buck, boost, buck–boost, Ćuk, single ended primary inductive converter (SEPIC), zeta, Z-source, quasi-Z source, etc. Many attempts have been proposed to develop these converters based mostly on canonical cell concepts and by introducing extra LC filters to the cells. This paper presents an enhancement to the layer and graft schemes by introducing the ideas of dc voltage/current offsetting, capacitor/inductor component splitting, diode grafting, and inverse operation of PWM converters. The PWM converters, which can be operated in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), therefore can be synthesized systematically according to decoded transfer gains. Decoding and synthesizing PWM converters uniquely bridge transfer gains to converter topologies and provide readers a comprehensive understanding of PWM-converter evolution from the original converter, the buck converter. Additionally, in this paper, the Ćuk, SEPIC, and zeta converters all with the same transfer gain of $D/(1 - D)$ are proved to be equivalent to the buck–boost converter with an extra LC filter. For further illustrating the proposed approaches, various types of Z-source converters, switched-capacitor/switched-inductor hybrid converters, and a single-stage interleaved converter are reviewed, and new PWM converters are developed. [ABSTRACT FROM AUTHOR]

In this paper, a new cascaded nonlinear controller has been designed and implemented on the packed U-cell (PUC) seven-level inverter. The proposed controller has been designed based on a simplified model of PUC inverter and consists of a voltage controller as an outer loop and a current controller as an inner loop. The outer loop regulates the PUC inverter capacitor voltage as the second dc bus. The inner loop is in charge of controlling the flowing current, which is also used to charge and discharge that capacitor. The main goal of the whole system is to keep the dc capacitor voltage at a certain level results in generating a smooth and quasi-sine-wave seven-level voltage waveform at the output of the inverter with low switching frequency. The proposed controller performance is verified through experimental tests. Practical results prove the good dynamic performance of the controller in fixing the PUC capacitor voltage for various and variable load conditions and yet generating low-harmonic seven-level voltage waveform to deliver power to the loads. Operation as an uninterruptible power supply (UPS) or ac loads interface for photovoltaic energy conversion applications is targeted. [ABSTRACT FROM AUTHOR]

This paper proposes a novel dc–dc converter topology to achieve an ultrahigh step-up ratio while maintaining a high conversion efficiency. It adopts a three degree of freedom approach in the circuit design. It also demonstrates the flexibility of the proposed converter to combine with the features of modularity, electrical isolation, soft-switching, low voltage stress on switching devices, and is thus considered to be an improved topology over traditional dc–dc converters. New control strategies including the two-section output voltage control and cell idle control are also developed to improve the converter performance. With the cell idle control, the secondary winding inductance of the idle module is bypassed to decrease its power loss. A 400-W dc–dc converter is prototyped and tested to verify the proposed techniques, in addition to a simulation study. The step-up conversion ratio can reach 1:14 with a peak efficiency of 94% and the proposed techniques can be applied to a wide range of high voltage and high power distributed generation and dc power transmission. [ABSTRACT FROM AUTHOR]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]

This paper proposes a new approach for the analysis of consensus of multi-agent systems subject to time-varying delayed control inputs and switching topology. The main contribution is a condition for consensus for a networked system based on linear matrix inequalities that takes into account the joint effect of time-varying delays and switching network topology. Topology changes are modeled using Markov jumps with uncertain rates of transitions. A practical example is shown to illustrate the main result in various scenarios. [ABSTRACT FROM PUBLISHER]

This paper proposes a new topology for an enhanced-boost Z-source inverter (ZSI) with combined two Z-impedance networks. By two Z-impedance networks and low shoot-through duty cycle, the proposed inverter produces high output voltage gain. In traditional ZSIs for high boosting voltage, a low modulation index is required; hence, under these conditions, the output voltage will have low quality with high total harmonic distortion. Compared with the conventional high-boost ZSI topologies, the proposed inverter uses shorter shoot-through duration and a larger modulation index to improve the output waveform quality. Comparison between the proposed topology and previously proposed schemes, in terms of inductor numbers, voltage and current stresses on elements, sizes of inductors and capacitors, efficiency, and switching device product (SDP) factors of diodes, is made, and the results verify the priority of the proposed topology. The operating principle of the proposed topology is analyzed in detail. Both simulation and experimental results verify the high performance of the proposed inverter. [ABSTRACT FROM PUBLISHER]

Series–parallel forward dc–dc converter system is a good option in high-voltage high-power applications. A switch fault, in this converter, should be detected as soon as possible, to avoid further damage and save maintenance cost. In this paper, a new switch fault diagnosis method, which treats output inductor voltages as diagnostic criteria, is proposed for this system. With the proposed method, expensive sensors are needless, since diagnostic signal can be easily acquired by adding a small auxiliary winding into inductor magnetic core. Based on the feature of diagnostic signals in such a system, a low-cost diagnostic circuit is designed. The failed module caused by open-circuit fault or short-circuit fault could be detected within one switching period, allowing for an immediate fault-tolerant action. This method also shows generality for different connections and buck-type isolated topologies. Besides, it works reliably under input-voltage variation and load step, and no misdiagnosis will occur during normal dynamic process. Finally, experimental result verifies the effectiveness of this method. The proposed scheme has a good potential to be applied in real applications for its simplicity and robustness. [ABSTRACT FROM AUTHOR]

Active pulsating power buffering (PPB) function can effectively reduce the twice-line frequency energy storage requirement in a single-phase rectifier. Existing single-phase solutions with active PPB must utilize more than two active switches in their circuits. Compared with conventional single-active-switch solutions without active PPB (e.g., a boost power-factor-correction (PFC) rectifier), the cost of additional semiconductor switches and gate drive circuitry in an active PPB-based rectifier may not be justified for low-power applications. This paper presents a family of single-switch single-phase rectifier with active PPB. Taking advantage of the on-time and off-time of a single switch, the proposed rectifiers are formulated by merging two converters that are duty and frequency controlled. The steady-state characteristics of these converters are analyzed. A step-by-step design procedure is provided, and an active control method for limiting the maximum switching frequency for wide-load-range operation is presented. A 100-W prototype is built for the demonstration of the proposed single-switch rectifier concept. It is envisaged that this concept, when combined with other circuit formulation techniques, e.g., partial power processing, dc-voltage feedback, may lead to new derivatives of single-switch rectifiers with more advanced features. [ABSTRACT FROM AUTHOR]

In this paper, a fixed switching frequency model predictive current controller is designed and implemented on a sensorless five-level packed U-cell (PUC5) inverter interfacing the utility. The predictive control methodology is based on a voltage vector generation technique for the cost function optimization by nullifying its derivative. The aim of the controller is to allow a fixed-frequency operation with no iterations while operating as a utility line current regulator. A pulsewidth modulator based on employing PUC5 redundant switching states fixes the PUC5 auxiliary dc bus capacitor voltage to its desired level with no necessity of a regulator; the overall technique reduces system complexity with less sensors and no loops in the predictive algorithm making it suitable for industrial applications. System discrete model is developed and experimental results verify the performance of the designed controller in making a fast response in regulating the grid current and balancing the capacitor voltage. [ABSTRACT FROM AUTHOR]

This paper proposes a family of multiport switched-capacitor multilevel inverter (SCMLI) topologies for high-frequency ac power distribution. It employs asymmetric dc voltage sources with a common ground that makes it ideal to be employed in renewable energy farms and modern electric vehicles. The proposed family of step-up SCMLI attains higher number of output voltage steps with optimum component count in comparison to several existing topologies. The problem of capacitor voltage balancing is solved as the capacitors are inherently charged to a finite voltage every half cycle. In-depth study on two staircase modulation strategies, namely, selective harmonic elimination and minimum total harmonic distortion (THD) scheme is presented with study on the variation of switching angles and THD with modulation indices under both schemes. Working principle and analysis are presented for the proposed family of topologies. Simulation outcomes are validated with experimental results under both the aforementioned modulation schemes with equal and unequal output voltage waveform steps. [ABSTRACT FROM AUTHOR]

A dual-input high step-up DC/DC converter with zero voltage turn-off (ZVT) auxiliary circuit is presented in this paper. The cost of whole photovoltaic (PV) power could be decreased significantly by the proposed converter because it allows two PV panels to be connected at the same time. ZVT auxiliary circuit provides soft switching in a wide range of load variations with six passive components. Turn-off switching losses could be decreased and the efficiency of the whole converter could be improved. In , the operation principle and performance characteristics of the proposed converter have been analyzed and an 800 W experimental prototype has been built to validate the analytical results in. In , a dual-input maximum power point tracking (DMPPT) control algorithm has been designed for the proposed converter. Experimental results show that two PV panels can achieve the maximum power output state separately by the proposed DMPPT control algorithm. [ABSTRACT FROM AUTHOR]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]