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Due to the increasing size of integrated circuits (ICs), their design and optimization phases (i.e., computer-aided design, CAD) grow increasingly complex. At design time, a large design space needs to be explored to find an implementation that fulfills all specifications and then optimizes metrics like energy, area, delay, reliability, etc. At run time, a large configuration space needs to be searched to find the best set of parameters (e.g., voltage/frequency) to further optimize the system. Both spaces are infeasible for exhaustive search typically leading to heuristic optimization algorithms that find some tradeoff between design quality and computational overhead. Machine learning (ML) can build powerful models that have successfully been employed in related domains. In this survey, we categorize how ML may be used and is used for design-time and run-time optimization and exploration strategies of ICs. A metastudy of published techniques unveils areas in CAD that are well explored and underexplored with ML, as well as trends in the employed ML algorithms. We present a comprehensive categorization and summary of the state of the art on ML for CAD. Finally, we summarize the remaining challenges and promising open research directions. [ABSTRACT FROM AUTHOR]

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a set of the best papers selected from the 2018 IEEE International Solid-State Circuits Conference (ISSCC) that took place February 11–15, 2018, in San Francisco, CA, USA. This issue covers papers from the Analog, Power Management, Data Converters, RF, and Wireless committees. [ABSTRACT FROM AUTHOR]

A rule-based expert system for the integrated control and supervision of the dry-end sections of a paper machine is proposed. This. system is capable of recognizing all the normal and abnormal changes in process operating conditions, including acceleration of sections, threading of paper sheet, nip pressure activation, activation and deactivation of tension control loops, change of parent roll, and sheet break. A core part of the system is the supervision of the sensorless tension control of the dry-end sections, assuring its long-term stability. [ABSTRACT FROM AUTHOR]

Among recent technological advances, microfluidic biochips have been leading a prominent solution for healthcare and miniaturized bio-laboratories with the assurance of high sensitivity and reconfigurability. On increasing more unreliable communication networks day-by-day, technological shifts in the fields of communication and security are now converging. In today's cyber threat landscape, these microfluidic biochips are ripe targets of powerful cyber-attacks from different hackers or cyber-criminals. Hence, securing such systems is of paramount importance. This paper presents the security aspects of digital microfluidic biochip layout to protect the confidentiality of layout data from unscrupulous people and man-in-the-middle attacks. We propose an authentication mechanism with an error control mechanism that provides reliability, authentication, trustworthy and safety for both storage and communication of GDS, i.e., Graphical Design System, file generally used for digital microfluidic biochip layouts. Simulation results articulate the efficacy of the proposed security model without the overhead of the bioprotocol completion time. The proposed scheme, which used AES as an encryption algorithm with a 256-bit encryption key, has also shown a speedup of 6.0 (with 85% efficiency) faster than the prior efficient scheme. We hope to develop a secure layout design flow for biochips to achieve better resistance to any attack. [ABSTRACT FROM AUTHOR]

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation. [ABSTRACT FROM AUTHOR]

This paper deals with a low-cost method for the assembly of flexible substrate antennas and UHF RF identification silicon (Si) chips. Such a method exploits a magnetic coupling mechanism, thus not requiring for galvanic contacts between the Si chip and antenna itself. The magnetic coupling is established by a planar transformer, the primary and secondary windings of which are implemented on flexible substrate and Si chip, respectively. As a result, the Si chip can be assembled on the antenna with a mere placing and gluing process. First, the idea has been validated by theory. Electromagnetic simulations of a square heterogeneous transformer (1.0-mm side) show a maximum available power gain (MAG) of -0.4 dB at 868 MHz. In addition, the heterogeneous transformer is also quite tolerant with respect to misalignment between primary and secondary. An offset error of 150 \mu\ m reduces the MAG to -0.5 dB. A sub-optimal matching strategy, exploiting a simple on-chip capacitor, is then developed for antennas with 50-\Omega input impedances. Finally, the idea has been experimentally validated exploiting printed circuit board (PCB) prototypes. A PCB transformer (1.5-mm side) and a transformer rectifier (two-diode Dickson multiplier) have been fabricated and tested. Measurements indicates a MAG of -0.3 dB at 868 MHz for the transformer and the capability of the developed rectifier to supply a 220-\k\Omega load at 1.5 V with a -2-dBm input power. [ABSTRACT FROM AUTHOR]

The article profiles the authors of the research paper "Impact of heavy ion energy and nuclear interactions on single-event upset and latchup in integrated circuits," which won the 2007 Nuclear and Space Radiation Effects Conference (NSREC) Outstanding Conference Paper Award. They include Paul E. Dodd, general chairman for the 2008 NSREC, James R. Schwank, senior editor for radiation effects for the "IEEE Transactions on Nuclear Science," Marty R. Shaneyfelt, member-at-large of the Radiation Effects Steering Group, and James A. Felix, associate guest editor for the "IEEE Transactions on Nuclear Science."

This Special Issue of the IEEE Journal of Solid-State Circuits highlights some of the best papers presented at the 32nd Symposium on VLSI Circuits, held on June 18–22, 2018, at the Hilton Hawaiian Village, Honolulu, HI, USA. Industry and university engineers from all over the world reported innovative new techniques and state-of-the-art results. Papers presented covered a broad range of topics important to VLSI circuit and system designers, including topics that are also important to integrated circuit technology developers. [ABSTRACT FROM AUTHOR]

The papers in this special section were presented at the 2020 International Symposium on Integrated Circuits and Systems (ISICAS) in a virtual conference that was held from August 27–28, 2020. [ABSTRACT FROM AUTHOR]

The article presents the information on authors involved in the journal.

This Special Issue of the IEEE Journal of Solid-State Circuits highlights some of the best papers presented at the 30th Symposium on VLSI Circuits, held on June 14–17, 2016 at the Hilton Hawaiian Village, Honolulu, Hawaii. Industry and university engineers from all over the world reported innovative new techniques and state-of-the-art results. Papers presented covered a broad range of topics important to VLSI circuit and system designers, including topics also important to integrated circuit technology developers. [ABSTRACT FROM AUTHOR]

This paper describes a silicon receiver for a multiple-input multiple-output (MIMO) wireless channel that supports up to 28.8 Mb/s using a 4 × 4 QPSK configuration over a 5-MHz frequency selective channel. The architecture has two key components: a space-time equalizer that mitigates both spatial and temporal effects of the channel, and a maximum likelihood detector with approximate a posterior probability (ML-APP) soft estimates of the transmit vectors over the MIMO configuration. The space-time equalizer uses an adaptive tap training process that includes a pilot correlator to reduce adaptation noise. The device is 685 k effective logic gates (11.6 mm²) in 0.18-pm 6LM CMOS. [ABSTRACT FROM AUTHOR]

The IEEE International Solid-State Circuits Conference (ISSCC) is the premier global forum for presenting advances in solid-state circuits and system-on-a-chip. Every year since its first issue, the IEEE Journal of Solid-State Circuits has highlighted some well-received papers from the most recent ISSCC in special issues. This Special Issue covers the ISSCC Conference held in San Francisco, CA, USA, on February11–15, 2017. [ABSTRACT FROM AUTHOR]

High quality scholarship requires technical excellence but also connects the work to the primary references in the field. In this way, the reader advances their knowledge and gains perspective. The TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING supports these goals by recognizing the best paper chosen by the Associate Editors and reviewers. The winning paper was selected from 140 papers published by TSM in 2015. The winner is “An Algorithm of Multi-Subpopulation Parameters With Hybrid Estimation of Distribution for Semiconductor Scheduling With Constrained Waiting Time” by Hung-Kai Wang, Chen-Fu Chien, and Mitsuo Gen published in the August 2015 issue of the IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING (10.1109/TSM.2015.2439054). I congratulate the authors on their selection. [ABSTRACT FROM AUTHOR]

The rising cost of production testing for a system-on-a-chip (SoC) is one of the crucial matters to chip makers, due to long test time and costly automated-test-equipment. This paper proposes a spectral leakage-driven built-in self-test (BIST) scheme to precisely predict the nonlinearity of mixed-signal circuits in the loopback mode, thereby accomplishing cost-effectiveness (compared to previous BIST-based works). A digitally synthesized single-tone sinusoidal stimulus used for conventional harmonic testing is incoherently sampled by a device under test (DUT). The DUT output signal exhibits the correlation between the DUT harmonics and the spectral leakage introduced by the incoherent sampling. The DUT output signal is then fed to another DUT through a loopback path, so that the harmonics of a pair of DUTs are correlated with the spectral leakage on the loopback response; the magnitude of the spectral leakage is considered as a weighting factor on the harmonic magnitude of those DUTs. The correlation is quantitatively modeled as characteristic equations in , and postprocessing predicts the harmonics of the two individual DUTs, by simultaneously solving the characteristic equations using on-chip DSP core available in an SoC. Simulation and hardware measurements validated that this paper can be practically used for production testing by showing less than 0.3 and 0.6 dB of the prediction errors, respectively. [ABSTRACT FROM AUTHOR]

This paper discusses the evolution towards the first integrated radio-frequency identification (RFID)-enabled wireless sensor network infrastructure using ultra-high frequency/radio frequency (UHF/RF) RFID-enabled sensor nodes and inkjetprinted electronics technologies on flexible and paper substrates for the first time ever. The first sections highlight the unique capabilities of inkjet printed electronics as well as the benefits of using paper as the ultra-low-cost, conformal and environmentally friendly substrate for the mass-scale ubiquitous implementation of the first RFID-enabled wireless sensing applications. Various inkjet-printed antenna configurations are presented for enhanced-range compact RFID-enabled sensing platforms in "rugged" environments up to 7 GHz, followed by the discussion of their 2-D integration with integrated circuit (IC) and sensors on paper. This integration is extended to a power-scavenging "smart-shoe" batteryless integrated RFID module on paper that could be used for autonomous wearable sensing applications with enhanced range. The paper concludes discussing the details for establishing for the first time an asynchronous wireless link between the aforementioned RFID-tags and a widely used commercial wireless sensor network (WSN) mote using a simplified protocol; a paramount step that could potentially create ubiquitous ultra-low-cost sensor networks and large-scale RFID implementations eliminating the need of expensive RFID reader infrastructure and linking RFIDs to the mature level of WSNs. [ABSTRACT FROM AUTHOR]

The IEEE Transactions on Semiconductor Manufacturing congratulates Yonghwi Kwon and Youngsoo Shin whose paper Optical Proximity Correction Using Bidirectional Recurrent Neural Network With Attention Mechanism was selected as the Best paper for 2021. The paper was selected from all the papers that appeared in 2021 by a team of Associate Editors. This paper applied recurrent neural networks to optical proximity correction for lithographic processing for integrated circuits. The challenge in determining a correction value comes from correlation: correction of one segment affects the correction value of other segments due to the optical proximity effect. This paper broke new ground by showing that Recurrent Neural Networks, which has been mainly applied to time series data, can be effectively applied to spatial data. Clearly, Machine Learning is rapidly moving from R&D into full flow manufacturing where the interplay between each aspect of a single process step has exponential increased in complexity requiring new approaches. Three additional papers were recognized with an Honorable Mention: [ABSTRACT FROM AUTHOR]

It is known that the determination of the good-dice-in-bad-neighborhoods (GDBNs) has been regarded as an effective technique to reduce the value of the defect parts per million (DPPM) by identifying and rejecting the suspicious dice even though they are good in testing. Instead of examining eight immediate neighbors in a small-sized $3\times 3$ window or exploiting simple linear regression, a large-sized window can be used to recognize the broad-sighted neighborhoods and accurately infer the suspiciousness level for any given die. In this paper, the artificial neural networks (ANN)-based method can be proposed to solve the GDBN identification. Furthermore, two enhanced techniques can be further presented to improve the inference accuracy of the original ANN-based method by considering the variation of the time-dependent wafer patterns and the wafer-to-wafer relationship between two adjacent wafers. After applying the two enhanced techniques, the business profits can be improved in the new ANN-based method. Various experiments on two datasets clearly reveal the superiority of the proposed ANN-based method over the other existing methods. In addition to the reduction of the DPPM value, the new ANN-based method can achieve the 1.5X–2X better reduction in the cost of the return merchandise authorization (RMA). On the other hand, the experimental results show that the similar result can also be obtained in the other lower-yield products. By using the new ANN-based method, the relationships on bad dice cross wafers can be captured and the highly-accurate inference results can be simultaneously maintained. [ABSTRACT FROM AUTHOR]

This paper investigates the Gaussian state-dependent interference channel (IC) and Z-IC, in which two receivers are corrupted respectively by two different but correlated states that are noncausally known to two transmitters but are unknown to the receivers. Three interference regimes are studied, and the capacity region boundary or the sum capacity boundary is characterized either fully or partially under various channel parameters. In particular, the impact of the correlation between states on cancellation of state and interference as well as achievability of capacity is explored with numerical illustrations. For the very strong interference regime, the capacity region is achieved by the scheme where the two transmitters implement a cooperative dirty paper coding. For the strong but not very strong interference regime, the sum-rate capacity is characterized by rate splitting, layered dirty paper coding, and successive cancellation. For the weak interference regime, the sum-rate capacity is achieved via dirty paper coding individually at two receivers as well as treating interference as noise. This paper also provides the achievable region for the state-dependent IC with each state known at its corresponding transmitter. [ABSTRACT FROM AUTHOR]

The article presents information about the Best Paper Award by the journal "IEEE Transactions on Semiconductor Manufacturing." The paper entitled "Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction," by Michael Orshansky, Linda Milor and Chenming Hu has been recognized as the best paper published in the 2004 issue of the journal. This paper, which appeared in the February 2004 issue, has been chosen for its development of methods to measure and analyze spatial within-chip variations, to understand the impact that these variations have on circuit speed, and to compensate for these variations.

Editiroal. Discusses the contents of the Special Issue of the 'IEEE Journal of Solid-State Circuits.' Introduction of a self-biased phase-locked loop that implements of a novel filter structure; Challenges of high-speed IO design.

This paper presents a novel survey of high level synthesis (HLS) based hardware security approaches for reusable intellectual property (IP) cores used in consumer electronics and computing systems. A succinct review of all major HLS based hardware security approaches applied on reusable IP cores, along with their design flow and security analysis, is provided. The paper presents a detailed design flow of hardware integrated circuits (ICs) along with vulnerability points where potential attacks/threats are possible. Trustworthy and untrustworthy regimes in the design flow have also been highlighted in the discussion. Further, a discussion of detective and preventive control-based HLS hardware security approaches used for hardware IP cores has also been presented, including an analysis of prominent structural obfuscation, logic locking (logic encryption), and IP core protection (IPP) techniques. Each approach has been lucidly explained in terms of its threat model, algorithm, and security analysis. Finally, a security comparison of hardware IP obfuscation approaches in terms of strength of obfuscation security metric as well as a security comparison of IPP approaches in terms of probability of coincidence security metric, have also been introduced. [ABSTRACT FROM AUTHOR]

Introduces the themes of the research papers featured in the October 2005 Special Issue of the "IEEE Journal of Solid-State Circuits." Description of a high-efficiency C-band amplifier for satellite communication systems; Presentation of experimental circuits in the InP DHBT technology; Development of a 220-GHz low-noise amplifier for use in high-resolution active and passive millimeter-wave imaging systems.

Introduces a series of papers published in the 2003 IEEE Custome Integrated Circuits Conference.

Technology computer-aided design (TCAD) is an integral part of the development process of semiconductor technologies and devices, a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resulting devices often have an intricate 3-D structure and contain various specifically designed materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (material properties, interfaces, defects, and so on), to nanometric (quantum confinement, non-bulk properties, tunneling, ballistic transport, and so on), to full-chip dimensions (strain, heat transport, and so on), and time scales from femtoseconds (scattering, ferroelectric switching time, and so on) to seconds (trapping times, degradation, and so on). Voltages, currents, and charges have been scaled to such low levels that statistical effects and process variations have a strong impact. Devices based on new materials (e.g., 2-D crystals) and physical principles (ferroelectrics, magnetic materials, qubits, and so on) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools, and are often too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead, a TCAD tool chain is required which can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles, and the ensuing large-scale simulations and that make use of artificial intelligence for well-chosen (sub)routines to decrease the overall simulation time. This Special Issue features six invited and 18 regular papers that address these problems. [ABSTRACT FROM AUTHOR]

A Hybrid AC/DC microgrid (MG) can integrate distributed generation sources and distributed loads on the AC and DC side of the MG by eliminating many unnecessary power conversion devices, which is more flexible and efficient. However, to achieve reliable and economic operation of a hybrid AC/DC MG is challenging due to its complex structure. In this paper, a novel distributed event-triggered hierarchical control strategy is proposed to improve the economic operation of a hybrid AC/DC MG. For the primary control, distributed local controls of AC DGs, DC DGs, and interlinking converters (ICs) are realized by adopting the droop control method. For the secondary control, the distributed economic dispatch, distributed average bus voltage discovery, and distributed proportional power-sharing algorithms are first proposed; then, control objectives of voltage and frequency restoration and economic operation of the hybrid AC/DC MG are realized based upon the developed algorithms. Furthermore, the distributed secondary control is built upon an event-triggered mechanism developed in this paper, which can reduce the communication burden. The simulation results demonstrate the effectiveness of the proposed control strategy. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM PUBLISHER]

Vertical interconnects used in monolithic 3-D integrated circuits (3-D ICs), so-called monolithic interlayer vias (MIVs), are as small as local vias. Thus, redesigning an existing 2-D IC layout in a monolithic 3-D IC generally results in shorter wire length than the 2-D IC layout. In addition, MIVs have almost negligible resistance and capacitance, so their impact on signal delay is very small. Thus, redesigning a 2-D IC layout in a monolithic 3-D IC is expected to improve its performance significantly. Some researchers designed several monolithic 3-D IC layouts and showed their timing benefits in the literature. In this paper, we present analytical models for performance (timing) benefits of multitier gate-level monolithic 3-D ICs. The analytical models we develop in this paper can be used to quickly estimate the performance benefits multitier gate-level monolithic 3-D integration provides without physically redesigning 2-D IC layouts in 3-D. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

The memristor-based memory cell design is getting renewed attention in recent years due to its high speed and low power consumption. This paper aims at designing a novel hybrid memory cell incorporating a minimum number of transistors for a rapid bidirectional write operation. The read stability is one of the key elements for high efficiency and superior performance in memory. The memory cell in this paper was designed undertaking adequate measures for maintaining the stability in successive reads without any refresh operation. Extensive simulation experiments were conducted using 32-nm predictive technology model transistors and the results demonstrate superb performance and sound stability of the proposed memory cell in terms of read/write time as well as switching power consumptions. [ABSTRACT FROM PUBLISHER]

Novel design techniques for efficient testability are developed and have been implemented in a 14-/16-nm bulk FinFET node technology characterization vehicle. The result of this paper was the measurement of over 300 000 SETs across 12 combinational logic variants and 415 000 SEUs in three D-flip-flop designs over a large test matrix of heavy-ion linear energy transfer, angle of incidence, and supply voltage in only 319 test runs with a total test time of 108 h. A similar-sized data set with equivalent technology coverage, using the traditional serial testing approach as used in previous work, would typically require thousands of test runs and a significant number of additional hours of testing. The methodologies developed in this paper are technology agnostic and have provided the capability to efficiently characterize the radiation-induced response of the 14-/16-nm FinFET technology generation and yielded insights for assessing the feasibility for incorporation in systems requiring radiation resiliency. [ABSTRACT FROM PUBLISHER]

This issue of the IEEE Journal of Solid-State Circuits (JSSC) includes some of the highlights of the best papers from the 2011 Asian Solid-State Circuits Conference (A-SSCC), which was held at the Ramada Plaza Jeju Hotel, in Jeju, Korea, on November 14-16, 2011. The A-SSCC is one of the four conferences fully sponsored by the IEEE Solid-State Circuits Society, and this was its seventh appearance since its inauguration in 2005 in Taiwan. Following the past six successful A-SSCCs, this conference has been recognized as a prestigious technical event in the IC design field. The theme of the 2011 A-SSCC was "Integrated Circuits for Sustainable Future." Motivated by pursuing a quality life, intelligent electronics designed to enable healthy living and sustainable environment are playing increasingly important roles. This conference theme is a testimony of our - the IC design communities' - efforts in making the world a better place to be. The conference received 270 manuscript submissions from 25 countries, ofwhich 98 paperswere accepted after rigorous review process. After the conference, the technical program committee selected 15 outstanding papers for this JSSC Special Section. These papers contain full-length materials which describe the presented works in more detail than they were in the conference proceedings. These 15 papers include 6 analog and data converter papers, 6 wireline and wireless/RF papers, and 3 digital and SoC papers. [ABSTRACT FROM PUBLISHER]

This paper provides an electrical equivalent circuit of a high-resistance grounded (HRG) power supply transformer to discuss damage at a fault location so long as the fault remains a line–ground fault. Fault resistance and fault current that have an effect on damage are included in the equivalent circuit. Three-line diagrams showing fault current flows along with their vector diagrams are also included. Part II of this paper provides a similar equivalent circuit for an HRG grounded generator. This paper provides guidance to update the current edition of IEEE STD. 142 with respect to HRG systems. [ABSTRACT FROM AUTHOR]

This paper presents an empirically grounded model, which links organizational learning to pattern-specific fixed costs in integrated device manufacturing. The approach described in this paper helps fab managers make fundamental strategic decisions concerning product design and product mix by engaging in scenario planning. Four critical aspects of managing pattern-specific fixed cost are analyzed in detail—sensitivity to time, design cost, and production volume; platform designs; process postponement solutions; and design penalties. The model suggests that designers and fabrication facilities must collaborate extensively on the design and realizations of product platforms for state-of-the-art integrated circuit products to remain economically viable. [ABSTRACT FROM AUTHOR]

Obtaining physiological data from animals in a non-obtrusive and continuous manner is important to veterinary science. This paper demonstrates the design and deployment of a miniaturized capsule-based system for subdermal injection to provide real-time and continuous heart-rate, movement, and core-body-temperature measurements. The presented device incorporates sensors for photoplethysmography, motion detection, and temperature measurements. A bluetooth-low-energy enabled microcontroller configures the sensors, digitizes the sensor information, and wirelessly connects with external devices. The device is powered by a CR425 battery for this paper, and various other battery solutions are available based upon the use case. The design uses only commercially available integrated circuits in order to reduce the development cost and be modular. The encapsulation is a combination of medical epoxy and poly(methyl methacrylate) that fits within a 6-gauge hypodermic needle. The preliminary evaluation of the device included an in vitro assessment of its thermal response and measurement accuracy, the impact of one-month implantation on surrounding tissue, the power consumption with duty cycling of various sensors, and a measurement of physiological signals in a rat and a chicken. Having a form factor and implantation method similar to existing devices for animals, this novel system is a useful platform for both scientists and veterinarians to better study a diverse range of animals. [ABSTRACT FROM AUTHOR]

In this paper, a novel filtering antenna based on periodic spoof surface plasmon polaritons (SSPPs) is proposed. Double-sided parallel-strip line (DSPSL) is used to realize the wideband property for the double-layer SSPPs. Filtering performance can be realized by adding via holes and ring resonators in the double-layer SSPPs. The simulated and measured results indicate the high gain of 9.38 dBi and bandwidth of 10.44% can be achieved for the antenna with via holes and ring resonators, the out-of-band rejection is over 17 dBi. Meanwhile, the gain variations are less than 1 dBi in the whole frequency band. Good agreements can be observed between the measured and simulated results, which indicate good potential applications in the communication systems and integrated circuits. [ABSTRACT FROM AUTHOR]

This paper presents two main contributions toward efficient very large scale integration circuits mapped with simple cells: 1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and 2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. An effective pattern-based algorithm to identify XORs/XNORs on and-inverter graphs is also presented. We show that efficient implementations in terms of inverter count, transistor count, area, power, and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while: 1) optimizing the number of added inverters and 2) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation, and delay up to 48%, 4%, 8%, 14%, and 16%, respectively. [ABSTRACT FROM AUTHOR]

This paper addresses the estimation and compensation of I/Q imbalance, one of the most prominent impairments found in wideband zero-intermediate frequency transceivers (TRxs). The I/Q imbalance encountered in this kind of TRx comprises not only frequency-selective gain and phase imbalance but also delay imbalance. Unless appropriate compensation is applied, the I/Q imbalance significantly degrades the performance of a communication system. This paper presents a novel compensation technique for transmitter I/Q imbalance based on built-in-self-calibration, a low cost and robust compensation technique that enables manufacturing as well as in-field calibration with low computational complexity. The method’s performance is evaluated in a TRx with 64-quadratic-amplitude modulation and 2 GHz of bandwidth implemented with real hardware. The measurements show that the proposed technique achieves an image rejection ratio greater than 35 dB in the entire 2 GHz bandwidth and an error vector magnitude lower than 3%. [ABSTRACT FROM PUBLISHER]

Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum transistor count. This paper presents two novel methods aiming the minimization of the number of devices in logic networks. The first contribution is a method for defactoring Boolean expressions able to apply the conventional factorization algorithms together with IG FinFET particularities, so improving it. The second contribution is a novel graph-based method that improves even more transistor arrangements by exploiting enhanced nonseries-parallel associations. Experimental results shown a significant reduction in the size of transistor networks delivered by the proposed methods. [ABSTRACT FROM AUTHOR]