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A dual-heterojunction-trench (DHT) diode is proposed as having an improved electrical performance compared with dual-metal-trench (DMT) diodes. This paper is based on simulations performed using the Silvaco TCAD tool. The DHT diode not only improves the compromise between forward current and breakdown voltage but also has a better I–V characteristic compared with DMT diodes. The P-polysilicon region concentration was found to have only a minor effect but the mesa width, P+ polysilicon region concentration and drift region concentration have a great influence on the I–V characteristics of the proposed device. The effect of the interface charge and the forward and reverse characteristics of the proposed device at room and high temperatures were also simulated. [ABSTRACT FROM PUBLISHER]

Silicon carbide (SiC) vertical-diffused metal oxide field transistor (VDMOSFET) is an important power device for aerospace application. However, it is sensitive to heavy particles radiation in space which can cause catastrophic single-event effects (SEEs). In this article, a method of SEE hardening at a high linear energy transfer (LET) value range is studied to the 1.2 kV-rated SiC VDMOSFET by the 2-D numerical simulator SILVACO TCAD. Simulation results illustrate that, compared with the VDMOSFET which only has four buffer (FB-VDMOSFET) layers, the improved MOSFET could increase the abilities of single-event burnout (SEB) and the single-event gate rupture (SEGR) of the device effectively. At the same time, the proposed MOSFET has the lower specific ON-resistance (${R}_{\text {on, sp}}$) at room temperature. As a result, the gate oxide of the FB-VDMOSFET has reached 7.5 MV/cm and the maximum temperature reached 2480 K at a voltage of 600 V and an LET value of 0.5 pC/ $\mu \text{m}$. However, the maximum temperature of the improved VDMOSFET is 2150 K when ${V}_{\mathrm {DS}}$ = 950 V. [ABSTRACT FROM AUTHOR]

This paper presents 2-D numerical simulation results of single-event burnout (SEB) in power planar vertical double-diffused MOSFET (VDMOSFET) with localized carrier lifetime control. A low carrier lifetime control region (LCLCR) is introduced to accelerate the recombination rate of the generated holes caused by an ion’s impact. The optimal localized range with LCLCR in epitaxial layer has been investigated. The SEB inhibition mechanism with LCLCR is analyzed and discussed. A VDMOSFET with localized LCLCR can operate like a normal VDMOSFET and can have improved SEB performance effectively. In addition, the leakage current density in breakdown characteristics of VDMOSFET is studied based on the variation of carrier lifetime. [ABSTRACT FROM PUBLISHER]

In this work, the single-event burnout (SEB) and degradation behaviors induced by heavy-ion irradiation were investigated in an 80-V-rated SEB-hardened split-gate trench (SGT) power U-shaped metal-oxide-semiconductor field-effect transistor (UMOSFET). After SEB hardening, the SEB failure threshold voltage of the sample device was measured to be 90 V; furthermore, a permanent degradation of the drain leakage or gate leakage was found after irradiation when the reverse voltage exceeded 60 V. The simulation results demonstrate that the heavy-ion-induced transient high temperature is a common mechanism responsible for the severe degradation and the catastrophic SEB. In addition, an effective method to improve the degradation and SEB tolerances, which enhances the rated breakdown voltage of a device, was proven through simulations. [ABSTRACT FROM AUTHOR]

This article proposes an RC-IGBT structure with N-Si/n-Ge heterojunction (NNH-IGBT) to suppress snapback effect. Because the proposed N-Si/n-Ge heterojunction acts as a gradually reverse bias diode to suppress the electron flow into the N-short region, so the snapback effect can be suppressed. For the same ${\mathrm{\scriptstyle {ON}}}$ -state voltage drop (${V}_{\text {CE}}$), the turn-off loss (${E}_{\mathrm{\scriptstyle {OFF}}}$) of the NNH-IGBT is lower than the conventional RC-IGBT (Con-RC-IGBT). In addition, the reverse recovery speed of NNH-IGBT is nearly identical to the Con-RC-IGBT. Because of the use of heterojunction, the NNH-IGBT is suitable for operate to suppress the snapback effect, especially at low temperatures. [ABSTRACT FROM AUTHOR]

In this article, we investigate a new hardened GaN MISFET with an integrated Schottky contact (SC-MISFET). The new device architecture significantly improves the single-event burnout (SEB) characteristics. Compared to the field plate conventional GaN MISFET (FPC-MISFET), the Schottky metal can extract a larger number of holes, which are generated by heavy-ion irradiation. In addition, the number of carriers involved in the impact ionization process is substantially reduced. These features enable the new hardened structure to achieve a better overall SEB characteristic. After heavy-ion irradiation, the SEB threshold voltages of devices with conventional and hardened structures are 520 and 710 V, respectively. [ABSTRACT FROM AUTHOR]

In this article, a method of single-event burnout (SEB) hardening at high linear energy transfer (LET) value range is proposed and investigated by the 2-D numerical simulations. The improved MOSFET using this method and the conventional MOSFET are analyzed and compared to evaluate the effectiveness of this method. Simulation results show that, compared with the conventional MOSFET, the improved MOSFET using this method can effectively and quickly reduce the internal high electric field, thereby reducing the temperature. Under the condition of a LET value of 0.5 pC/μm and a drain voltage of 1200 V, the maximum drain current is 0.168 A, and the maximum global device temperature is 1724 K, which is much lower than the melting down temperature of silicon carbide (SiC) (3100 K). The hardening method in this article can be applied to different breakdown voltages by adjusting structure parameters. [ABSTRACT FROM AUTHOR]

In this article, we investigate a novel optimized 4H-SiC U-shaped trench-gate MOSFET (UMOSFET) structure, which features an electric field modulation region below the P-body. This region consists of a p-type region and an n-type region, while the p-type region is wrapped by the n-type region. We use the p-type region to reduce the electric field at the P+ shielding layer and the gate oxide. The reduced electric field increases the breakdown voltage (BV) of the optimized UMOSFET substantially. The n-type region can also improve the ON-state characteristics of the UMOSFET. Under the combined action of the p-type region and the n-type region, the BV and figure of merit increased by 25.2% and 120.5%, respectively. Moreover, the specific ON-resistance dropped by 40.8%. [ABSTRACT FROM AUTHOR]

In this article, a novel snapback-free reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with P+ pillars at the collector side (PPC) is proposed and investigated by TCAD simulations. This structure features the P+ pillar structure at the side of collector and exits a gap of N-buffers above N+ collector. The P+ pillars increase the distributed resistance below the buffer layer during turn-on transient, show bipolar mode, and eliminate the snapback phenomenon. Accordingly, the structure eliminates the snapback phenomenon with a smaller half-cell pitch of 10~μm, making that the device is more reliable and suitable for parallel connection. For the same forward voltage drop, the turn-off loss of the PPC structure is reduced by 34%. [ABSTRACT FROM AUTHOR]

In this article, the performance and triggering mechanism of the single-event burnout (SEB) of a 4H-SiC trench-gate (TG) MOSFET structure are evaluated by the 2-D numerical simulations. The novel N+ island buffer 4H-SiC TG MOSFET and the conventional TG 4H-SiC MOSFET are analyzed and compared to examine whether an N+ island region introduced in the second buffer can effectively reduce the impact ionization located at the N− drift/N+ buffer junction and improve device tolerance to the SEB. The TCAD simulation results revealed that compared with the conventional structure, which is a simple double-buffer structure, the N+ island buffer-hardened structure changed the burnout threshold voltage, improving the SEB performance significantly. In addition, the results proved that the impact ionization played an important role in the SEB triggering mechanism, significantly affecting the SEB performance of the 4H-SiC TG MOSFET. The performance of the hardened N+ island buffer with a different dopant concentration of N-buffer 2 and a size of N+ island is discussed. The specific burnout threshold voltage at the optimal parameters of the proposed structure is 47% higher than that of the conventional structure. [ABSTRACT FROM AUTHOR]

This brief first time presents single-event burnout (SEB) simulation results for conventional AlGaN/ GaN gate field plate MISFET (GFP-C MISFET), simultaneously, a hardened MISFET with electrode connected doped plugs in the buffer (EC-DP MISFET) is proposed for the first time. The SEB triggering mechanisms contain the back-channel effect and following impact ionization dominated by electron in the high field region. By comparing the simulation results from the GFP-C MISFET and proposed hardened EC-DP MISFET, the carriers induced by heavy ion can be quickly absorbed to drain and source electrode through EC-DP, so that the proposed EC-DP MISFET can achieve better SEB performance than conventional one. With a heavy ion having the linear energy transfer value of 0.6-pC/ $\mu \text{m}$ striking vertically, SEB threshold voltage obtained in GFP-C MISFET and hardened EC-DP MISFET is 280 and 338 V, respectively. [ABSTRACT FROM AUTHOR]

A fully depleted silicon-on-insulator (SOI) pixel detector with multijunction structure in p-type substrate is proposed to reduce the diode capacitance and improve the effective shielding between the SOI circuits and sensor. A buried p-well (BPW) and a buried n-well (BNW) are applied to their respective bias voltages to shield SOI circuits from the sensor in the substrate. BPW is biased to counteract the back-gate effect. A deeply BPW is employed to form a potential barrier to electrons in BNW, stopping the front-to-back leakage current. Lateral electric field is also formed to accelerate holes to the p+ charge collector. The simulation results demonstrate that the pixel can achieve its objectives under a full depletion condition. The capacitance of the charge collector can be reduced, which depends primarily on the charge-collector/BNW junction. [ABSTRACT FROM AUTHOR]

This paper presents the 2-D numerical simulation results of single-event burnout (SEB) in 4H-SiC junction barrier Schottky (JBS) diode by low carrier lifetime control (LCLC) for the first time. We investigate the SEB performance based on an 1800-V JBS structure and find that the most sensitive ion’s strike position is the middle of junction spacing because of the punchthrough of the electric field at anode contact. Then, the SEB hardening mechanism of LCLC is studied in this paper that the double-sided peak electric field can be effectively improved which results in a significantly decrease of maximal temperature. For the incident particle with different linear energy transfer values, we find that the SEB threshold voltage can be substantially enhanced when the carrier lifetime ($\tau $) is under a certain value. In addition, the basic characteristics with LCLC are discussed that the forward and reversed characteristics are hardly affected. [ABSTRACT FROM AUTHOR]

This paper introduces the anode-via vertical field plate Schottky barrier diode (AVFP-SBD) structure as an enhanced breakdown voltage AlGaN/GaN SBD, using the 2-D ATLAS Silvaco software. The breakdown voltage enhancement is achieved by integration of the lateral field plate (LFP) and vertical field plate (VFP) into the AlGaN/GaN SBD. The simulation results indicate that the VFP not only provide a uniform electric field along the channel, but also distributes the internal electric field on the side of the anode evenly. We show that the proposed structure significantly enhances the breakdown voltage of the conventional AlGaN/GaN diodes, i.e., from −246 to −354 V. Moreover, optimal breakdown voltage of −2301 V is achieved using the SBD with anode-via both LFP and VFP, through an integration of the LFP into the AVFP-SBD. Such breakdown voltage enhancement is achieved without any deterioration in the forward characteristics of the diode. [ABSTRACT FROM AUTHOR]

In this paper, we propose an enhanced efficiency 4H-SiC U-shaped trench-gate MOSFET (UMOSFET) structure. The proposed device structure takes an advantage of a p+-polySi/SiC shielded region to reduce the on-state specific resistance. We show that the heterojunction diode formed by the p+-polySi and the n-drift regions improves the body diode effect, and thereby, reduces the reverse recovery charge. Further, we illustrate through simulation results that in comparison with the traditional p+-SiC shielded UMOSFET, the proposed device structure provides a 56.5% improvement in the figure of merit (including the breakdown voltage and on-resistance), and a 35.7% and 55.5% reduction in specific on-resistance and reverse recovery charge, respectively. [ABSTRACT FROM PUBLISHER]

In this paper, a multiple trench split-gate silicon-on-insulator (SOI) lateral double-diffused MOSFET with a Schottky rectifier (MTS-SG-LDMOS) is proposed and its characteristics are studied using 2-D simulations. The new structure features double oxide trenches, a floating polysilicon split-gate, and a Schottky rectifier. Each oxide trench includes a vertical field plate which enhances the depletion of the drift region and modulates the bulk electric field. As the simulation results, when compared to the conventional SOI LDMOS (C-LDMOS), the breakdown voltage in the MTS-SG-LDMOS increases from 297 to 350 V, the specific on-state resistance ( R \mathrm{\scriptscriptstyle ON,\mathsf {sp}} ) decreases from 142.9 to 48.2 \textm\Omega \cdot \mathsf cm^\mathsf 2 , and the gate–drain charge ( Q {\mathsf {gd}} ) decreases from 19 to 9 pC. Moreover, the reverse recovery time of the proposed structure shows a 73.6% reduction as compared to the C-LDMOS device. [ABSTRACT FROM AUTHOR]

This paper presents an optimized split-gate-enhanced trench MOSFET with dual channels (DSGE-UMOS). The 2-D device simulator ATLAS is used to investigate the characteristics of the proposed structure. When compared with the conventional SGE-UMOS, the optimized device shows a significant reduction in the specific on-resistance ( R {\mathrm{\scriptscriptstyle ON}\text {-sp}} ) at a breakdown voltage of 120 V, which is due to the adoption of an additional p-type well region. Furthermore, the proposed structure can also enhance the single-event burnout (SEB) survivability. Based on the DSGE-UMOS, the hardened DSGE-UMOS (an n-type buffer layer is added between the epitaxial layer and substrate layer) is also investigated that the addition of the buffer layer can improve the SEB performance a lot. [ABSTRACT FROM AUTHOR]

In this paper, an n-p-n collector incorporated in the back side of a 4H-SiC trench IGBT is presented to reduce the turn-off energy loss. A comparative study between the proposed structure and the conventional structure is conducted through ATLAS. The simulation results have demonstrated that the turn-off energy loss is reduced by more than 82.96% with a slight degradation in the on-state voltage drop. [ABSTRACT FROM PUBLISHER]

This paper presents 2-D numerical simulation results of single-event burnout (SEB) in power trench accumulation mode field effect transistor (ACCUFET) for the first time. In this device, a p+ base region is used to deplete the n− base region to achieve a low leakage current density, and the blocking voltage is supported by the n− drift region. We find that the depth of the p+ base region determines both the leakage current density and SEB performance, as a result, there is a tradeoff relationship between the two characteristics. The 60 V hardened power ACCUFET shown in this paper could demonstrate much better SEB performance without sacrificing the current handling capability compared with the standard UMOSFET. The hardened structure mentioned in this paper indicates that an n buffer layer is added between the epitaxial layer and substrate layer based on a basic power device. As a result, the safe operating area (SOA) of the 60 V, 80 V and 100 V hardened ACCUFET discussed in this paper could reach the value of breakdown voltage when the buffer layer is over a certain value, that can realize safety operation throughout entire LET range. [ABSTRACT FROM PUBLISHER]

Junction barrier Schottky (JBS) rectifiers with p-well on 4H-SiC for improving the electrical performance are proposed. Compared with the common JBS rectifier, the devices show an increasing breakdown voltage due to a uniform electric field. Forward and reverse characteristics have been verified at room and elevated temperatures. As a result, the breakdown voltage of 1.9 kV was obtained for the JBS rectifier with the \P^+ grids on the p-well (POP), and that of the JBS rectifier with the \P^+ grids in the p-well (PIP) is about 1.6 kV. The forward voltage drops of the POP and PIP JBS rectifiers at a current density of 100 \A/cm^2 are 3 and 3.2 V, respectively. The POP and PIP JBS rectifiers have more than \3.3 \times \10^10 and \5.4 \times \10^10 on/off (1 V/ -500 V) current ratios, respectively. In addition, the output capacitance of the POP JBS rectifier at -3 V reduces about 15% relative to that of the common JBS rectifier. In addition, the figures of merit of the POP and PIP JBS rectifiers are about 4.1 times and 2.9 times that of the common JBS rectifier, respectively. [ABSTRACT FROM PUBLISHER]

Presents information on a study which discussed the time- and frequency-domain analysis of the extraction of epiphyseal/metaphyseal regions of interest. Classification issues leading to bone age assessment; Stages of image analysis; Results and discussion; Conclusions.