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Your search keyword '"Zou, Xuecheng"' showing total 438 results
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438 results on '"Zou, Xuecheng"'

1. Nanoscale three-dimensional magnetic sensing with a probabilistic nanomagnet driven by spin-orbit torque

Author

Zhang, Shuai, Li, Shihao, Guo, Zhe, Xu, Yan, Li, Ruofan, Chen, Zhenjiang, Min, Song, Yang, Xiaofei, Li, Liang, Hong, Jeongmin, Zou, Xuecheng, and You, Long

Subjects
Condensed Matter - Materials Science
Abstract

Detection of vector magnetic fields at nanoscale dimensions is critical in applications ranging from basic material science, to medical diagnostic. Meanwhile, an all-electric operation is of great significance for achieving a simple and compact sensing system. Here, we propose and experimentally demonstrate a simple approach to sensing a vector magnetic field at nanoscale dimensions, by monitoring a probabilistic nanomagnet's transition probability from a metastable state, excited by a driving current due to SOT, to a settled state. We achieve sensitivities for Hx, Hy, and Hz of 1.02%/Oe, 1.09%/Oe and 3.43%/Oe, respectively, with a 200 x 200 nm^2 nanomagnet. The minimum detectable field is dependent on the driving pulse events N, and is expected to be as low as 1 uT if N = 3 x 10^6., Comment: 15 pages, 4 figures

Published
2022

16. A 3.83–5.55 GHz high frequency resolution DCO with optimized switched‐capacitor ladder and low‐coupled eight‐shaped transformer.

Author

Zou, Wei, Li, Lei, Cheng, Zhengwang, Zhang, Li, Wang, Mei, Ma, Xinguo, and Zou, Xuecheng

Subjects
PHASE noise, ON-chip transformers, VOLTAGE-controlled oscillators, COMPLEMENTARY metal oxide semiconductors, ELECTROMAGNETIC coupling, SUPERCONDUCTING coils
Abstract

Summary: A high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched‐capacitor (SC) ladder and a low‐coupled eight‐shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on‐chip transformer, thus reducing quantization noise and phase noise. An eight‐shaped transformer designed using two coils cross‐connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180‐nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is −120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is −191 dBc/Hz. The chip size is 0.294 mm2. [ABSTRACT FROM AUTHOR]

Published
2023
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19. The Evolution Characteristics of Soil Heat Storage of the Sidewalls in Subway Stations with Years

Author

Zeng Xianming, Wang Lihui, Zou Xuecheng, Yin Liyuan, and Cheng Jian

Subjects
Environmental sciences, GE1-350
Abstract

The long-term evolution characteristics of the heat reservoir of soil have been analyzed by 15 years of simulation test with periodic indoor and outdoor air temperature conditions. A scale model test of the soil in the subway station sidewalls and software ANSYS fluid-structure coupling heat transfer model are built in this study, which are complementary and mutual authentication. In 1∼15 years, the results show that the maximal temperature rise of soil at 2 m buried depth is 3.9 °C, at 7 m buried depth is 1.6 °C, and at 12 m buried depth is 1.5 °C. On the sidewalls surface the average maximal endothermic heat flow density is 6.8 W/m2 in summer, and the average maximum exothermic heat flow density is 11.3 W/m2 in winter. It provides theoretical reference for the reasonable use of heat storage of the soil in the sidewalls of subway stations.

Published
2022
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33. In‐Memory Mathematical Operations with Spin‐Orbit Torque Devices

Author

Li, Ruofan, primary, Song, Min, additional, Guo, Zhe, additional, Li, Shihao, additional, Duan, Wei, additional, Zhang, Shuai, additional, Tian, Yufeng, additional, Chen, Zhenjiang, additional, Bao, Yi, additional, Cui, Jinsong, additional, Xu, Yan, additional, Wang, Yaoyuan, additional, Tong, Wei, additional, Yuan, Zhe, additional, Cui, Yan, additional, Xi, Li, additional, Feng, Dan, additional, Yang, Xiaofei, additional, Zou, Xuecheng, additional, Hong, Jeongmin, additional, and You, Long, additional

Published
2022
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34. A Methodology for Design of Unbuffered Router Microarchitecture for S-Mesh NoC

Author

Liu, Hao, Cao, Feifei, Liu, Dongsheng, Zou, Xuecheng, Zhang, Zhigang, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Ding, Chen, editor, Shao, Zhiyuan, editor, and Zheng, Ran, editor

Published
2010
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35. A High Efficient On-Chip Interconnection Network in SIMD CMPs

Author

Wu, Dan, Dai, Kui, Zou, Xuecheng, Rao, Jinli, Chen, Pan, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Hsu, Ching-Hsien, editor, Yang, Laurence T., editor, Park, Jong Hyuk, editor, and Yeo, Sang-Soo, editor

Published
2010
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44. Harmonic Weighting and Target Function Design Strategy to Minimize Switch Voltage Stress of Class Φ 2 Inverter.

Author

Zhang, Desheng, Lu, Liangliang, Tong, Qiaoling, Zhang, Qiao, Min, Run, Peng, Han, and Zou, Xuecheng

Subjects
VOLTAGE, IDEAL sources (Electric circuits), HARMONIC distortion (Physics), ELECTROSTATIC induction
Abstract

For very high frequency (VHF) class Φ2 inverter, conventional design method requires complex tuning for parameters. Without fully quantitative calculations, the tuning highly depends on experience that cannot achieve optimal design. In this article, a target function design strategy is proposed based on quantitative harmonic weighting, which simplifies the design procedures and minimizes the switch voltage stress. First, the target switch voltage with minimized peak value is derived by optimizing the harmonic weighting. With the result, the power switch is modeled as a voltage source to simplify the calculations, where the branch currents are solved to provided fully quantitative analysis. Based on the analysis, optimal features of switching node impedance are derived to achieve the target switch voltage. In addition, basic constrains of the resonant tank are analyzed to reduce circling currents. Combining the optimal features and basic constrains of the resonant tank, the circuit parameters are calculated directly, which minimizes the switch voltage stress and improves power efficiency. Compared with conventional design, a 27.12 MHz prototype demonstrates 10.2% reduction in average switch voltage stress and 7.2% improvement in average efficiency. [ABSTRACT FROM AUTHOR]

Published
2022
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48. ML-Accelerated Yield Analysis Framework Using Regularization for Sparsity in High-Sigma and High-Dimensional Scenarios

Author

Xu, Haoran, Fan, Haoran, Jiang, Bo, Chen, Jianfei, Tong, Qiaoling, and Zou, Xuecheng

Abstract

Highly repetitive structures in IC, such as SRAM cells typically require extremely low failure ratio, making traditional Monte Carlo analysis extremely time consuming. Furthermore, the “curse of dimensionality” has become a major challenge for existing high-sigma yield analysis techniques. Thus, we propose a “sampling-training-substitution-verification” (STSV) yield analysis framework, which utilizes machine learning (ML) techniques to accelerate yield analysis in high-sigma and high-dimensional scenarios, effectively addresses the “curse of dimensionality.” In our framework, least absolute shrinkage and selection operator (Lasso) regression is adopted to substitute the mapping from process parameters to circuit performance, achieving high accuracy, and generalization. The model is adaptive for both low- and high-dimensional scenarios since the dimensional sparsity is achieved by $l1$ regularization. In addition, important process parameters can be identified by sparse feature weights of the Lasso model, which is of assistance for yield optimization. Compared with existing yield analysis techniques, the Lasso-based STSV framework offers great saving in a simulation program with integrated circuit emphasis (SPICE) cost, is attractive in high-dimensional demands.

Published
2023
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