Search

A silicon/silicon carbide (Si/SiC) hybrid switch (HyS), comprised of a high-current Si insulated gate bipolar transistor and a low-current SiC metal oxide semiconductor field effect transistors, gains attention because it offers lower on-state loss under both light and heavy loads. However, the dynamic overcurrent stress experienced by the HyS under the heavy load has to be coped with to avoid reliability degradation and the maximum current rating limitation. This article comprehensively studies how gate resistances regulate the dynamic behavior of the HyS under the heavy load condition. Experiments and analyses are conducted for both turn-on and turn-off processes. It is found that the gate resistance is important for not only the dv/dt control but also the overcurrent suppression. Moreover, the lower switching loss can be achieved by adjusting gate resistances when the HyS operates at a heavy load, compared with the gate timing control. A guideline is developed for the design of the gate resistances. This study offers an insight into the role of gate resistances in switching performances of the HyS and an alternative way of coping with the dynamic overstress stress. [ABSTRACT FROM AUTHOR]

For silicon carbide power mosfets, high dv/dt in switching may bring about a high level of electromagnetic interference. This letter shows that the dv/dt rate decreases at lower load currents. A dynamic dv/dt control strategy is then proposed for switching loss reduction in the whole operating range, by maintaining the dv/dt at the maximum acceptable level. The effectiveness of the proposed control strategy is verified by an experiment, showing that the total switching loss can be reduced by as much as 22% at 30% load. Furthermore, the simulation shows that a power loss reduction of 11.4% can be obtained for an electric vehicle converter which typically operates at light loads for most of the time. [ABSTRACT FROM AUTHOR]

As the silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistor (MOSFET) develops, increasing efforts are placed on ac bias temperature instability (AC BTI). It was reported that AC BTI becomes significant when and only when the gate stress is bipolar. A detailed study is made in this article to reveal the underpinning mechanism. A physical model is proposed to explain on how and why the gate stress bipolar affects the threshold drift. It is found that the gate stress polarity has to be carefully defined. As the model shows, it is the bipolar electric field, rather than the gate voltage itself, that speeds up the threshold voltage drift. It is hoped that this study provides a stepping stone toward the eventual understanding and management of AC BTI. [ABSTRACT FROM AUTHOR]

With increasing applications of silicon carbide power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability of the gate threshold voltage is of paramount importance. In this article, laboratory experiments are conducted to investigate the threshold voltage instability under ac gate stresses with different duty ratios, and on and off-state gate voltages. It is found that no prominent drift would occur even for bipolar gate stresses, as long as the off-state gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process. Furthermore, not only the gate voltage swing but also the gate voltage polarity will affect the speed of threshold voltage drift when it occurs. The findings are intended for better understanding and management of potential threshold voltage drift in device applications. [ABSTRACT FROM AUTHOR]

A comparative study on SiC MOSFETs is carried out with an emphasis on the design of integrated Schottky barrier diode (SBD) with numerical simulations by Sentaurus TCAD. Compared with the conventional SiC MOSFET (C-MOS) and the conventional SBD-embedded SiC MOSFET (C-MOSBD), the MOSFET (M-MOSBD) features a hybrid doping mesa above the JFET region where a Schottky contact is formed, which exhibits a superior trade-off between the on-state resistance (R dson) and the reverse transfer capacitance (C rss). Besides, the integrated diode in M-MOSBD renders a better trade-off between OFF-state junction field (E Smax) and forward voltage (V F) when compared to C-MOSBD and the conventional junction barrier Schottky diode (JBS), i.e., the external SBD of C-MOS. In the double pulse test simulation, C-MOS exhibited the largest switch loss followed by C-MOSBD, and M-MOSBD is the smallest. Therefore, in power switching applications where reverse conduction is required, M-MOSBD greatly reduces the chip area while presenting better characteristics. [ABSTRACT FROM AUTHOR]

A GaN/SiC hybrid field-effect transistor (HyFET) is proposed as a high-voltage power device that provides a high-mobility lateral AlGaN/GaN channel to reduce the channel resistance and a vertical SiC drift region to sustain the high OFF-state voltage. The performance of the HyFET is evaluated by numerical device simulations. Compared with the conventional SiC MOSFET, the HyFET exhibits a greatly reduced R\mathrm{\scriptscriptstyle ON} together with a low C\mathrm{ GD} and low gate charges. The figures of merit Q\mathrm{ G}\times R\mathrm{\scriptscriptstyle ON} and Q\mathrm{ GD}\times R\mathrm{\scriptscriptstyle ON} of the HyFET are dramatically improved. [ABSTRACT FROM AUTHOR]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

Parallel devices in nonuniform conditions can easily lead to reduced overall reliability or even failure due to uneven energy distribution. Especially under long-term avalanche stresses, the degradation of the device may have a great impact on the electrical parameters and performance. To study the degradation tendency and aging mechanism of parallel-connected silicon carbide (SiC) MOSFET, the repetitive unclamped inductive switching (UIS) experiments are carried out in this article. Technology computer-aided design (TCAD) simulations are utilized to simulate the temperature change and current distribution of the chip during an avalanche. The results showed that for planar and trench devices, the electrical parameters drifts are different during repetitive avalanches. The degradation rates are unequal for parallel devices with different case temperatures. Two degradation mechanisms, including hot holes injection and trapping in the gate oxide and metal aging, are found to dominate in the repetitive avalanche process. The findings are helpful for better understanding of degradations for parallel repetitive avalanches in device applications. [ABSTRACT FROM AUTHOR]

A 4H‐SiC trench metal–oxide–semiconductor field‐effect‐transistor (MOSFET) design with an integrated merged PiN Schottky (MPS) diode is proposed. The Schottky contact is embedded on the bottom of the trench structure for the first time. The low electric field in the oxide and Schottky contact surface can be achieved simultaneously using the proposed integration design which enhances the oxide reliability and reduces leakage from the Schottky diode. The integration of the MPS diode reduces the total chip area and the required number of dies compared with the conventional method of using an external Schottky diode. [ABSTRACT FROM AUTHOR]