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Magnetic circuit components have long been the largest and most difficult components to miniaturize. Printed circuit board (PCB) fabrication methods cannot achieve small diameter, high aspect-ratio vias for high winding turn numbers to achieve high inductance, and microelectronics methods cannot achieve the high-quality and thick ferrite core materials. In this paper, we present an alternative breakthrough method of printed circuit fabrication to significantly reduce the effective via diameter for embedded magnetic devices, boosting the inductance per unit area. To reduce the effective via diameter, high-density via plugs are ex-situ fabricated and shaped, and then embedded into PCB substrate in the same process as standard magnetic core embedding. The structure of the plug is such that precise placement within the substrate, or alignment to the plug with the winding pattern, is not necessary. Devices presented in this paper use via plugs with an effective diameter of 40 μm and a theoretically unlimited aspect ratio, though refinements in the plug fabrication process are expected to reduce the via diameter down to 10μm. The process is experimentally demonstrated with a 14-turn racetrack shaped transformer; novel diagnostic methods using magneto-optic garnet films to image current paths are also demonstrated.

This brief proposes a low voltage ultra-low power 10-bit 100-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To overcome the performance degradation due to the signal-related current fluctuation under lower supply voltage, an adaptive-biasing comparator with current self-compensation (CSC) technique is proposed to obtain a constant working current, reducing the minimum supply voltage from 0.7V in conventional ADCs to 0.55V. Since full-scale range shrinks with the supply voltage, voltage undershoot in power rail caused by capacitor digital-to-analog converter (C-DAC) deteriorates effective-number-of-bits (ENOB). Conventional solutions involve enhanced regulators and large decoupling capacitors, which cost remarkable power dissipation and large chip area. This brief presents a pulse-injection undershoot compensation technique which reduces the DAC-related supply fluctuation from a typical 15mV to 1.8mV, and improves the ENOB by 0.4 bit. The prototype was fabricated in TSMC 28nm HPC CMOS technology. The proposed SAR ADC achieves an SNDR of 54.7dB and an SFDR of 68dB with the power consumption of 0.16mW under 0.55V supply voltage, a figure of merit (FoM) of 3.6-fJ/conversion-step is achieved. The chip area of the ADC core is 130μm×225μm.

The present day ever escalating power demand moves the operating point ofthe distribution networks in the vicinity of the voltage stability boundaries.Any small reactive power unbalance between the generation and demandmay trigger voltage instability, which makes the voltage magnitude to fallslowly until a rapid change occurs. This paper presents an adaptive dragonflyoptimization based method for placement of shunt capacitor banks witha view of improving the voltage stability besides enhancing the voltageprofile and lowering the network losses. Simulation results on 33 and 69-node distribution networks exhibit the greater performances of the suggestedalgorithm.

A new dc-dc converter with high voltage gain is proposed in this study. The proposed converter consists of two switches which are turned on and off simultaneously. Additionally, two Switched-Capacitor (SC) cells and one Energy Storage (ES) cell are utilized in the structure of the proposed converter. These result in high voltage gains at low values of the duty cycle. Besides, the voltage stress across the power devices is low and below half of the output voltage. Therefore, the MOSFET switches with low RDS-on and devices with reduced nominal voltage can be used in the proposed converter which in turn reduces the conduction and turn-on losses. The analysis of the voltage and current stresses of the devices is accomplished. The circuit performance is compared with other solutions in the literature in terms of voltage gain and normalized voltage stress of switches and diodes. Eventually, in order to verify the theoretical analysis, the experimental results are provided.

In the hardware design of battery energy storage system (BESS) interface, in order to meet the high-voltage requirement of grid side, integrating 10-kV silicon-carbide (SiC) MOSFET into the interface could simplify the topology by reducing the component count. However, the conventional gate driver design is challenging and inextensible in BESS, since the high-voltage rating and high dv/dt bring the requirements of high-voltage isolation and low common-mode capacitance. Therefore, in this article, a scalable converter-based self-powered (SCS) gate driver is further proposed. A 5-kV input power extracting converter based on a voltage-balanced SiC MOSFET stack is constructed to self-power the gate driver, which exhibits simplification of basic topology and sufficient gate driver power handling capability regardless of the switching requirement of main loop power device. Besides this, the power extracting converter is designed to act as a clamping resistor-capacitor-diode (RCD) snubber circuit, which makes the SCS gate driver scalable to the series connection of power devices. Analysis and design consideration are given in detail, followed by the experimental verification using 10-kV/10-A SiC MOSFETs.

Wide voltage design has been widely used to achieve power reduction and energy efficiency improvement. The consequent increasing number of PVT corners poses severe challenges to timing analysis in terms of accuracy and efficiency, especially for low voltage corners. In this paper, a learning-based timing prediction framework is proposed to predict multi-corner path delays across wide voltage range by exploiting both the correlations of circuit topology information and timing analysis results from known corners, which are respectively captured by LSTM (Long Short-Term Memory) and MMoE (Multi-gate Mixture-of-Experts) networks. Experimental results demonstrate that with the proposed framework, the path delays at low voltages could be predicted across wide voltage range with rRMSE of less than 2.9% and 4.7% for seen and unseen circuits respectively. Compared with the learning-based models used in prior works, the proposed framework achieves significant prediction error reduction by up to 19.1×.

Advanced safe battery storage systems with health prognostic performance are vital for electric vehicles. Various faults of lithium-ion batteries are usually undetectable in their early stage due to their concealment and graduality. This paper presents a real-time fault diagnosis and isolation scheme for real-scenario batteries using the normalized discrete wavelet decomposition. The early frequency-domain features of the fault signals are extracted utilizing the high-frequency detail wavelet components, and a multi-level fault prognosis strategy is developed considering complex charging/driving characteristics under real-vehicle operating conditions. The verification results, implemented on loose wire connection batteries and real-scenario thermal runaway batteries, demonstrate that the proposed method can accurately extract and locate the hidden fault signals even under small magnitudes, as well as effectively detecting and isolating battery faults before thermal runaway. Furthermore, significant reliability and stability of the proposed method are verified on more real-vehicle operation data, enabling online monitorable and traceable of battery faults before triggering thermal runaway, safeguarding drivers and passengers in real-world vehicular operation.

The continuous monitoring of transmission line protection relay is desirable to ensure the system disturbance such as fault inception is detected in transmission line. Therefore, fault on transmission line needs to be detected, classified, and located accurately to maintain the stability of system. This project presents design enhancement and development under voltage relay in power system protection using MATLAB/Simulink. The under-voltage relay is a relay that has contacts that operate when voltage drops below a set voltage which is used for protection against voltage drops to detect short circuit and others. This study is carried out for all types of faults which only related with one of the parallel lines. For the overall of operation conditions, the sample data were generated for the system by varying the different fault types and fault location. This design system proposes the use of MATLAB/ Simulink based method for fast and reliable fault classification and location for a various type of fault.

A new, effective pi-based control method for a neutral 3-level inverter with a unified series and shunt converter is provided in this work. The proposed series of shunting and 3-levels can restrict harmonic current source and combat interruptions of voltage such as voltage drops, swells, imbalances and harmonics. With serial integration and shared DC bus capacitors, it is constructed with Active filters (AFs). With the proportional integrated voltage controller, the DC voltage is continually maintained. The Synchronous SRF theory is utilized to gather APF reference signals and power response theory (p-q theory). For the switching signal the shunt and series APF signal generated by the control algorithm and the observed signal was supplied into two controllers. In the management of the APF Series, PI approaches are employed to enhance capacities and shift 3-tier conversion devices. The power, power and voltage harmonics and any correction for any other voltage disturbance are assessed in the proposed 3 level range and shunt converter with the Matlab-Simulink Software and SimPower System Tool Box. The results of the simulation show the performance of the three-story series & shunt converter's non-linear load for improving energy quality at the sharing point.

This paper describes an adaptive noise generator circuit suitable for on-chip simulations of stochastic chemical kinetics. The circuit uses amplified BJT white noise and adaptive low-pass filtering to emulate the power spectrum and auto-correlation of random telegraph signals (RTS) with Poisson-distributed level transitions. A current-mode implementation in the IHP 0.25 µm BiCMOS process shows excellent agreement with theoretical results from the Gillespie stochastic simulation algorithm over a 60 dB range in mean current levels (modeling molecule count numbers). The circuit has an estimated layout area of 0.01 mm2 and typically consumes 100 µA, which are 10× and 8× better, respectively, than prior implementations.

Now adays Very Large-Scale Integration (VLSI) circuits have good or great demand. Because CMOS circuit design having less power consumption. Transistors on the chip is doubled every two years, according to Moore’s law. So, it means transistor size is decreasing. This leads to increase the chip density and decrease the device size. The write and read depending on the bitline and bitline bar discharging and charging. When design the memory in below 16 nm uses Fin Field effect Transistor (FinFET) technology instead of CMOS (Complementary metal oxide semiconductor field effect transistor). Because to avoid short channel effect. Comparing leakage power, dynamic power and static power at 90 nm technology and write delay, read delay at both 90 nm and 45 nm technology in nine transistors (9 t), eight transistor (8 t) and six transistor (6 t) sram cell.

Accurate and timely fault diagnosis of the rotating rectifier for a wound-rotor synchronous starter/generator is of great importance to improve system reliability. In the generation mode of the system, there is one idle stator winding of the main exciter. The terminal voltage characteristic of the idle stator winding is analyzed, and a novel fault diagnosis method for the rotating rectifier in the generation mode of the system is proposed. In this method, two feature voltages, namely, the maximum peak voltage and any other peak voltage of the idle stator winding terminal voltage are extracted through voltage sequence reconstruction to calculate the feature ratio for fault detection. The corresponding rotor position obtained by an inherent position sensor where the maximum peak voltage occurs is collected to determine the faulty diode location. The experimental results verify the feasibility and effectiveness of the proposed fault diagnosis method.

In this paper, a non-isolated dc-dc high step-up converter with passive switched-inductor-capacitor network is proposed, which is applicable for the required high gain voltage low power applications, such as battery-powered LED lighting systems and high-intensity mobile discharge lamps. The proposed circuit can produce higher gain voltage with small duty cycle, which decreases the voltage stress and conduction power loss on the active switches. In contrast to other non-isolated dc converters, by using the same or analogous number of passive/active components in circuit topology, the proposed topology has lower voltage stresses across capacitors and diodes, lower inductor current stresses. Therefore, the efficiency and reliability of the circuit topology can be ameliorated. The theoretical principle, parameter design guideline, small-signal dynamic analysis, power loss analysis and performance comparison with other dc-dc non-isolated converters have been implemented. Finally, a 200 W experimental setup is built and tested with an input dc voltage of 36V–60V and an output voltage of 200V to validate the aforementioned merits of the proposed circuit.

The single gate driven series connected power device stack possesses the advantages of high compactness and low cost. However, research of its short circuit (SC) characteristic remains uncovered. This article fills this gap and points out that, with the single gate driver it has the potential of over-current limitation. Furthermore, based on it, an improved single gate driven silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (mosfet) stack with strong antishort circuit fault capabilities is proposed. By adding auxiliary circuits to adjust the driving process of the single gate driver, the SiC mosfet stack can be automatically turned off in both SC conditions of fault under load and hard switch fault, while the normal working principle of the stack is not influenced. Neither active control nor overcurrent detection is required, which is the biggest merit of the proposed topology. Its design and analysis are presented in detail, followed by the validation by conducting simulations and experiments.

Modular multilevel converter (MMC) topology has received widespread attention in flexible DC transmission, power quality control, and other fields because of its high modularity and malleability characteristics, and has become one of the most promising topologies. However, owing to the characteristics of the MMC itself, the fluctuation of the capacitor voltage of the MMC sub-module is inversely proportional to the MMC working frequency. One of the main technical challenges for MMC is effectively suppressing the fluctuation of the capacitor voltage of the MMC sub-module when working at low frequencies. This study first analyzes the reasons for the fluctuation of the MMC sub-module capacitor voltage at low frequency. Then, based on the results of this analysis, we propose a suppression control strategy for the capacitor voltage fluctuation of the MMC sub-module in variable-frequency working situations. Finally, an MMC module was built using the MATLAB/Simulink environment for simulation verification, and a five-level MMC physical experimental platform was built for experimental verification. The simulation and experimental results demonstrate that the proposed suppression control strategy for the MMC sub-module capacitor voltage effectively suppresses the fluctuation of the capacitor voltage under variable-frequency working situations.

This paper introduces a new coupled inductor based dual-input ultra-high step-up DC-DC converter with a high voltage conversion ratio, low voltage stress across semiconductor components, and high efficiency features. The coupled inductor and voltage multiplier circuit (VMC) techniques have been utilized to enhance the voltage gain. The blocking voltages of power switches are clamped by VMC at low values and can be controlled via the turn ratio of the coupled inductors that decreases the voltage rate of power switches and converters cost. The presented dual-input structure can transfer power to the load from two independent voltage sources. Also, the inputs and output ports are common ground, which can reduce the electromagnetic interference (EMI) influences. Operation modes delineation, steady-state analysis, and comparison section are provided for describing the proposed structure performance. Finally, to confirm the effectiveness of the presented topology, experimental waveforms with a 200 W output power at 50 kHz operating frequency are presented.

Non-isolated high-voltage gain soft-switching dc-dc converter is an ideal candidate for distributed generation system converters. This paper proposes a high-voltage gain soft switching quasi-Z-source dc-dc converter. The converter integrates a coupled inductor and switched capacitor into a quasi-Z-source network. Soft switching is achieved for all active devices in the converter by controlling the auxiliary switch Sa. By inheriting the advantages of the quasi-Z-source network and coupled-inductor/switched-capacitor, the converter has high voltage gain, high efficiency, low input current ripple, low voltage spike of main switch, and common ground. In addition, the efficiency of the converter is improved by recycling the energy of leakage inductance, resulting from an inherent active clamp of the main switch. The steady-state operation, voltage relationship, current/voltage stress, and power dissipation of each component of the converter have been analyzed and derived in detail. The properties of the proposed converter are verified by designing a 200 W prototype in the laboratory. When the input voltage is 48 V and the output voltage is 380 V, the converter efficiency reaches 96.92%, while the efficiency is 93% in a hard switching. The key waveforms of the converter obtained from the experiment agree well with the theoretical analysis results.

DC-field excited modular variable flux reluctance machines (VFRM) have passive salient-pole rotor, which makes it suitable for high-speed applications. In addition, independent stator winding eliminates the electrical, magnetic, and thermal coupling among phases, improving its reliability. However, fault-tolerant operation is still required to improve its output capability under post fault. Hence, the performance under winding open-circuit faults is analyzed and the fault-tolerant control strategy is presented to increase the output capacity in this paper. Firstly, the DC-rectified output voltages and power of the VFRM under both normal and open-circuit faults are derived. Then, phase angle control (PAC) strategy of the fault-tolerant operation for a 12-slot-14-rotor-pole (12s14r) modular VFRM is proposed, where the control sequence is optimized to achieve the maximum output power of the generation system. Compared with the classical fault-tolerant method, a higher applicability of the proposed method in terms of the types of fault-tolerant operations can be achieved. The electromagnetic properties, including the armature current and the capacity of electrical power output are analyzed with finite element analysis. The effectiveness and feasibility of the proposed fault-topology and control strategy are verified by the 12s14r VFRM prototype in normal, fault and fault-tolerant operation.

We associate to triangulations of infinite type surface a type of flip graph where simultaneous flips are allowed. Our main focus is on understanding exactly when two triangulations can be related by a sequence of flips. A consequence of our results is that flip graphs for infinite type surfaces have uncountably many connected components., 15 pages, 5 pages

International audience; The work presented in this two-part paper focuses on a prediction method of the radiated susceptibility of integrated circuit and printed circuit board from near-field scan injection, in order to anticipate risks of non-compliance due to design weakness. In Part I, a worst-case estimator of the far-field induced voltage on a PCB trace was proposed. Based on it, an estimator of the radiated susceptibility of a printed-circuit board based on near-field scan results is derived and validated through two validation case studies.

Cloud storage is a cost-effective platform to accommodate massive data at low cost. However, advances of cloud services propel data generation, which pushes storage servers to its limit. Deduplication is a popular technique enjoyed by most current cloud servers, which detects and deletes redundant data to save storage and bandwidth. For security concerns, proof-of-ownership (PoW) can be used to guarantee ownership of data such that no malicious user could pass deduplication easily or utilize such mechanism for malicious purposes. Generally, PoW is implemented in static data archive where the data file is supposed to be read-only. However, to satisfy users' needs for dynamical manipulation on data and support real-time data services, it is required to devise efficient PoW for dynamic archive. In this work, we propose the notion of bidirectional and malleable proof-of-ownership (BM-PoW) for the above challenge. Our proposed BM-PoW consists of bidirectional PoW (B-PoW), malleable PoW (M-PoW) and dispute arbitration protocol DAP. We provide the security analysis of our proposal, and performance evaluation that suggests our proposed B-PoW is secure and efficient for large file in static data archive. In addition, our proposed M-PoW achieves acceptable performance under dynamic setting where data is supposed to be outsourced first and updated later in dynamic data archive.

Evaluating the robustness of power semiconductor devices is key for their adoption into power electronics applications. Recent static acceleration tests have revealed that SiC MOSFETs can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the high-bias robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc-bias higher than the device rated voltage. Under this high-bias switching condition, SiC MOSFETs show degradation in merely tens of hours at 25°C and tens of minutes at 100°C. Two independent degradation and failure mechanisms are unveiled, one present in the gate-oxide and the other in the bulk-semiconductor regions, featured by the increase in gate leakage current and drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. These results suggest the insufficient robustness of SiC MOSFETs under high-bias, hard switching conditions and the significance of using switching-based tests to evaluate the device robustness.

Introducing bond wire diagnosis for multichip IGBT modules is key to the health monitoring of modular multilevel converters (MMCs), which allows for improved field robustness, reliability, and reduced maintenance cost. This paper leverages the crosstalk phenomenon during switching transitions to detect the chip open-circuit faults caused by the bond wire lift-off using typical half-bridge IGBT modules in a multichip-parallel configuration. The cycle-controlled, non-intrusive measurement is conducted under normal operation, when the device under test is at off-state and its complementary switch is during switching transitions. Two specialized health sensitive parameters arising from the dynamic gate loop waveforms are identified and evaluated, including 1) the gate voltage VGE(t3) when the declining collector voltage reaches zero, and 2) the negative peak gate voltage VGE(t4). The sensitivity and stability of these two parameters are compared through theoretical analysis, circuit simulation and practical verification. The results show that VGE(t4) is more suitable for online monitoring, while VGE(t3) is more sensitive than VGE(t4). With managed complexity in gate drives, this proposed health awareness approach is feasible in the submodules of MMC applications, but it can also be used in other power converter topologies incorporating the half-bridge structure.

This paper presents novel radiation hardening design techniques to substantially reduce the single event effects (SEE) on high-frequency receivers subject to various radiations when operating in space. A W-band (75-110 GHz) receiver front-end implemented in Global Foundry’s 90 nm SiGe BiCMOS technology is used for studying SEE and investigating the effectiveness of the proposed techniques. Specifically, the mixer is modified to allow for different modes of operation, in addition to introducing matching considerations between the mixer’s gain and switching stages. The receiver includes integrated high frequency signal sources to provide the input radio frequency (RF) and local oscillator (LO) signals for full operation of the proposed millimeter-wave (mmW) receiver. Measurements are taken while the receiver is in normal operation (RF and LO are applied.) The design techniques are carefully analyzed via extensive simulations using equivalent transient current pulses obtained from calibrated Technology Computer-Aided Design (TCAD) simulations. A two-photon-absorption (TPA) pulsed laser experiment is used to induce transient currents in the silicon–germanium heterojunction bipolar transistor (SiGe HBT) circuit. Various devices within the mixer are hit from the back side through a hole in the designed printed circuit board (PCB.) The propagated transients are then captured using a high-speed oscilloscope at the output of the receiver. The measurement results, supported by simulations and analysis, validate the robustness of the proposed radiation hardened receiver to SEE.

The outsourcing of the design and manufacturing of integrated circuits has raised severe concerns about the piracy of Intellectual Properties and illegal overproduction. Logic locking has emerged as an obfuscation technique to protect outsourced chip designs, where the circuit netlist is locked and can only be functional once a secure key is programmed. However, Boolean Satisfiability-based attacks have shown to break logic locking, simultaneously motivating researchers to develop more secure countermeasures. In this paper, we present a novel fault injection attack to break any locking technique that relies on a stored secret key, and denote this attack as AFIA, ATPG-guided Fault Injection Attack. The proposed attack is based on sensitizing a key bit to the primary output while injecting faults at a few other key lines that block the propagation of the targeted key bit. AIFA is very effective in determining a key bit as there exists a stuck-at fault pattern that detects a stuck-at 1 (or stuck-at 0) fault at any key line. The average complexity of number of injected faults for AFIA is linear with the key size and requires only |K| test patterns to determine a secret key, K. AFIA requires a fewer number of injected faults to sensitize a bit to the primary output, compared to 2|K|-1 faults for the differential fault analysis attack [26]., arXiv admin note: text overlap with arXiv:2007.10512

For a flying capacitor multilevel converter (FCMC), prompt detection of power switch failures is crucial for fault-tolerant operation. This paper presents a new technology for identifying and locating faulty cells in FCMC. Mathematical derivation points out that different fault types and locations will present different high-frequency harmonics. The new technology extracts high-frequency harmonics in the switch node voltage and look up a pre-established table to identify the fault type and location. The discrete Fourier transform (DFT) can be easily performed to analyze the harmonic using the built-in IP core in Field Programmable Gate Array (FPGA). For a FCMC with any number of levels, the new approach requires only one voltage sensor, and can accurately locate the faulty cell after one carrier cycle when the fault occurs. Both simulation and experimental results validate the proposed concept on a 5-level 100 kHz GaN FET based FCMC prototype. Furthermore, we have experimentally demonstrated fault-tolerant operation of the FCMC after a switch short and open fault is detected and identified by the new technique.

The superior electrical and thermal characteristics of SiC MOSFETs bring major challenges to its short-circuit reliability. To fully understand its short-circuit mechanism, estimate its safe operating area, and provide guidance for circuit design, it is crucial to establish a theoretical model to quantize the relationship between circuit parameters and short-circuit behavior of SiC MOSFETs. A temperature-dependent analytical model considering the parasitic inductances, nonlinear junction capacitances, and temperature dependence of the channel current is proposed in this paper, which only uses the parameters in the datasheet or provided by manufacturers. The proposed model is established based on the analysis for each short-circuit stage in both single-device configuration and half-bridge configuration, and the quantitatively analytical results of the transient short-circuit waveforms, energy loss, and junction temperature rise can be calculated by solving the model. The accuracy of the analytical model is verified by comparing the analytical results with the experimental results. Furthermore, the effects of varied parameters on the short-circuit behavior are evaluated by the proposed analytical model. And the corresponding circuit design guidance for higher short-circuit reliability is given.

This paper introduces a fault-tolerant reconfiguration topology and control strategy for symmetric open-winding multiphase machines. Bidirectional switching devices are proposed to connect the inverter bridge legs on different ends when the open-circuit fault occurs, and the reconfigured circuit can regenerate the missing voltage phasors due to the faults. Furthermore, to prevent overcurrent problems on the reconfigured bridge legs and maximize the torque output capability of the reconstructed system, winding currents are optimized with zero-sequence component injection during fault-tolerant operation. The experiments implemented on the five-phase system validate that the proposed fault-tolerant scheme is effective and has higher torque output capability compared with the traditional fault-tolerant solutions.

Continuous scaling of the VLSI system leaves a significant challenge on manufacturing; thus optical proximity correction (OPC) is widely applied in conventional design flow for manufacturability optimization. Traditional techniques conduct OPC by leveraging a lithography model but may suffer from prohibitive computational overhead. In addition, most of them focus on optimizing a single and local clip instead of addressing how to tackle the full-chip scale. In this paper, we present DAMO, a high-performance and scalable deep learningenabled OPC system for full-chip scale. It is an end-to-end mask optimization paradigm that contains a deep lithography simulator (DLS) for lithography modeling and a deep mask generator (DMG) for mask pattern generation. Moreover, a novel layout splitting algorithm customized for DAMO is proposed, composed of DBSCAN clustering and KMeans++ clustering, to handle the full-chip OPC problem. Further, graph-based computation and parallelism techniques are proposed to deploy our GPU algorithms to accelerate computations. Extensive experiments show that DAMO outperforms state-of-the-art OPC solutions in both academia and industrial commercial toolkit.

SiC MOSFET is a promising power device for electric drive system due to its various advantages such as high switching frequency and low loss. However, fast switching speed results in high voltage stress and can potentially cause insulation damage of the winding. Few studies have analyzed and evaluated the voltage stress, especially for the hairpin winding, which is the mainstream winding type for electric vehicle traction machines. For this purpose, this paper proposes a high-frequency equivalent circuit model to predict the inter-turn voltage stress of hairpin windings driven by SiC MOSFETs. Firstly, the working principle of the overvoltage at the winding ends is analyzed and validated by experiments. Then, the parasitic parameters are calculated before building the high-frequency equivalent circuit. A field-circuit coupled finite element method is used to consider the nonlinear parameters and to evaluate the voltage stress. Finally, a prototype is built, and the voltage stress is tested. The resultant error between the calculated and experimental maximum inter-turn voltage stress is only 1.3%, which supports the inference on the validity of the presented equivalent circuit and the method. Based on the above, a novel winding connection scheme is proposed to reduce effectively the voltage stress of hairpin winding.

In recent studies, a fault analysis method called persistent fault analysis (PFA) is proposed for cracking block ciphers. Unlike widely used differential fault analysis methods, PFA does not require correct cihpertexts and precise time control of fault injection. The existing PFA methods mainly assume single fault, i.e., the fault injection process induces a single fault in the target cipher devices. However, the existing lowcost fault injection attack (FIA) techniques such as clock glitch injection and electromagnetic pulse (EMP) injection usually induce multiple faults per injection. Given multiple faults, the existing PFA methods are either not applicable or faced with high computational complexity in practice. In this paper, a new PFA method called MPFA is proposed for multiple persistent faults, which reduces both the computational complexity and the required ciphertexts. MPFA can be applied to the ciphertextsonly attack scenario where all fault positions, fault values and fault quantity are unknown. The experiments show that compared to the existing PFA methods, the MPFA method reduces the required ciphertexts for cracking AES by at least 57.5% and reduces the computational complexity NF16 times for NF faults. The proposed MPFA is also evaluated on the block ciphers LED and PRINCE. Moreover, a real EMP fault injection attack is carried out and the key of AES-128 is successfully cracked by the MPFA method, demonstrating its validity and efficiency.

Health economists have written extensively on the design and implementation of coverage with evidence development (CED) schemes and have proposed theoretical frameworks based on cost-effectiveness modeling and value of information analysis. CED may aid decision-makers when there is uncertainty about the (cost-)effectiveness of a new health technology at the time of reimbursement. Medical devices are potential candidates for CED schemes, as regulatory regimes do not usually require the same level of efficacy and safety data normally needed for pharmaceuticals. The purpose of this research is to assess whether the actual practice of CED for medical devices in Europe meets the theoretical principles proposed by health economists and whether theory and practice can be more closely aligned. Based on decision-makers' perceptions of the challenges associated with CED schemes, plus examples from the schemes themselves, we discuss a series of proposals for assessing the desirability of schemes, their design, implementation, and evaluation. These proposals, while reflecting the practical challenges with developing CED programs, embody many of the principles suggested by economists and should support decision-makers in dealing with uncertainty about the real-world performance of devices.

This article presents a programmable multiple frequencies clock generator with a process and temperature compensation circuit design. The proposed clock generator can achieve a stable and wide frequency range output for a single input frequency by using digital control codes as well as process and temperature compensation mechanisms. In our approach, the first step is to adjust the duty-cycle of the input clock by using a digitally controlled pulsewidth modulator (DCPWM) to generate an output clock signal with a duty-cycle of 20% to 80%. Second, the various duty-cycle clock outputs of the DCPWM are integrated by the duty-cycle-to-voltage converter to generate analog voltage signals to control the succeeding voltage-controlled ring oscillator (VCO). Through the use of various control voltages, different VCO output frequencies are generated. Finally, by using the process and temperature compensation circuit, the proposed clock generator can provide a stable and wide frequency range. The proposed chip is fabricated in a 180-nm CMOS process and has an output frequency range of 35–138 MHz at a supply voltage of 0.9 V. At 120 MHz, the power dissipation and rms jitter are 224.3 μW and 7.84 ps, respectively. The active area of the chip is 0.62 mm × 0.76 mm.

During the manufacturing process of three-dimensions integrated circuits (3-D ICs), many defects may occur in through-silicon vias (TSVs). These defects affect integrity of the signal passing through TSVs, therefore detecting these defects in early production stage is crucial. This paper proposed a built-in-self-test (BIST) method with simple test structure and easily-implemented fault detection process. Due to the fact that the defects in TSVs influence the charge/discharge speed of TSVs’ equivalent capacitance, a weak current source is designed as the central part of the proposed test structure, which can measure the TSVs’ charge/discharge speed and quantify it using digital values. The effectiveness and robustness of the proposed method is validated by HSPICE simulation. The minimum measurable fault, test time and test circuit area are also assessed in this paper. The simulation results show that the method this paper proposed can detect weaker faults, compared with the traditional test methods.

Insulated Gate Bipolar Transistor (IGBT) module is one of the most prone-to-fail components in the wind power converter. The reduction of the junction temperature swing by thermal management can improve the reliability of a wind power converter. Due to the lack of an applicable selection criterion, not many studies on the control target of junction temperature swing were reported. This paper proposes a thermal management strategy to find the control target of junction temperature swing. The proposed strategy considers the return on investment (ROI) of thermal management as a quantitative indicator to guide the control target selection. The selected control target enables optimal benefit of the thermal management. Results show that a 1%-increase in the total harmonic distortion would extend the lifetime of IGBT module by 0.144 years. Success of the proposed scheme lies in the efficient regulation of the junction temperature swing. Case studies with different mission profiles and experimental tests on a three-phase two-level inverter are presented to validate the proposed method.

This paper proposes a traveling wave based scheme for wye-connected shunt capacitor bank protection. The proposed method provides high sensitivity and fast response, assisting in mitigating capacitor damage during internal cascading failure. The available protection schemes for capacitor bank use RMS values of voltage and current phasors for trip decision. Threshold selection is required in these methods which needs accurate estimation of equivalent capacitance of the bank. In addition, phasor being estimated from one-cycle running data window, such a method is slow. The proposed traveling wave based method identifies an internal fault in case of opposite polarities of traveling waves seen in the terminal voltage and current signals of the faulted phase. If the mid-point tapping is available in capacitor bank, the faulted half can be identified using the traveling wave of tap voltage. The magnitude of the traveling wave in terminal voltage reveals the number of failed capacitor elements. Such information assists in expediting maintenance. The performance of the proposed method is tested using PSCAD/EMTDC simulation data for various situations, including internal short circuit, external, and identical faults in the shunt capacitor bank. Comparative analysis highlights its higher sensitivity and better accuracy in comparison to available protection methods.

To address the most commonly seen single IGBT open-circuit fault problems in cascaded H-bridge (CHB) converter based STATCOM, a simple online fault diagnosis method and the corresponding ride-through operation approach are proposed. The method can quickly determine the exact location of the open-circuit IGBT through three steps, via analyzing the relationships between the dc bias in the three-phase output current of CHB converter, the transient dc rail voltage variations with respect to the averaged dc rail voltage, and the response of dc rail voltage and output current when the modulation approach of the faulty power module is adjusted. Afterwards, a fault ride-through approach is adopted to seamlessly transfer the modulation approach of faulty H-bridge module and it behaves as a half-bridge to provide a half of the rated output AC voltage. Meanwhile, the corresponding dc offset voltage form this faulty module is compensated by producing the same dc voltage in the healthy phase legs to avoid the dc bias in the three-phase output current. It has been demonstrated that the proposed fault diagnosis approach and the fault ride-through approach are effective in various adverse situations including grid voltage sudden disturbances and the load power sudden changes.

Solid-state transformers can be applied in the AC/DC hybrid distribution network. The reliability and power density of a solid-state transformer is significantly influenced by the insulation design of the isolated DC-DC converter and, in particular, its medium-voltage medium-frequency transformer. This paper proposes an insulation design method for the medium-voltage medium-frequency transformer. A novel insulation structure is adopted to reduce the volume and improve the heat dissipation performance. Optimization of insulation distance parameters is performed based on finite element method simulations. The proposed method is applied to a 60 kVA/10 kHz transformer, and the simulation results verify the improved performances with the proposed insulation design method. A prototype is developed according to the proposed scheme, and the experimental results of a DC-DC converter and the partial discharge and applied voltage tests are presented.

A three-level bidirectional AC-DC converter with H8 topology is proposed to combine the advantages of both neutral-point clamped and flying-capacitor three-level converters for medium voltage AC-DC solid-state transformer applications. The innovative H8 converter features self-balanced capacitor voltage, common-mode voltage elimination, and small capacitance of the flying capacitors. The proposed carrier-based modulation enables the H8 converter to operate under both active and reactive power conditions. A 10 kVA AC-DC converter prototype with 1.7 kV SiC MOSFETs and 3.3 kV SiC diodes verifies the feasibility and advantages of the proposed topology and the modulation method. The capacitance of the flying capacitors in the H8 converter is reduced by 45 times compared to that of the flying-capacitor converters. The H8 converter efficiency is tested up to 99% at 2 kV DC voltage. The proposed H8 converter is suitable for the next-generation PV inverter, grid-forming inverter, MV fast charger, and SST applications.

In this article, fault diagnosis is of great significance for system health maintenance. For real applications, diagnosis accuracy suffers from unbalanced data patterns, where normal data are usually abundant than anomaly ones, leading to tremendous diagnosis obstacles. Therefore, it is challenging to use only normal data for fault diagnosis under this imbalanced condition. In addition, a single fault diagnosis model can only conduct one fault diagnosis task in most of cases. Accordingly, a one-class generative adversarial detection (OCGAD) framework based on semisupervised learning is proposed to learn one-class latent knowledge for dealing with multiple semisupervised fault diagnosis tasks, i.e., fault detection using only normal knowledge learning, novelty detection from unknown conditional data, and fault classification with unlabeled data. A bi-directional generative adversarial network (Bi-GAN) is first trained with only normal data. A one-class support vector machine is then established using features exacted by Bi-GAN from signals acquired from an attitude sensor for multifunctional fault detection. The presented OCGAD model is validated using an industrial robot with experiments of three fault detection tasks. The results demonstrate that the present model has good performance for dealing with multiple semisupervised diagnosis problems. info:eu-repo/semantics/publishedVersion

Following the continuous development of wide bandgap (WBG) devices and multilevel converter technology, medium voltage (MV) active front ends (AFEs) are becoming promising in future high-power-density and high-power applications. However, the cost issue is one of the major drawbacks, which stops the WBG devices from being widely applied in high-power areas. This paper proposes a silicon carbide (SiC) and silicon (Si) hybrid five-level unidirectional rectifier. It requires only four SiC MOSFETs with relatively low blocking voltage and four Si diodes. Meanwhile, by adding snubber capacitors, all the Si devices are with low-speed switching, and the voltage stresses of fast SiC MOSFETs are minimized. In this paper, operational analysis and carrier-based phase-disposition PWM scheme for this circuit are discussed in detail. The capacitor voltage balancing and unity power factor are both realized. Simulation and scaled-down experimental results are demonstrated to verify the proposed rectifier. Furthermore, the comparison of the hybrid five-level rectifiers is given to show the advantages of the proposed rectifier in terms of voltage stress, efficiency, and cost.

In order to locate the leakage fault location of low-voltage electrical lines, cut off the power supply of electrical lines, and ensure the safety and reliability of the power supply network, this paper proposes an electrical line leakage fault detection system based on a signal trigger. Based on the research on the current leakage protection system of low-voltage electrical lines, the author puts forward that the leakage current of the selected test analog trigger signal is not less than twice the maximum value of the normal leakage current of electrical lines and equipment with STC15F2K60S2 single-chip microcomputer as the control core. The experimental results show that 30 mA is preferred for the sensitivity of the leakage fault test signal. When the rated leakage action current is equal to or less than 30 mA, the protection action time is required to be less than 0.1 s, and when the rated leakage action current is greater than 30 mA, it is required to be less than 0.2 S. The device is a supplement to the traditional leakage protection device. According to the comparison between the indirect leakage detection and direct leakage detection results and the actual leakage position distance, the error is within 10%. It is proved that the system meets the actual needs and improves the protection performance of the leakage protection system of low-voltage electrical lines.

Aiming at the popularization and application of a real-time monitoring parameter acquisition system of the electric submersible pump (ESP) well, this paper proposes a fault diagnosis method of ESP well operation based on the SPC rule and prior knowledge fusion. Based on the study of parameter variation rules of ESP well, the SPC expansion rule model is established; by analyzing the variation of some typical characteristic parameters of ESP well, combined with SPC expansion rules and expert experience, a priori knowledge of fault diagnosis of ESP well is formed, that is, multiparameter fault analysis table and weight factor; the SPC extended rule model and prior knowledge are fused to establish the fault probability model of ESP well, form the fault diagnosis method of ESP well, develop the online fault diagnosis software of ESP well, and deploy it in 425 ESP wells in a block. Taking five types of tubing leakage, pump wear, shaft breakage, gas influence, and pump plugging as examples, the application process of fault diagnosis method is analyzed. The research and application show that compared with other fault diagnosis methods, this method needs a smaller time window and higher diagnosis accuracy. By setting multiple time windows, this diagnosis method is applied to calculate the fault probability of ESP well in real time, solve the real time and accurate identification of 14 sudden faults and gradual faults, and significantly improve the intelligent diagnosis level of production faults of ESP well.

The rapid growth of the globalized integrated circuit (IC) supply chain has drawn the attention of numerous malicious actors that try to exploit it for profit. One of the most prominent targets of such parties is the third-party intellectual property (3PIP) vendors and their circuit designs. With the increasing number of transactions between vendors and system integrators, the threat of IP reuse and piracy has become a significant consideration for the IC industry. What is more, the correctness of 3PIP designs should be verified before integration, imposing another challenge for 3PIP vendors since they have to prove the functionality of their designs to system integrators while protecting the privacy of the circuit implementations. To eliminate this deadlock, we utilize the cryptographic technique of “zero-knowledge proofs” to enable 3PIP vendors to convince system integrators about various functional properties of a circuit (e.g., area, power, frequency) without disclosing its netlist (i.e., in zero-knowledge). Our approach comprises a circuit compiler that transforms arbitrary netlists into a zero knowledge-friendly format and a library of modules that provide cryptographic guarantees for various properties of the netlist while hiding the actual gates. We evaluate our method using combinational and sequential circuits from the ISCAS and ITC benchmark suites.

Multicore platforms are becoming the dominant trend in designing Mixed-Criticality Systems, which integrate applications of different levels of criticality into the same platform. The availability of multiple cores on a single chip provides opportunities to employ fault-tolerant techniques, to ensure the reliability of MCSs. However, applying fault-tolerant techniques increases the power consumption on the chip, and thereby, on-chip temperatures might increase beyond safe limits. To prevent thermal emergencies, urgent countermeasures, like DVFS or DPM will be triggered to cool down the chip. Such countermeasures, however, might not only lead to suspending low-criticality tasks, but also might lead to violating timing constraints of high-criticality tasks. Therefore, it is indispensable to consider a temperature constraint within the scheduling process of fault-tolerant MCSs. Therefore, this paper presents, for the first time, a thermal-aware scheduling scheme for fault-tolerant MCSs, named TherMa-MiCs, which satisfies the temperature constraint jointly with the timing constraints of the high-criticality tasks, while attempting to maximize the QoS of low-criticality tasks under the predefined constraints. At the same time, a reliability target is satisfied by employing the well-known N-Modular Redundancy fault-tolerant technique. Experimental results show that our proposed scheme meets the temperature and timing constraints, while at the same time, improving the QoS of low-criticality tasks, with an average of 44%.

The phase-locked loop (PLL) is an essential synchronization technique to ensure stable operation and control of grid-connected converters. Nevertheless, under actual conditions, the grid voltage is often influenced by harmonics and frequency variation, resulting in unsatisfactory steady-state precision and dynamic performance of the PLL. Therefore, in this paper, an improved digital PLL (ID-PLL) including harmonics elimination module and angular frequency reference calculation module is proposed. The proposed ID-PLL can maintain steady-state precision and dynamic performance in the condition of voltage unbalance, voltage harmonics and voltage frequency variation. The influence of adverse grid voltage on PLL performance is analyzed in detail. The parameters design and discretization approach is presented accordingly. The effectiveness of the proposed approach is confirmed by compared experiments with DSOGI-PLL.

Since spiking neural networks can effectively simulate the information processing mechanism of the biological cortex, they are expected to bridge the gap between neuroscience and machine learning. The hardware simulation of large-scale spiking neural networks requires a simple and versatile silicon neuron model framework. In this paper, a spiking neuron circuit as the core device of spiking neural networks is presented. The proposed neuron circuit can mimic the dynamics of different types of biological neurons by adjusting the bias voltage. In order to facilitate the implementation of the spiking neuron circuit based on complementary metal-oxide-semiconductor (CMOS) and reduce the overhead of the circuit area, a modified Mihalas-Niebur mathematical model is adopted. The improved Mihalas-Niebur model is biologically plausible and can still successfully display all dynamic behaviors observed in biology. The function of the proposed neuron circuit has been verified by the phase diagram analysis method. The simulation results show the designed neuron circuit can successfully replicate 15 of the 20 firing patterns exhibited by the biological cortex, which proves that the neuron can act as a universal spiking neuron in very large-scale integrated circuit (VLSI) neuromorphic networks.

DC short-circuit current calculation is necessary to design and protect modular multilevel converter-based (MMC-based) multi-terminal DC (MTDC) grids. In this paper, a general and analytical short-circuit current calculation method is proposed for bipolar MTDC grids. For pole-to-pole (P2P) faults, the superposed fault equivalent network of the MTDC grid is first developed in the frequency-domain. Then, a decoupling method based on the network inductance ratio is proposed, which simplifies the high-order network into the superposition of several independent two-order RLC circuits. As a result, the short-circuit current can be expressed as the sum of the currents of these RLC circuits. For P2G faults, the phase-domain DC line impedance considering the coupling effects is determined based on its modal-domain parameters, so that the P2G fault current can be calculated using the method of the P2P fault. The proposed methods effectiveness is verified through simulations and experiments, and the calculation error is classified and analyzed. Compared with the existing methods, the proposed method is more accessible, more accurate, and available for hand-solution.

To construct the bipolar low-voltage dc distribution system, a dual-active-bridge (DAB) converter and a voltage balancer are needed. However, this conventional two-stage circuit is bulky and shows low efficiency. Besides, when a short circuit fault occurs at one of the bipolar dc poles, the conventional topology cannot balance the other normal dc pole voltage due to its single closed circuit, which eventually loses the high reliability of the bipolar system. To mitigate those issues, a modified three-port DAB converter is proposed. The proposed converter is an enhanced topology of the three-port DAB converter, which can balance the bipolar voltage levels without additional voltage balancers. In addition, each bipolar output has an independent closed circuit to balance the normal dc pole under the short circuit fault at one of the dc poles, thereby improving the system reliability. Moreover, constant duty-cycle modulation and magnetizing inductance design are proposed to obtain full-range ZVS of all switches. Since the proposed ZVS modulation uses a constant duty-cycle value, its control can be easily implemented in a digital signal processor. Finally, a 2-kW prototype is developed to validate the effectiveness of the proposed converter.

Multivariate statistical process monitoring methods are often used in chemical process fault diagnosis. In this article, (I) the cycle temporal algorithm (CTA) combined with the dynamic kernel principal component analysis (DKPCA) and the multiway dynamic kernel principal component analysis (MDKPCA) fault detection algorithms are proposed, which are used for continuous and batch process fault detections, respectively. In addition, (II) a fault variable identification model based on reconstructed-based contribution (RBC) model that paves the way for determining the cause of the fault are proposed. The proposed fault diagnosis model was applied to Tennessee Eastman (TE) process and penicillin fermentation process for fault diagnosis. And compare with other fault diagnosis methods. The results show that the proposed method has better detection effects than other methods. Finally, the reconstruction-based contribution (RBC) model method is used to accurately locate the root cause of the fault and determine the fault path.