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Multiple internal reflection spectroscopy (MIRS) was applied to analyse atomic bonds at deep (500 μm) interfaces of directly bonded Si/Si wafer pairs. It is shown that under the conditions used the polarized spectra contain information only about the interface layer a few nanometers thick. Examples are given of analysing the Si-H- and SiO-H vibration modes and bands of undissociated water in interfaces of bonded hydrophobic and hydrophilic wafer pairs, respectively, after annealing at temperatures between 200 and 1100 °C. Variations of the bonding behaviour (especially caused by alterations of the Si-H bonds) are discussed.

Based on the site-binding model, the effects of two types of surfaces sites (namely, silanol sites and amine sites) and their ratio on the characteristics of an Si3N4-gate pH-ISFET are discussed. As the ratio β of silanol sites to amine sites is about 7 3 , the maximum of sensitivity of the electrolyte-insulator (E-I) interfacial potential versus the pH value, as well as of the range of linear response are theoretically obtained. The stability of pH-ISFET devices is partially determined by the total number of the two types of surface sites and their ratio. The theoretical results are shown to be supported by experimental results.

The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3∕H2O∕HF or the HNO3∕HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ∕m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

For bonded pairs of silicon-oxide-covered wafers, the bonding energy at low temperatures is significantly enhanced by very slight etching of the silicon oxide surfaces in diluted (0.05%–0.2%) HF aqueous solutions prior to room temperature contacting. The bonding energy is a factor of 10 higher than standard bonded pairs to about 2000mJ∕m2 after annealing at 100°C. The improved surface cleaning and activation with desired surface termination have been achieved by the HF dip. A fluorine concentration peak at the bonding interface measured by secondary ion mass spectroscopy suggests that the number of Si–O–Si covalent bonds at the bonding interface appears to be increased appreciably by the formation of fluorinated silicon oxide that absorbs water effectively.

An oxide-free, covalently bonded interface of InP/silicon wafer pairs has been realized at low temperature by B2H6 plasma treatment of bonding surfaces in the reactive ion etch mode followed by a HF dip and room temperature bonding in air. The bonding energy reaches InP fracture surface energy of 630 mJ/m2 at 200 °C. A total B-doped amorphous layer of about 15 A with peak concentration of ∼2×1020 cm−3 was detected at the bonding interface. The release of hydrogen at low temperature from B–H complexes and subsequent absorption of the atomic hydrogen by the amorphous layer at the bonding interface is most likely responsible for the enhanced bonding energy.

By introducing a nanometer-scale H trapping defective silicon layer on bonding surfaces, the bonding surface energy of bonded oxide-free, HF dipped, hydrophobic silicon wafers can reach a silicon fracture surface energy of 2500 mJ/m2 at 300 to 400 °C compared with 700 °C conventionally achieved. Adding boron atoms on bonding surfaces can reduce the surface hydrogen release temperature but would not increase the bonding energy unless a defective layer is also formed. This indicates that, in order to achieve high bonding energy, the released hydrogen must be removed from the bonding interface. Many prebonding treatments are available for low-temperature hydrophobic wafer bonding including the formation of an amorphous silicon layer by As+ implantation, by B2H6 or Ar plasma treatment, or by sputter deposition, followed by an HF dip and room temperature bonding in air. The interface amorphous layer may be recrystallized by annealing at elevated temperatures, e.g., at 450 °C for As+-implanted samples.

The true phonon analog of optical focusing is the redirection of flux at an interface, where continuity of interface strains requires the conservation of the wave vector component parallel to the interface on either side. Such refraction is observable only at extremely clean defect-free interfaces. We have conducted phonon imaging studies of a variety of wafer-bonded samples in which the bonded materials have a large lattice mismatch at the interface (e.g., [0 1 1] GaAs bonded to [0 0 1] GaAs). The materials on either side of the bond are of the same crystalline type but are acoustically distinct because of the deliberate misorientation of the sample faces. Phonon imaging reveals a combination of refraction and diffuse scattering at these interfaces. Comparison of the experimental images to computer simulations confirms the dominance of refraction without energy down-conversion at high quality interfaces and provides interesting evidence of inelastic phonon–defect interactions.

The piezoelectric tensors and piezoelectric charge densities of arbitrarily oriented GaAs substrates are reported for a second-rank stress tensor. The GaAs piezoelectric modulated resistors are presented, modelled and tested through the example of a cantilever. The results suggest that the piezoelectric modulated effect on GaAs would allow the monolithic integration of mechanical sensors and signal-processing circuits.

An electrostatic variable-capacitance micromotor and an electroquasistatic induction micromotor are discussed. Both the micromotors, with rotors of 160 μm diameter, have been fabricated by the surface micromachining of polysilicon. In order to reduce the friction in the micromotors, the application of a gas-lubricated bearing is proposed. An aerodynamic in-pumping spiral grooved thrust microbearing with a groove width of 4 μm and a groove depth of 300 nm has been designed and used in the micromotors.

This paper proposes the scaling-down of gas-lubricated bearings and their special application in microelectromechanical systems (MEMS). A gas bearing could eliminate the friction problem in microactuators and micromotors because its rubbing surfaces are completely separated by a film of gas. Two kinds of microbearings, the aerodynamic spiral-grooved type and an externally pressurized type, have been designed and fabricated by processes derived from IC fabrication processes. They have been used in micromotors with a rotor diameter of 160 μm and a hub diameter of 48 μm.

Summary form only given. A technique for bonding GaAs to silicon by depositing a thin phosphosilicate glass (PSG) layer on the surface of the polished GaAs member, resulting in a GaAs-Si structure, is described. The PSG layer is deposited by the chemical vapor deposition method, which is capable of controlling film composition and thickness. Scanning electron microscopy (SEM) has been used to view the cross-section image of the GaAs-PSG-Si structure. An etch-back process is used to produce GaAs-on-insulator whose electrical quality is equal to that of bulk GaAs. Bonds created during rapid annealing are mechanically strong enough to withstand the mechanical and/or chemical thinning of the GaAs wafer to the desired thickness and subsequent device processing. >

Based on the site-binding model, the effects of two types of surface-sites (namely, silanol site and amine site) and their ratio on the characteristics of Si/sub 3/N/sub 4/-gate pH-ISFET are discussed. As the ratio /spl beta/ of silanol sites to amine sites is about 7/3, the maximum of the sensitivity of electrolyte-insulator (E-I) interfacial potential versus pH value, as well as of the range of linear response are theoretically obtained. The stability of pH-ISFET devices is partially determined by the total number of the two types of surface-sites and their ratio. The theoretical results are supported by experimental results.

For the fully depleted complementary buried-channel MOSFET (FD CBCMOS) discussed, although its operational principle is similar, its structure is different from that of the conventional buried-channel MOSFET in which a p-n junction exists at the surface of the channel region. Moreover, the p-n junction is totally eliminated in the device structure for both source and drain. Low interface charges in the silicon-on-insulator/silicon direct bonding (SOI/SDB) structure allow the fabrication of the FD CBCMOS. Numerical simulation and experimental measurement have demonstrated that no kink effect is present and that the device has the potential for VLSI applications due to the absence of the p-n junction and the superior SOI/SDB material quality. >

This paper presents a microfabrication technology for silicon capacitive tactile sensor arrays using SOI material produced by electric field-assisted silicon wafer direct bonding technology (SOI/SDB). Because of the great difference between the etch rates of Si and SiO 2 in KOH solution, the SiSiO 2 boundary in SOI material is employed as an etch stop. An excellent surface smoothness and better thickness controllability of silicon diaphragms are realized by this technique.

This paper presents a new process which permits the electrostatic bonding of GaAs to glass. The hydrogen plasma treatment of GaAs and glass is employed prior to the bonding. Auger electron spectroscopy (AES) has been used to study the properties of GaAs and glass before and after plasma treatment. Scanning electron microscopy (SEM) has been performed to view the interface cross-section image of the bonded GaAs/ glass. It is shown that the hydrogen plasma treatment appears to be effective in the electrostatic bonding of GaAs to glass.

X-ray optical elements (such as single-crystal silicon monochromators) illuminated with high-power synchrotron-radiation beams produced by insertion devices and, to a lesser extent bending magnets, require cooling, When operating a silicon crystal at room temperature, channels for the coolant are often fabricated directly beneath the diffracting surface. Then a separate silicon distribution manifold/plenum is manufactured, and the components are bonded together using an adhesive or some intermediate material. In many cases, such monochromators suffer from strains induced by the bond. A silicon-to-silicon direct-bonding technique (i.e., without any intermediate material) has been developed that appears to be an attractive method for creating a bond with less strain between two pieces of silicon. This technique is well understood for the case of thin wafers ({approximately}0.5 mm thickness) and is used by the semiconductor industry. Recently, bonding of 16-mm-thick 10-cm-diameter silicon crystals has been successfully performed inducing very little strain. A short review of the silicon-to-silicon crystals has been successfully performed inducing very little strain. A short review of the silicon-to-silicon direct-bonding process will be presented with an emphasis on its application to room temperature high-heat-load x-ray optics with the present status of direct bonding efforts at the APS.

One possibility of a low temperature joining techniques relies on the bonding of atomically clean surfaces. Results on the application of this method to silicon direct bonding are being presented. Clean surfaces for bonding were prepared by ex situ chemical cleaning with ensuing hydrogen passivation and their subsequent activation by thermal desorption of the hydrogen in ultrahigh vacuum (UHV). In UHV at room temperature, the wafers were gently brought into contact to initiate the bonding process. Without any subsequent heat treatment, the adhesive strength thus achieved was equivalent to the cohesion of bulk silicon: covalent bonds join the two crystals.

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

Room temperature covalent bonds between bonded silicon oxide layers can be realized by forming surface and subsurface absorption layers followed by terminating outmost bonding surfaces with desired bonding groups prior to bonding. For example, by introducing fluorine into bonding oxide layers and NH2 groups onto surfaces of bonding oxide layers before bonding, bonding energy equivalent to silicon fracture energy (2500mJ∕m2) has been realized at room temperature after storage in air. Fluorine incorporation causes Si–O–Si ring breaking leading to fluorinated oxide formation with lower density, thus facilitating a higher diffusion rate of polymerization by-products and enhanced moisture absorptivity. Results indicate that by-products of the polymerization reaction between NH2 groups on mating surfaces appear to be more easily diffused and dispersed away from the bonding interface by the low density fluorinated oxide than are polymerization by-products of OH groups. This enhanced by-product removal results in...

The orientation effect in GaAs MESFETs is related to the piezoelectric charge due to stress in overlayers. This brief describes an analytical method for the calculation of the piezoelectric charge in GaAs MESFETs on (100), (011), (1~1~1~)Ga, and (111)As substrates.

A novel method for the preparation of bonded and etch‐back silicon‐on‐insulator is presented and demonstrated in which the surface of the to be thinned silicon wafer near the oxide is biased to inversion, so the bulk of this silicon wafer can be removed by anodic etching using the depletion layer as an etch stop. The high etching selectivity between the bulk silicon wafer and the depletion layer makes it possible to produce a micron/submicron‐thick active silicon layer with good thickness uniformity across a 3 in. silicon‐on‐insulator wafer.

Silicon-on-insulator (SOI) was fabricated by wafer bonding using thermal SiO2 and trichloroethylene (TCE)-grown SiO2 as the buried oxides. Both the fixed charge density and the interface trap density at the back of silicon films on oxides were found to be appreciably lower for TCE-grown SiO2 than for dry-grown SiO2. The addition of TCE resulted also in significant increases of carrier lifetimes. The bonded SOI strength using TCE-grown SiO2 is comparable to that using dry-grown SiO2.

This paper presents a new explanation of the orientation effect of self-aligned WSix gate GaAs MESFET's by taking the different channel-substrate interfaces formed in the [011] and [011̄] directions due to the piezoelectric charges in GaAs MESFET's into account. The predicted results are in agreement with the measurement data.