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A simple expression for the threshold voltage of an IGFET is derived from a charge conservation principle which geometrically takes into account two-dimensional edge effects. The expression is derived for zero drain voltage and is valid for short and long-channel lengths. The dependence of the threshold voltage on the source and drain diffusion depth, r j , and channel length, L , is explicitly given. In the limit, L / r j → ∞, the threshold voltage equation reduces to the familiar expression for the long-channel case. The theory is compared with the measured threshold voltages on IGFET's fabricated with 1·4, 3·8 and 7·4 μm channel lengths. The dependence of the threshold voltage under backgate bias voltages ranging from zero to breakdown agrees closely with the theory.

The relationship between the threshold voltage shift of the n-channel Si-gate MOSFET and the implant dose of boron ions has been examined theoretically and experimentally when these ions are implanted with an energy of 60 keV through a gate oxide of 1200 A into a p-type silicon substrate of the acceptor concentration of 7 × 1014/cm3. The effect of high-temperature treatment after ion implantation on the threshold voltage shift has been considered. The good agreement between the theory and the experiment verifies that the model used is reasonable. The threshold voltage shift with the dose is expressed by about 5 × 10-12V.cm2below a dose of 5 × 1011ions/cm2. Above this value, the increase of the threshold voltage shift becomes slow and the slope takes the value of about 2 × 10-12V.cm2due to the maximum surface depletion layer.

Threshold voltage characteristics are presented for a double boron-ion-implanted n-channel enhancement MOSFET device for high speed logic circuit applications. A 15-Ω-cm high resistivity p-type (100) substrate was used to achieve low junction capacitance and low threshold substrate sensitivity. A shallow boron implant was used to raise the threshold voltage, and a second, deeper, boron implant was used to increase the punch-through voltage between the source and the drain. This design is especially beneficial for short channel devices, while maintaining the low junction capacitance and low threshold substrate sensitivity of the high resistivity substrate. A one-dimensional analysis was performed to predict the effects of ion implantation dose and energy on the device characteristics, and a quasi two-dimensional analysis was used to account for the short channel effect. The calculated results agree well with the behavior of experimental devices fabricated in the laboratory.

The sensitivity of double-diffused metal-oxide-semiconductor (D-MOS) transistor threshold voltage to fabrication process variations has been studied. Computed impurity profiles are used to study the process dependencies. For the double diffused process, the channel predeposition is shown to be the most critical step in threshold voltage control for long channel devices. Experimental results confirm this relationship. Process considerations appropriate for the fabrication of short channel D-MOS devices are also presented. Computed variations of threshold voltage with expected process tolerances for the channel predeposition are consistent with experimental results. Computer results show that for D-MOS deviceswith source junction depths of about 1 µm and channel lengths greater than 2 µm, threshold voltage can be controlled to ±20 percent using thermal diffusion and ±5 percent using ion implanted predeposition. Greater variation in threshold voltage is found for shorter channel lengths.

The static electrical characteristics below current saturation of MOSFET's with degenerate source and drain regions are calculated for operation at 0°K. The expression for current takes the same form as at room temperature although the flat-band voltage and the voltage across the depletion region at threshold are altered slightly. Potential hills occur in the channel if the gate does not overlap source and drain or if the oxide thickness is increased in the overlap regions. Although these barriers do not affect operation appreciably at room temperature, at 0°K a finite drain voltage (source-drain threshold voltage) is required to initiate conduction. This threshold voltage is included in the theory and the theory is compared with experimental results on p -channel enhancement mode MOSFET's at 4·2°K using hole mobility in the channel as a matching parameter. The channel hole mobility (assumed constant along the channel) is found to be relatively independent of gate voltage but to increase with increasing (negative) drain voltage. Values ranging between 500 and 1000 cm 2 /V-sec are deduced for drain voltages ranging from −1·2 V to −7 V. This compares to channel hole mobility values of 200–300 cm 2 /V-sec at room temperature. It is found that the channel width is on the order of 30–50 A—appreciably less than that at room temperature.

For short-channel insulated-gate field-effect transistors (IGFET) operating with source-to-substrate reverse bias, the threshold voltage is in general a function of channel length and drain-to-source voltage. It is shown in this analysis that these dependences can be attributed to the two-dimensional distribution of the depletion charges. Starting from two fundamental relations, the overall charge neutrality and the voltage relations based on the energy band diagram, a generalized threshold voltage equation in integral form is derived. A closed-form threshold equation is then obtained using a regional approximation with a simplified piecewise-linear depletion profile. The equation includes as new factors, the channel length, junction depth and drain voltage, and passes to the conventional form for increasing channel length. The theoretical threshold voltage expression is found to predict the correct tendencies and is shown to be in reasonable agreement with experimental measurements.

Oxidation of a boron doped silicon wafer reduces the surface concentration of boron due to segregation into the oxide. This in turn reduces the threshold voltage of an FET fabricated on such a wafer. This effect is calculated for realistic process types including a sequence of several oxidations at different temperatures. The threshold voltage is found to be reduced by about 1 V (1000 A oxide) which is quite considerable. The depletion effect on threshold voltage is expressed in terms of two parameters (effective doping and apparent surface charge). The approximations used can be adapted to most processes. Also, the effect of boron depletion on the MOS capacitance-voltage curve is calculated. An apparent flat-band voltage shift of only 0·1 V is found (1000 A oxide, 2 ohmcm).

The threshold voltage of the field regions of p-channel Si gate devices can be controllably increased by phosphorus ion implantation prior to field oxidation without any additional masking step. For a 1.25-µ field oxide thickness, an increase of more than 20 V in intermediate field threshold can be achieved without lowering junction breakdown voltage.

The threshold voltage of "normally off" Si-MESFET's for simple dc-coupled circuits is defined and computed with a two-dimensional device model, taking into account carrier velocity saturation and diffusion. The influence of the main parameters, gate length, conducting-layer thickness, and doping is investigated outside the range of Shockley's equations. A threshold voltage of a MESFET with a 1-µm gate length U_{T} = 0.2 V±10 percent requires a conducting-layer thickness tolerance d =0.15 µm±3 percent.

A shift in the gate threshold voltage of 7 to 9 times its initial value after irradiation with 2 to 6 x 1012 electrons/cm2 of 1.5 Mev electrons is observed for a p-channel enhancement type MOSFET. The effect has only been observed at gate biases greater than -20 V.

This paper discusses design considerations for short-channel ion-implanted MOSFET devices with relatively deep junctions. Four device parameters are considered: threshold and transconductance reduction, sub-threshold turn-on, and punch-through. Channel-length variations affect power and performance tolerances of enhancement/ depletion logic NOR gates in two ways: first, down-level current is inversely proportional to channel length; second, short-channel physical effects cause variations in transconductance and threshold voltage. It will be demonstrated that threshold and transconductance variations in short-channel devices tend to offset one another so their net contributions to tolerances on such circuit parameters as switching speed, down-level power and down-level voltage are negligible. Dual-energy ion implantation is used in the channel regions — a shallow implant to control threshold voltage, and a deep implant to control punch-through voltage. Hence high-resistivity (15 ohm-cm) substrates can be used to reduce junction capacitance. These implants are shown to have little effect on short-channel properties other than punch-through because the doses are low. Low channel doping and the relatively deep junctions contribute to a desirable, steep device turn-on characteristic. We concluded that short-channel effects do not have to be avoided in the design of small MOSFET devices. Using ion implantation and careful design, circuit tolerances can be maintained allowing parameters such as junction depth to be optimized for other criteria such as metallurgy compatibility.

P-channel enhancement mode MOS field effect transistors have been fabricated on high resistivity P-type (π) silicon substrates. A high off-state impedance can be achieved with zero gate voltage if the substrate resistivity is sufficiently high so that the P+π low-high junctions formed by the diffusion of the drain and source regions exhibit the desired rectifying characteristics. N-channel MOSFETs can also be fabricated on these high resistivity π substrates. While the N-channel devices usually exhibit depletion mode characteristics, both N and P-channel enhancement type MOSFETs can be simultaneously fabricated on a signal substrate if Al 2 O 3 -SiO 2 gate insulating layers are used and if Q SS is kept sufficiently small. The channel lengths must be sufficiently large to eliminate SCL current flow from drain to source with zero gate voltage. Off-state leakage currents on the order of nanoamperes have been observed for both units when the channel length was equal to 2 mils. By using techniques such as beam-lead interconnections or dielectric. isolation, complementary MOS integrated circuits can be fabricated on a single substrate and only two diffusions are required. Additional advantages of this approach include: extremely high carrier mobilities, very low threshold voltages for both units and negligible variation of MOSFET charac teristics with reverse substrate bias.

A memory element has been developed that has the structure of a typical silicon planar p-channel enhancement insulated-gate field-effect transistor (IGFET). The information is stored by setting the threshold voltage of the IGFET to a high or low value. Interrogation is accomplished by applying a gate voltage intermediate to the threshold voltage extremes. Current will flow between source and drain if the recorded threshold voltage is less negative than the interrogating gate voltage; none will flow if the recorded threshold voltage is more negative. A high (negative) threshold voltage is written by applying a pulse of -50 v or higher for a duration of 1 msec or less between gate and substrate. A low threshold voltage is similarly obtained with positive 50 v pulse. The persistence of stored information has been demonstrated for periods of at least several months.

Ion implantation of11B+directly into the channel region was used to adjust the threshold voltage of n-channel enhancement mode FETs. Implantation was performed through a 500A gate oxide grown during a standard four-mask FET process. Threshold voltage shift was determined as a function of implant dose and energy by measuring the difference in threshold voltage between implanted and unimplanted devices on the same wafer. Threshold voltage shift varied sublinearly with implant dose. These are believed to be the first results reported accurate enough to show this effect. Threshold voltage shift for a given dose is also reduced as implant energy (or channel depth) is increased. These results are easily understood in terms of a simple model in which the collapse of the depletion region at inversion, due to the additional doping in the channel, partially compensates for this additional doping. Data are compared with a numerical solution that for the first time fully accounts for the nonuniform doping profile, with excellent agreement.

The threshold vollage of an m.o.s. field-effect transistor is modulated by the source-to-substrate reverse bias. In the letter, the theory for long- and short-channel transistors is extended to include the influence of the channel width. The result is an analytical expression for the threshold voltage as a function of geometry and bias that agrees well with experimental data.

Even under the same implantation conditions, e.g., 50‐keV 11B+ ions implanted through 1100‐A gate oxides on 4‐Ω cm silicon substrates, the threshold voltage shift of n ‐channel MOS transistors is ∼55% of the shift of p ‐channel specimens, and deviation from linear dose dependence is observed for the n channel above a dose of 6×1011/cm2, while for a p ‐channel case the threshold voltage shift depends linearly on the net dose in silicon at least up to 1×1012/cm2. These results are discussed and explained with a calculated dose dependence that accounts for the large decrease of the maximum width of the depletion layer with increasing dose for acceptor‐implanted n ‐channel specimens.

The polarized memory effect (the memory in which switching between ON and OFF states depends on the polarity of the bias voltage) on the Se-SnO2 system is described. This effect is observed on the samples with Se films 300∼5000 Å in thickness. The ratio of the resistance of OFF state R O F F to that of ON state R O N is about three orders of magnitude. In the case of the film with thickness 103 Å, the threshold voltage from OFF to ON states V t h is 15 V, and the reverse voltage from ON to OFF states V r is 3.5 V.

A method of m.o.s.-transistor threshold-voltage measurement is described. The method is based on the measurement of the time interval between the pulse that releases the linear voltage ramp applied to the transistor gate, and the pulse of the transient current resulting from the channel formation. This method is particularly useful for investigation of threshold-voltage instabilities.