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This research aimed to develop best-practice recommendations for identifying the "standard of care" (SoC) and integrate it when it is the comparator in diagnostic economic models (SoC comparator). A multi-methods approach comprising 2 pragmatic literature reviews and 9 expert interviews was used. Experts rated their agreement with draft recommendations based on the authors' analysis of the reviews. These were refined iteratively to produce final recommendations. Fourteen best-practice recommendations are provided. Care pathway mapping (using quantitative, qualitative, or mixed-methods approaches) should be used for identifying the SoC comparator. Guidelines analysis can be integrated with expert opinion to identify pathway variability and discrepancies from clinical practice. For integrating the SoC comparator into the model, recommendations around structure, input sourcing, data aggregation and reporting, input uncertainty, and model variability are presented. For example, modelers should consider that the reference standard is not synonymous with the SoC, and the SoC may not be the only comparator. The comparator limitations should be discussed with clinical experts, but elicitation of its diagnostic accuracy is not recommended. Probabilistic sensitivity analysis is recommended when evaluating the overall input uncertainty, and deterministic sensitivity analysis is useful when there is high model uncertainty or SoC variability. Consensus could not be reached for some topics (eg, the role of real-world data, model averaging, and alternative model structures), but the reported discussions provide points for consideration. To our knowledge, this is the first guidance to support modelers when identifying and operationalizing the SoC comparator in diagnostic cost-effectiveness models. • Modeling the cost-effectiveness requires a comparison of the new diagnostic and patient management strategy with a comparator, often a complex standard of care (SoC) pathway. The new diagnostic test can replace or, more commonly, be integrated with the diagnostic SoC pathway. This presents 2 main challenges in obtaining useful estimates of cost-effectiveness: (1) identifying the diagnostic SoC pathway to define the comparator and (2) integrating it into the model. • We identified possible methodological approaches through pragmatic literature reviews and expert interviews. Some examples are to identify the SoC comparator via mapping the care pathway through qualitative, quantitative, or mixed-methods approaches; to select data on the diagnostic accuracy of the SoC comparator from studies in which the reference standard is the one used for the new test and report detailed information of the data source; and to assess the impact of the SoC pathway variability through scenario analysis. • We provide 14 recommendations that can support modelers to minimize the risk of a misrepresentation of the incremental clinical utility of the new diagnostic test because of the uncertainty and variability of the SoC comparator. We identified practice recommendations, gaps in knowledge, and areas where further research would advance the field. [ABSTRACT FROM AUTHOR]

Digital health definitions are abundant, but often lack clarity and precision. We aimed to develop a minimum information framework to define patient-facing digital health interventions (DHIs) for outcomes research. Definitions of digital-health-related terms (DHTs) were systematically reviewed, followed by a content analysis using frameworks, including PICOTS (population, intervention, comparator, outcome, timing, and setting), Shannon-Weaver Model of Communication, Agency for Healthcare Research and Quality Measures, and the World Health Organization's Classification of Digital Health Interventions. Subsequently, we conducted an online Delphi study to establish a minimum information framework, which was pilot tested by 5 experts using hypothetical examples. After screening 2610 records and 545 full-text articles, we identified 101 unique definitions of 67 secondary DHTs in 76 articles, resulting in 95 different patterns of concepts among the definitions. World Health Organization system (84.5%), message (75.7%), intervention (58.3%), and technology (52.4%) were the most frequently covered concepts. For the Delphi survey, we invited 47 members of the ISPOR Digital Health Special Interest Group, 18 of whom became the Delphi panel. The first, second, and third survey rounds were completed by 18, 11, and 10 respondents, respectively. After consolidating results, the PICOTS-ComTeC acronym emerged, involving 9 domains (population, intervention, comparator, outcome, timing, setting, communication, technology, and context) and 32 optional subcategories. Patient-facing DHIs can be specified using PICOTS-ComTeC that facilitates identification of appropriate interventions and comparators for a given decision. PICOTS-ComTeC is a flexible and versatile tool, intended to assist authors in designing and reporting primary studies and evidence syntheses, yielding actionable results for clinicians and other decision makers. • Abundant, yet vaguely defined definitions in digital health represent a challenge for clinicians, decision makers, developers, and researchers. Despite having several guidelines/checklists for the standardization of evidence generation and assessment for digital health interventions (DHIs), the identification of comparable DHIs remains difficult because of their personalized nature, complex technologies, and linkages to larger systems. This may restrict the validity of evidence syntheses. • We introduce the PICOTS-ComTeC (population, intervention, comparator, outcome, timing, setting, communication, technology, and context) framework, a newly developed, flexible, and versatile tool to help the formulation of sufficiently specific and detailed definitions for patient-facing digital health interventions and related research questions. • To overcome the limitations of terminology in digital health, the PICOTS-ComTeC framework of patient-facing DHIs should be specified in sufficient detail, to allow the identification of comparable interventions and allow for the selection of appropriate comparators that deliver similar effects to patients; therefore, the fit of DHIs in clinical, financing or development decision contexts, and specific research questions can be assessed. [ABSTRACT FROM AUTHOR]

Achieving low propagation delay in comparators under low input overdrive voltage is challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed comparator. By clamping the output node of the current summation circuit relative to a fixed level V C , the overdrive recovery time under large signal is successfully reduced. Moreover,by adopting a cascaded approach with multiple stages of high bandwidth and low gain,not only is the comparator's gain enhanced,but it also acquires higher bandwidth. Ultimately, the comparator's output is transmitted at high speed through an LVDS interface. This design is implemented using 0. 18 μ m SiGe BiCMOS technology. Simulation results show that the comparator has a static power consumption of 26.4 mW, and for 5 mV input overdrive, the average propagation delay is about 1.09 ns. • The input common-mode range is expanded to rail-to-rail. • The propagation delay under small input overdrive is greatly reduced. • The static power consumption of the comparator is 26.4 mW. • The comparator's output is transmitted at high speed through an LVDS interface. • The comparator is implemented using 0.18 μ m SiGe BiCMOS technology. [ABSTRACT FROM AUTHOR]

In this paper we study some fuzzy order in fuzzy sets based on t-norm fuzzy arithmetic. The definition of the order comes from the extension principle for interval order: a > b iff a − b > 0 and from measurement sciences. In measurement sciences the order is given by a comparator whose operation is based on empirical determination of the difference of two input signals. Fuzzy comparison based on fuzzy sets subtraction is considered as an extension of substraction operation, namely a fuzzy set B is greater than a fuzzy set A if B − A is greater than zero in fuzzy arithmetic. In the paper we show that this fuzzy order is irreflexive, transitive, asymmetric and compact, subhomothetic, Archimedean and semi-Ferrers. Our idea refers to the work of M. K. Urbański (Modeling the measurement in algebraic fuzzy structures, Warsaw 2003, in polish) and to the fundamental problems in the measurement theory. [ABSTRACT FROM AUTHOR]

We present a highly robust 12-bit, 100 kS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) that excels in mitigating the effects of mismatch, temperature variations and process corners. A modified hybrid switching method is developed in design of the Capacitive Digital-to-Analog Converter (C-DAC) that saves 17 % of the DAC power consumption. Furthermore, we utilize a switched local feedback loop in the pre-amplifier circuit of the comparator that significantly minimizes the offset. Using this technique, the 3-sigma offset is reduced from 11.33 mV to 0.37 mV. Moreover, a high performance latched-based Bit Slice Unit (BSU) is proposed to preserve the successive codes during each conversion. Designed in 65 nm CMOS technology, the ADC operates in −55 °C to +125 °C temperature range, consuming only 1.55 μW with a 0.7V supply voltage and occupying a 0.6 mm2 area. [ABSTRACT FROM AUTHOR]

A dynamic comparator is the core element in high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. The majority of the dynamic comparators can only operate at high speeds when the input difference voltage is large enough. Due to the limited pre-amplifier gain, the comparators' performance deteriorates at lower input difference voltages, which is not suitable for high-speed, high-resolution ADCs. A double-tail dynamic comparator with a pair of auxiliary inverters is proposed to alleviate this problem. With the proposed comparator, the pre-amplifier's differential gain is increased, and the latch regeneration time is reduced by the auxiliary inverter pair resulting in faster comparison operations. The proposed comparator is designed, simulated, and compared with the latest topologies in 65 nm CMOS technology. The performance metrics such as delay, kickback noise, energy consumption per bit, rms noise, and power delay product are evaluated and compared with the state-of-the-art architectures. The proposed technique can be applied to any dynamic comparator that has differential signals at the output of the pre-amplifier stage. Simulations show that the auxiliary inverter pair improves the comparator's speed by more than 10%. [ABSTRACT FROM AUTHOR]

This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 % compared with conventional one without extra reference voltage (V CM ). Gain tunable voltage-controlled delay unit (GT-VCDU) is proposed for offset calibration of time-domain comparator (TD-CMP). The residual offset is reduced by proposed stage-by-stage calibration. 1 sigma of TD-CMP offset is reduced to 0.8 mV. The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038 m m 2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this paper, a low-power, small-area SAR-VCO ADC is proposed using a highly linear and single-path differential VCO-based quantizer. Compared to conventional digital solution or analog design, proposed digital synthesizable dynamic voltage comparator (DVC) employs a two-stage structure, which reduces the comparator delay and offset and saves chip area. Furthermore, improved differential voltage-to-current (V–I) converter enables the realization of a single-path differential VCO-based quantizer. Trimming circuits enhance the robustness of VCO, compensating for variations induced by process variations. Additionally, a novel frequency-to-digital converter (FDC) is used as the fine quantization to directly measure the frequency. Finally, a SAR-VCO ADC is realized in 65 nm CMOS process. The simulation results show that the signal-to-noise distortion ratio (SNDR) is 70.16 dB under sampling rate of 7.8 MHz at oversampling rate (OSR) of 8. The proposed ADC has a supply voltage of 1.2V and a power consumption of 405 μW. It occupies an area of 0.16 mm2, and achieves an area figure of merit (FoM A) of 25.12 fJ*mm2/conversion-step. [ABSTRACT FROM AUTHOR]

Heated tobacco products (HTPs) are non-combustible, inhaled tobacco products that generate an aerosol with fewer and lower levels of toxicants, with a potential to reduce risk relative to cigarette smoking. Here, we assessed in vitro toxicological effects of three menthol (glo neo neoCLICK, neo Smooth Menthol and Fresh Menthol) and one non-menthol (neo Smooth Tobacco) variants of glo HTP, along with market comparators for cigarettes and HTPs. Limited chemical characterization of the study products revealed significantly lower levels of acetaldehyde, acrolein, crotanaldehyde and formaldehyde in test samples from HTPs than those from cigarettes. The glo HTPs were non-mutagenic in the bacterial reverse mutagenesis assay. Although, the whole aerosol exposures of glo HTPs were classified as genotoxic in the in vitro micronucleus assay, and cytotoxic in the NRU (monolayer) and MTT (3 dimensional EpiAirway™ tissues) assays, the cigarette comparators were the most toxic study products in each of these assessments. Further, glo HTPs elicited oxidative stress responses only at the highest dose tested, whereas the cigarette comparators were potent inducers of oxidative stress at substantially lower doses in the EpiAirway tissues. The comparator (non-glo) HTP results were similar to the glo HTPs in these assays. Thus, the glo HTPs exhibit substantially lower toxicity compared to cigarettes. [ABSTRACT FROM AUTHOR]

This paper proposes an Active Rectifier for low-frequency vibration piezoelectric (PZE) energy harvesting of Autonomous Underwater Vehicle (AUV). By using the cross-coupled NMOS transistors and active driven PMOS transistor, the turned-on resistance across the transistors could be minimized such that the voltage conversion efficiency is improved. Besides, the problem of the reverse current is avoided. Moreover, the novel self-biased low power comparator operated in subthreshold region is employed to reduce the power consumption. Only 6 MOS transistors and 1 resistor are required in the proposed self-biased comparator. The proposed design is implemented with a 0. 18 μ m HV process. Based on the measurement results, the peak voltage conversion efficiency (VCE) and the peak power conversion efficiency (PCE) are 97.63% and 96.26%, respectively, at 50 K Ω loads and 20 Hz vibration frequency. The maximum output power is 14.1 mW with the load of 1 K Ω. [ABSTRACT FROM AUTHOR]

• Periodic-threshold amalgamated quasi-one-junction SQUID comparator enhances sensitivity via magnetic control. • Flux-biased Josephson-junction SQUID obtains low hysteresis constant by suppressing effective critical current. • A 30 GS/s sampling rate and 9 dB sensitivity enhancement have been verified in the simulation. • 2-bit operation and performance metrics have been confirmed through the chip fabricated by the SIMIT Nb03 process. This article proposes a periodic-threshold superconductive comparator named amalgamated quasi-one-junction SQUID comparator (AQOS) for sensitivity enhancement. The comparator employs a pair of compound Josephson-junction SQUID with magnetically-controlled effective critical current in quantization to relieve the constraints on the period current without disrupting the non-hysteresis operation state. As a result, the AQOS comparator can achieve three times more comparing operations than the quasi-one-junction SQUID (QOS) comparators, corresponding to a 9 dB sensitivity improvement. The AQOS comparator also adopts the complementary structure and feedback-free topology for linearity and robustness. It can reach a 30 GS/s sampling rate, 0.5 mA period current, −25 dBm sensitivity, more than ±10 % bias current margin, deviation of quantization current peak-to-peak magnitude that is about 10 % of the mean, and the 4.4 dB average DC duty bias margin in simulation from 1 GHz to 30 GHz with a process of 6 kA/cm2 Josephson critical current density. A 2-bit AQOS comparator has been fabricated with the SIMIT Nb03 process for the qualification test. It has passed functional tests at low frequency, and its performance metrics, including period current, sensitivity, and bias current margin, have also been proven. [ABSTRACT FROM AUTHOR]

In this paper, an area-and-energy-efficient 10-bit single-ended (SE) counter-type (CT) analog-to-digital converter (ADC) with dual 5-bit capacitive digital-to-analog converter (DAC) arrays and dual 5-bit counters is presented. The 10-bit capacitive-DAC (CDAC) array and counter of the conventional counter-type structure are divided into two 5-bit CDAC arrays and counters, respectively. Significant improvements are achieved in comparison to the conventional counter-type ADC as follows: the capacitance of the most-significant-bit (MSB) capacitor is reduced by 96.88 % from 512C to 16C; the total capacitors are reduced by 93.75 % from 1024C to 64C; the total clock cycles required in the conversion phase are reduced by 93.94 % from 1023 to 62; the average switching energy is reduced by 98.55 % from 2390CV2 to 35CV2. The proposed ADC occupies a smaller area, performs much faster, and its power consumption is greatly reduced. This structure has a simple design with small sampling capacitor (32C) and does not require a rail-to-rail comparator compared to SAR ADCs. It is suitable for biomedical and multi-channel applications. The proposed ADC is post-layout simulated in 65-nm CMOS technology which occupies 0.016 mm2 area. This ADC has 85.43 nW power consumption, 9.64 ENOB on 33.33 kS/s sampling rate, and 3.23 fJ/conversion-step FOM. [ABSTRACT FROM AUTHOR]

This paper presents a high-speed low-power cryogenic CMOS two-stage dynamic comparator for SAR ADC. The pre-amplifier uses the dynamic bias technique to save power. To increase the output voltage difference of the pre-amplifier, the StrongARM latch is inserted. The proposed latch keeps a cross-coupled inverter to ensure good positive feedback. The tail current source of the proposed latch is replaced by the input pair to suppress the through current. The auxiliary input pair enhances the gain and positive feedback to speed up the latch. The paper also presents a delay analysis of the dynamic bias technique, which gives a deep understanding and a good intuition for circuit design. The simulation results demonstrate the proposed comparator achieved a CLK-Q delay of 162.1 ps and 295.4 ps at V i d = 1 mV and V C M = 0.7 V with V D D = 1.2 V and f s = 1 GHz in 300 K and 4K. The energy per comparison is 34.04 fJ and 27.75 fJ. [ABSTRACT FROM AUTHOR]