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In the field of paper conservation and archival research, identifying the raw materials of paper is important to elucidate its history and culture. As the most basic element of the raw materials for paper, fibers have not been sufficiently investigated. In this study, we propose a nondestructive method for estimating paper fibers from macro photographs ( $4000\times3000$ pixels) captured using a digital camera. The proposed method consists of background patch (500 pixels per side) detection (BPD), wherein background regions with no text are identified; patch fiber classification (PFC), wherein background patches obtained after BPD are analyzed for fiber classification; and paper fiber estimation (PFE), wherein macro images obtained after PFC are analyzed for fiber estimation. BPD and PFC are employed to perform patch-based classification on segmented macro images, which are reconstructed during PFE to obtain the final fiber estimation results. We performed experiments using 1337 macro images (64176 patches) to evaluate the fiber estimation accuracy for kozo, mitsumata, and gampi via three-fold cross-validation. The average fiber classification accuracy for patch images was observed to be 79.1%; accordingly, the average fiber estimation accuracy for macro images was 85.8%. Experimental results indicated that PFE can be realized in a nondestructive manner on macro images of paper captured using a digital camera.

Computer scientists often publish their source code accompanying their publications, prominently using code repositories across various domains. Despite the concurrent existence of scholarly articles and their associated official code repositories, explicit references linking the two are often missing. Traditionally, identifying whether scholarly content and code repositories pertain to the same research project requires manual inspection, a time-consuming task. This paper proposes a deep learning-based algorithm for automatically matching scholarly articles with their corresponding official code repositories. Our findings indicate that the most common linking information includes the paper title and BibTeX entries, typically found in the repository’s readme document. In this study, we employed SPECTER for vector embedding of paper and repository metadata. Utilizing these embedding representations with the Light Gradient Boosting Machine (LGBM), our method achieved an F1 score of 0.94. Moreover, combining our best model with a rule-based approach improved performance by 5.31%. This study successfully delineates a connection between academic papers and associated official code repositories, minimizing reliance on explicit bibliographic information in repositories.

In the era of Industry 4.0, digital transformation has spurred the swift advancement of technologies, including intelligent predictive maintenance scheduling, prognostics and health management. The accurate prediction of remaining useful life plays a crucial role in these technologies as it extends power equipment’s safe operational duration and decreases the maintenance costs associated with unforeseen shutdowns. Also, the increased accessibility of data for monitoring system conditions has paved the way for the more immense adoption of machine learning models in prognostics and health management for power transformers. At the moment, with the ever-increasing demand for electricity, there is a corresponding increase in the degradation processes of power transformers. Transformers insulation system and more importantly, the paper insulation happens to be the principal part where the degradation is prominent. Therefore, an accurate prediction of the insulating paper condition through its degree of polymerization is required to guarantee the reliability of power transformers. In this regard, the predictions, reliability, and health monitoring of this power equipment can be actualized by modeling the degradation of transformer insulation paper through several machine learning frameworks. In this view, this review paper has been drafted not only to serve as a guide for researchers interested in the fields of transformer insulation system fault prognosis but also to offer insights into potential research directions as existing literature in modeling and evaluating transformer paper insulation is presented.

Evaluating the long-term influence of academic papers in the early stage after publication is crucial for research management and decision-making. Although the total number of citations has been considered as a valid indicator to measure the academic influence of papers, there are still some bottleneck problems in predicting future citation counts. Firstly, it remains a challenging task to select the reasonable features due to the diversity of model features. Secondly, some prediction models are overly complex and their defects may cause prediction bias or even errors. Finally, the most important thing is that very few models possess long-term predictive ability. This paper proposes a prediction model that can provide an early evaluation of the long-term citations, or the long-term influence, of academic papers. The model uses features available immediately after publication or after a certain period of time. Taking academic papers in Information Science and Library Science as our experimental subject, we train the model using three machine learning algorithms and find that the artificial neural network performs satisfactorily. Our findings may offer guidance for research management and decision-making.

This special section of the IEEE Open Journal of Circuits and Systems (OJCAS) aims to highlight a selection of papers from 2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). Due to COVID-19 and travel restrictions, APCCAS 2022 was organised as a hybrid conference during 11 - 13 November 2022 in Shenzhen China. As the regional flagship conference of IEEE Circuits and Systems Society, APCCAS 2022 was driven by the theme “Building a Fully-connected AIoT World” to emphasize the CAS Society’s potential for finding multidisciplinary solutions to societal and industrial challenges. The papers in this special issue were selected from a comprehensive list of papers presented in the sessions of APCCAS 2022.

The Editorial Board of the IEEE Open Access Journal of Power and Energy (OAJPE) would like to recognize the following best papers selected from all papers published between October 1, 2020 and September 30, 2023 in OAJPE.

Digital Object Identifier 10.1109/ TSM. 2024.3411140Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. [Extracted from the article]

Digital Object Identifier 10.1109/ TSM. 2024.3442019Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. [Extracted from the article]

The article titled "Call for Papers: IEEE ETHICS-2025" discusses the theme of the 2025 IEEE ETHICS conference, which is "Emerging Technologies, Ethics, and Social Justice." The conference aims to explore various topics related to the ethical and social implications of emerging technologies, such as automation, AI ethics, social innovation, and the future of work. It also highlights the connection between emerging technologies and UN Sustainable Development Goals, as well as the importance of teaching AI ethics. The article provides information on the submission deadline for papers and poster abstracts. [Extracted from the article]

Welcome to Volume 4 of IEEE Journal of Microwaves! In this issue, we bring you 11 quality papers: two invited and nine regular submissions. We also celebrate six of our Outstanding Reviewers of 2023 and announce our IEEE Journal of Microwaves 2022 Best Paper prize. Our author and reader pools continue to expand and our usage counts per article published now exceed 1530. All of our 232 published articles from 2021 to 2023 now appear on Clarivate's Web of Science and we are looking forward to possibly receiving an impact factor this July. Remember to take a look at our solicitation for papers that can fit into our Microwaves in Climate Change special issue, which we intend to release before the end of 2024.

This research proposes an inkjet printed dual-band dual-sense circularly polarized antenna using CPW-feeding on PET substrate. The antenna is designed and optimized using ANSYS HFSS, which operates at 4.01 GHz - 5.05 GHz (22.96%) and 6.23 GHz - 7.58 GHz (19.55%) with a return loss of $0.44\lambda $ x $0.52\lambda $ x $0.002\lambda $ , where $\lambda $ is the free-space wavelength at the lowest circular polarization frequency. Measurement of the fabricated version shows good agreement with the simulated version. To the best of author’s knowledge, this proposed design is the first circularly polarized antenna integrating flexibility with dual-band and dual-sensing characteristics.

The article announces the IEEE International Symposium on Technology and Society, scheduled from September 18-20 in Puebla, Mexico, focusing on the Social Implications of Artificial Intelligence (AI), inviting submissions from academia, industry, and government to explore AI's impacts.

As this Special Section goes to publication, semiconductor manufacturing in the United Status, and globally, continues to expand at a seemingly torrid pace. Assisted by government funding and driven in part by artificial intelligence workloads that gobble up increasing amounts of data center computing capacity, Intel and TSMC fabs are going up in Arizona, TI and Samsung fabs are coming to Texas, and Micron has big plans in New York. Unfortunately, just like those flying cars we were once promised, AI has not yet eliminated the need for the skilled trades and engineers required to build and successfully operate a fab. As a result, workforce development has become an important part of the increasingly complex semiconductor manufacturing process: Where are the thousands of engineers the semiconductor industry needs to staff these new fabs going to come from? How can we make more students excited about science and engineering? While the Guest Editors don’t have all the answers, we are happy that ASMC contributes to the solution by actively supporting student presentations and posters and annually recognizing the best student paper of the conference. And, maybe some day, the artificial intelligence systems that semiconductor manufacturing has enabled will give us those Star Wars or Star Trek robots that can build fabs and make chips too. [ABSTRACT FROM AUTHOR]

The semiconductor industry faces increasing pressure to improve energy efficiency while maintaining competitiveness and sustainability. Apart from more conventional energy efficiency measures look at equipment modernization and process and design optimization, this paper explores the potential of data-driven approaches to address these challenges and optimize energy consumption across both the facility and manufacturing space of a semiconductor manufacture plant. By harnessing advanced analytics, machine learning algorithms, and IoT technologies, semiconductor manufacturers can gain real-time insights into energy usage patterns, and identify areas of opportunities that leads to the implementation of targeted interventions to optimize performance. The paper first looks into the challenges and measures of enabling and enhancing data visibility which is the foundation of the data-driven approach, then it examines case studies, best practices and various systematic approaches, demonstrating the transformative impact of data-driven energy efficiency measures which leads to operational efficiency, cost reduction, and environmental sustainability. Ultimately, this paper aims to provide a fresh angle into the energy efficiency study for peers in semiconductor industries to leverage in their journey towards a more sustainable and energy efficient future. [ABSTRACT FROM AUTHOR]

Computational simulation has been used in the semiconductor industry since the 1950s to provide engineers and managers with a faster, more cost-effective method of designing semiconductors. With increased pressure in the semiconductor industry to move towards greener and more sustainable manufacturing, it is crucial to understand the impact of computational simulation and artificial intelligence on environmental sustainability, specifically reducing greenhouse gas (GHG) emissions. This paper quantifies the degree to which various types of simulation used for hardware, process, and device optimization can be adopted for different applications in wafer fabrication equipment research and development, along with the potential reduction in physical experimentation, saving silicon, gases, chemicals, and wafers. With this understanding and an estimation of the equivalent carbon cost impact of the computation itself, analyzed projects demonstrated a significant (>80%) decrease in emissions, primarily driven by the ability to use fewer patterned and blanket wafers whose carbon footprint appears to be orders of magnitude larger than that of used modeling resources. The paper concludes with an attempt to quantify the environmental savings from virtualization across our entire research organization and to illustrate the potential future impact of described activities. [ABSTRACT FROM AUTHOR]

The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods. [ABSTRACT FROM AUTHOR]

The document is the table of contents for the February 2024 issue of IEEE Transactions on Semiconductor Manufacturing. It includes editorials, regular issue papers, and announcements. The regular issue papers focus on topics such as energy-aware scheduling, adaptive photolithography scheduling, integrated scheduling, gas-delivery fluid-mechanical timescales, machine learning on optical metrology, yield modeling, and more. The document also includes announcements for joint call for papers and a call for papers for other IEEE transactions. [Extracted from the article]

Plasma Dry-Etch (DE) is one of the key unit-operations in semiconductor manufacturing that use greenhouse gases (GHG) as feed gas (Donnelly and Kornblit, 2013). The exhaust GHG emission reduction or mitigation is one of the main focuses of scope 1 emission reduction at Micron Technology Inc. The reduction and mitigation approaches have been strategized in focus-tiers in order of proximity to the source of emissions. The focus-tiers upstream of exhaust are avoidance, replacement, reduction and downstream of exhaust are recovery/capture/recycle, abatement. This paper focuses on the replacement focus-tier that pertains to replacing high-emission feed gases (HE gas, feedgas that will produce relatively high kgCO2e through exhaust) with relatively low-emission feed gases (LE gas, feedgas that will produce relatively low kgCO2e through exhaust). The paper presents replacement opportunities and challenges through an evaluation study of Carbonyl Floride (COF2) as a replacement gas for NF3 or CF4 as a DE in-situ plasma chamber cleans gas. In conclusion, direct emissions from DE chamber cleans can be lowered by replacing NF3 and CF4 GHGs with COF2 by 90% or more. However, this replacement would require additional safety measures and abatement in operations due to increased toxicity and reactivity of COF2, along with cost roadmap to make its adoption economically feasible. Similar and possibly additional challenges would arise with other replacement options. To overcome challenges in replacement strategy focus-tier, it will require strong industry level collaboration between chemical suppliers, original equipment manufacturers (OEMs), device manufacturers, semiconductor research and collaboration centers and university research groups. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to outline the path that Intel has been taking to drive sustainable semiconductor manufacturing processes. As new sites are built to deliver Intel’s Design & Manufacturing (IDM) 2.0 strategy, we expand and grow our manufacturing output and facilities scope. To minimize environmental impact, there was focus on chemical and water usage reduction, chemical reuse, improvement of Destruction Removal Efficiencies (DRE), abatement of hazardous by-products, & innovation of novel Point of Use (POU) systems. There is also commitment to replacing fossil fuel with electrically driven alternatives and/or renewable natural gas. There has been a collective approach in the decarbonization methodology for all manufacturing emissions through technology-based innovations to reduce climate impact in global manufacturing. Intel also engages with suppliers and customers with a focus on reducing waste and wastewater emissions by leveraging technology to reduce environmental impacts on global manufacturing. There has been a focus on enabling greener circular economy strategies across the industry value chain by transforming its chemical footprint methodology. Collaboration with others to lead the way in the semiconductor sector has led to accelerating progress on reducing climate impact by advancing sustainable and green chemistry use. Intel strives to achieve renewable energy use and energy conservation across its global manufacturing operations, along with maximizing water conservation and implementing novel technologies to drive reduction in greenhouse gases. [ABSTRACT FROM AUTHOR]

Sustainability and semiconductor manufacturing are linked in ways that may not be visible to experts in either area; this opacity is slowly fading with the surge of corporate commitments toward net-zero carbon emissions by 2050. In 2023, imec released a model (imec.netzero) to quantify the environmental impact of manufacturing integrated circuits (ICs). In this paper, the emissions trends are used to create an understanding of the processes that contribute. Lithography - both 193nm (DUV) and 13.5 nm (EUV) - has a large role to play in changing the overall emissions of IC chip manufacturing. Methods for reducing the emissions associated with lithography include design and process choices that maximize throughput and tool operational choices to reduce consumption. Low-emissions behaviors in manufacturing can be promoted once their potential benefit has been quantified. Engineers are well-accustomed to optimizing for performance; we must now optimize for lower emissions in parallel. [ABSTRACT FROM AUTHOR]

Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability. [ABSTRACT FROM AUTHOR]

Chemical mechanical planarization (CMP) is vital for ensuring chip fabrication uniformity at nanometer scales. The emergence of a series of phenomenological CMP process models (Stine et al., 1997; Gbondo-Tugbawa, 2002; Xie, 2007; Vasilev, 2011) suggests that the existing model upgrade approach is largely based on a change in phenomenological model assumptions, demanding deep insights into complex process mechanisms and protracted period for accuracy improvements. To tackle this issue, this paper proposes a decoupling regression strategy for model upgrades. This strategy employs a data-driven approach to enhance the coupling relationships within the model, facilitating continuous improvement of simulation accuracy based on the existing model. It is capable of achieving improvements in model accuracy even in scenarios where modelers lack insight into complex process mechanisms. We validate our method by upgrading the Density Step Height (DSH) model to the Extend-DSH model to address poor erosion predictions at the 28nm node. Comparing model predictions with silicon data reveals that the Extend-DSH model aligns better with the measured data, reducing the root mean square error from 159.31Å to 6.89Å and increasing the coefficient of determination from -0.83561 to 0.6058, showcasing the effectiveness of the proposed chip-level CMP model upgrade method grounded in the decoupling regression strategy. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method for Virtual Metrology (VM) in plasma etch processes based on analysis of all time and wavelength samples of Optical Emission Spectroscopy (OES) signals. The new method flattens each OES signal into a single vector, after which Singular Value Decomposition (SVD) is performed on the matrix formed by vectors of flattened OES signals in the training dataset. Low rank SVD projections of flattened and standardized OES recordings served as inputs for Ridge Regression, Artificial Neural Network, and Random Forest based VM models. A VM study is then conducted on a dataset gathered from a major 300 mm wafer fabrication facility, showing that the use of newly proposed SVD-based OES features consistently outperformed benchmark VM model features. Additional analysis of feature importance performed based on the analytically tractable Ridge Regression VM model form demonstrated distinct time-frequency patterns of OES signal portions that were highly informative for prediction of relevant Critical Dimensions, clearly justifying the need to use the entire OES signals for VM. [ABSTRACT FROM AUTHOR]

The article is an editorial from the IEEE Transactions on Semiconductor Manufacturing journal. It congratulates Sewon Park, Kyeongwon Lee, Da-Eun Jeong, Heung-Kook Ko, and Jaeyong Lee for their paper on Bayesian nonparametric classification for incomplete data in semiconductor manufacturing. The paper proposes using the Dirichlet Process - Naive Bayes model to impute missing values and address classification problems. The article also mentions two other papers that received honorable mentions. The editorial board encourages authors to submit their papers for review and emphasizes the importance of design, modeling, and process control in semiconductor manufacturing. [Extracted from the article]

The document is the table of contents for the August 2024 issue of the IEEE Transactions on Semiconductor Manufacturing. It includes a special section on the 2023 Advanced Semiconductor Manufacturing Conference, as well as regular issue papers on topics such as wafer-scale 3D integration, chemical uniformity impacts on electrodeposition, and thermal study of polymers for microelectronics. The document also includes letters and announcements, such as calls for papers and nominations for awards. [Extracted from the article]

The "IEEE Transactions on Semiconductor Manufacturing" is a journal that publishes the latest advancements in the manufacturing of microelectronic and photonic components. It aims to enhance knowledge and improve manufacturing practices in the semiconductor industry. The journal covers various topics such as process integration, manufacturing equipment performance, yield analysis, metrology, and supply chain management. Papers submitted to the journal should focus on practical engineering techniques for solving manufacturing-related problems. The journal follows a peer review process and encourages authors from low-income countries to submit their work. The standard length for regular papers is eight pages, with longer manuscripts incurring additional charges. The journal also accepts short communications in the form of letters. Authors are required to follow specific style guidelines for manuscripts and illustrations. The review process takes an average of four to six weeks, and the reviewers' comments are confidential. The journal also accepts graphical abstracts and electronic supplements. Authors are responsible for preparing a publication-quality manuscript and may seek English language editing services. Plagiarism is strictly prohibited, and manuscripts found to have plagiarized content may be penalized. All authors are required to have an Open Researcher and Contributor ID (ORCID). The journal offers both traditional and open access publication options, with associated fees. Native language author names are supported, and page charges may apply. The IEEE owns the copyright to the published material. [Extracted from the article]

In semiconductor manufacturing, defect detection is pivotal for enhancing productivity and yield. This paper introduces a novel weakly supervised method, the Implicit Cross Domain Diffusion Model (ICDDM), designed to tackle defect pattern segmentation challenges in the absence of detailed pixel-wise annotations. ICDDM employs a generative model to estimate the joint distribution of images depicting defect patterns and background circuits, formulating this estimation as a Markov Chain and optimizing it through denoising score matching. Building on this, we propose the Cross Domain Latent Diffusion Model (CDLDM), inspired by the Latent Diffusion Model, which simplifies the diffusion process into a lower-dimensional latent space to boost detection efficiency. Further enhancing our model, we introduce the Knowledge Distillation Cross Domain Diffusion Model (KDCDDM), which utilizes CDLDM as a teacher model and a Generative Adversarial Network (GAN) as a student model. This approach significantly accelerates the diffusion process by reducing the number of necessary denoising iterations while maintaining robust model performance. This suite of techniques offers a comprehensive solution for efficient and effective defect detection in semiconductor production environments. [ABSTRACT FROM AUTHOR]

The impact of human activity on the environment is well documented. While citizens and responsible leaders aim at a more sustainable future, it is our duty as industrial companies to examine our products portfolio from its life cycle perspective. A promising approach is to use sustainable manufacturing technologies, that minimize negative environmental impact, while boosting the product benefits towards decarbonization objectives. This paper enriches our earlier description (Nicoleau et al., 2023) of STMicroelectronics approach in developing sustainable technologies. It starts by examining the global context while putting in perspective the definition of responsible products. Then we will go through the different phases of the product lifecycle by illustrating the involved processes during technology development and product manufacturing. And we will complete our Life Cycle Assessment methodology by illustrating the efforts in striving to reduce our ecological footprint towards our ambition of carbon neutrality by 2027. [ABSTRACT FROM AUTHOR]

Recent legislation concerning the potential regulation of per- and polyfluorinated chemistries as a class (PFAS) has enormous implications for the field of semiconductor manufacturing. This is so because the material foundation of silicon and its dielectrics which prevails across all advanced device technologies dictates the usage of fluorocarbon gases, particularly for subtractive patterning and chamber cleaning processes. Simultaneously, recent progresses in artificial intelligence have spurred large investments in fabrication plants to produce the critical hardware driving that field. As these trends stand in clear opposition to each other, it is increasingly important for synergy between research fields to center sustainability as a key parameter of technological development. The first critical step for such research efforts involves improved characterization of the fluorinated byproducts created in such manufacturing processes. The use of low-temperature plasma discharges tremendously increases the complexity of the available reaction pathways, making this task significantly more challenging. In this paper we present a novel technical analysis method applied to the fluorocarbon polymerization remaining on through-silicon via sidewalls patterned using the Bosch Process. Fluorinated carbon fragments with longer chain lengths than the starting gas precursor molecule were detected, which represents to the best of our knowledge the first time this has been reported in literature. This baseline will be invaluable in future research efforts to assess novel chemistries and abatement treatments. [ABSTRACT FROM AUTHOR]

Digital twins of the semiconductor fabrication process provide means for optimization of the physical layout and nanofabrication process design, studying compatibility between desired structures and a process flow, and a pathway to analyze the root causes of defects for state-of-the-art CMOS and MEMS devices. In this paper, a metric for the geometric differences between structures visualized by CD-SEM images is defined, and a computer-vision-based algorithm is developed to evaluate the metric. One of the major uses of such metrics is to compare experimental and simulated images. For this application, numerical results are presented when the simulator is SEMulator3D®, a physics-based process modeling software system for semiconductor and MEMS devices. Computer vision tools, such as filters, thresholding, and morphology operations, are used to extract geometric features from CD-SEM images and pattern matching and symmetric difference are used to compute the metric. Examples of using the metrics to quantify the geometric similarity between a simulated nanostructure and an experimental CD-SEM image of the fabricated nanostructure are presented. The data consists of eight classes of nanostructures which are defined, fabricated in the cleanroom with 36 combinations of layout parameters, and imaged with a CD-SEM. [ABSTRACT FROM AUTHOR]

The bottom-up assessment of environmental impact of the fabrication of integrated circuit chips relies on accurate modeling of the operation of a high-volume semiconductor fab. In our virtual fab model, we structure fab operation in three concentric sectors: the wafer processing equipment, the generation of utilities that feeds the equipment, and the fab infrastructure that provides a suitable environment for the equipment and the workers. In this paper, we first address the correlation between process flow, wafer demand and fab dimension, which sets the scale of the virtual fab and enables global fab energy consumption estimates. Next, we describe how energy consumption calculations are performed sector-by-sector and how these evolve over the deployment of successive generations of logic nodes. In particular, we propose an original bottom-up model for fab infrastructure energy consumption that takes into account local climate dependence of a fab’s geographical location. The essence of these learnings is condensed into a normalized power consumption per manufacturing area (in kW/m2) that is deduced from our models as a function of technology maturity and location. These values form a good comparison basis with data from industry and literature. [ABSTRACT FROM AUTHOR]

This paper studies simultaneous scheduling of production and material transfer that arises in the semiconductor photolithography area. In particular, the right reticle and right job both need to be present to process the job. Jobs are transferred by a material handling system that employees a fleet of vehicles. Reticles serving as an auxiliary resource are also transferred from one place to another by a different set of vehicles. This intricate scheduling challenge, encompassing jobs, reticles, machines, and two distinct sets of vehicles, is explored here for the first time. The paper introduces a multi-stage methodology that involves relaxation, a constructive heuristic, constraint programming, and a warm-start approach to address this complex problem. [ABSTRACT FROM AUTHOR]

A scheduling problem for parallel batch processing machines (BPMs) with jobs having unequal ready times in semiconductor wafer fabrication facilities (wafer fabs) is studied in this paper. A blended objective function combining the total weighted tardiness (TWT) and the total electricity cost (TEC) under a time-of-use (TOU) tariff is considered. A genetic programming (GP) procedure is designed to automatically discover priority indices for a heuristic scheduling framework. Results of computational experiments are reported that demonstrate that the learned priority indices lead to high-quality schedules in a short amount of computing time. [ABSTRACT FROM AUTHOR]

The "IEEE Transactions on Semiconductor Manufacturing" is a journal that publishes the latest advancements in the manufacturing of microelectronic and photonic components. It aims to enhance knowledge and improve manufacturing practices in the semiconductor industry. The journal covers various topics such as process integration, manufacturing equipment performance, yield analysis, metrology, and supply chain management. Papers submitted to the journal should focus on practical engineering techniques for solving manufacturing-related problems. The journal follows a peer-review process and encourages authors from low-income countries to submit their work. The standard length for regular papers is eight pages, and shorter contributions can be submitted as letters. The journal provides guidelines for manuscript preparation, including the use of the IEEE template style. It also accepts graphical abstracts and electronic supplements. Authors are responsible for preparing a publication-quality manuscript and may use English language editing services if needed. Plagiarism is strictly prohibited, and manuscripts found to have plagiarized content may be penalized. Authors are required to have an Open Researcher and Contributor ID (ORCID) and can submit their manuscripts online. The journal offers both traditional and open access publication options, with associated fees. Native language author names are supported, and page charges may apply for publication. The IEEE holds the copyright to the published material. [Extracted from the article]

Detecting wafer map anomalies is crucial for preventing yield loss in semiconductor fabrication, although intricate patterns and resource-intensive labeled data prerequisites hinder precise deep-learning segmentation. This paper presents an innovative, unsupervised method for detecting pixel-level anomalies in wafer maps. It utilizes an efficient dual attention module with a knowledge distillation network to learn defect distributions without anomalies. Knowledge transfer is achieved by distilling information from a pre-trained teacher into a student network with similar architecture, except an efficient dual attention module is incorporated atop the teacher network’s feature pyramid hierarchies, which enhances feature representation and segmentation across pyramid hierarchies that selectively emphasize relevant and discard irrelevant features by capturing contextual associations in positional and channel dimensions. Furthermore, it enables student networks to acquire an improved knowledge of hierarchical features to identify anomalies across different scales accurately. The dissimilarity in feature pyramids acts as a discriminatory function, predicting the likelihood of an abnormality, resulting in highly accurate pixel-level anomaly detection. Consequently, our proposed method excelled on the WM-811K and MixedWM38 datasets, achieving AUROC, AUPR, AUPRO, and F1-Scores of (99.65%, 99.35%), (97.31%, 92.13%), (90.76%, 84.66%) respectively, alongside an inference speed of 3.204 FPS, showcasing its high precision and efficiency. [ABSTRACT FROM AUTHOR]

It is known that the determination of the good-dice-in-bad-neighborhoods (GDBNs) has been regarded as an effective technique to reduce the value of the defect parts per million (DPPM) by identifying and rejecting the suspicious dice even though they are good in testing. Instead of examining eight immediate neighbors in a small-sized $3\times 3$ window or exploiting simple linear regression, a large-sized window can be used to recognize the broad-sighted neighborhoods and accurately infer the suspiciousness level for any given die. In this paper, the artificial neural networks (ANN)-based method can be proposed to solve the GDBN identification. Furthermore, two enhanced techniques can be further presented to improve the inference accuracy of the original ANN-based method by considering the variation of the time-dependent wafer patterns and the wafer-to-wafer relationship between two adjacent wafers. After applying the two enhanced techniques, the business profits can be improved in the new ANN-based method. Various experiments on two datasets clearly reveal the superiority of the proposed ANN-based method over the other existing methods. In addition to the reduction of the DPPM value, the new ANN-based method can achieve the 1.5X–2X better reduction in the cost of the return merchandise authorization (RMA). On the other hand, the experimental results show that the similar result can also be obtained in the other lower-yield products. By using the new ANN-based method, the relationships on bad dice cross wafers can be captured and the highly-accurate inference results can be simultaneously maintained. [ABSTRACT FROM AUTHOR]

Three dimensional Not-And (3D NAND) flash memory devices are scaling in the vertical direction to more than 200 oxide/sacrificial wordline nitride layers to further increase storage capacity and enhance energy efficiency. The accurate measurement of the thicknesses of these layers is critical to controlling stress-induced wafer warping and pattern distortion. While traditional optical metrology in the UV-vis-NIR range offers a non-destructive inline solution for high volume manufacturing, we demonstrate in this paper, that mid-IR metrology has advantages in de-correlating oxide and nitride thicknesses owing to their unique absorption signatures. Furthermore, because of the depths sensitivity of oxide and nitride absorptions, the simulated measurement results show the ability to differentiate thickness variations in the vertical zones. Good blind test results were obtained with a machine learning model trained on pseudo-references and pseudo spectra with added skew. [ABSTRACT FROM AUTHOR]

Titanium tetrachloride (TiCl4) is a well-known source of titanium (Ti) for the formation of titanium nitride (TiN) barrier material in the semiconductor interconnection process; however, the reaction of by-products with airborne molecules can cause unexpected pump trips and equipment breakdown from the by-product powder build-up. Plasma scrubbers are used to decompose by-products, but hydrogen chloride (HCl) and nitrogen oxides are produced during and after the process. The process mechanisms change when the temperature and applied power of the heat source change. In this paper, we study the influence of the reactor temperature and applied power to the heat source on the decomposition capacity of TiCl4 in a plasma pretreatment system (PPS). We examine the effect of the temperature and heat source power to understand the reaction mechanisms for the composition and decomposition of gaseous species with chemical reactions through simultaneous methods. We analyzed the system with computational fluid dynamics (CFD) and chemical kinetic simulation to investigate the changes of the system mechanism. Subsequently, we achieved results for the correlation between the temperature of the reactor, power applied to the heat source, composition and decomposition of species, and chemical reaction mechanisms. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing processing can be jeopardized due to process fluctuations, and the degradation of equipment parts can significantly influence process variation. Timely diagnosing equipment faults causing process variations is desired in current high-end product manufacturing. This paper proposes a diagnostic method for the SiH4 gas flow rate drift using N2 vibrational transition in oxide deposition. In this research, optical emission spectroscopy (OES) and quadrupole mass spectrometer (QMS) are employed as condition monitoring sensors serving as a reference model to compare the diagnostic performance for gas flow rate drift. The study observes that the OES model exhibits much higher performance for minor diagnoses of less than 5% drift. The diagnostic model performance can be enhanced by incorporating plasma condition and gas indicators compared to when these indicators are used individually. This suggests that when conducting diagnostics for equipment and processes, it is crucial to consider indirect indicators like plasma indicators along with direct indicators such as gas radical density. The comprehensive use of both types of indicators enhances the diagnostic performance, providing a more accurate assessment of the conditions and potential problem in semiconductor manufacturing. [ABSTRACT FROM AUTHOR]