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In this work, we manifest that the epitaxial structure for p-GaN gate high-electron-mobility transistor is a versatile platform to develop electronics for operating in an extremely wide temperature range (X-WTR) from 2 to 675 K, with comprehensive X-WTR studies on device operation and circuit behaviors. The key enabler for the high-temperature operation is the wide bandgap that substantially suppresses the thermal excitation of the intrinsic carrier. However, for the low-temperature side, the two-dimensional electron and hole gas (2DEG and 2DHG) channels at the heterojunctions are formed by the temperature-insensitive polarization fields, which free the carriers from freezing out. The monolithically integrated GaN n-FET, p-FET, and the resultant complementary circuits are, therefore, shown to operate in X-WTR. [ABSTRACT FROM AUTHOR]

The p-GaN/AlGaN/GaN heterostructure, predominantly epitaxially grown on large-scale silicon wafers, has been widely used for producing consumer power switching devices and recently manifested favorable for developing GaN-based complementary devices and circuits. This work investigates the hole distribution and transport in this structure based on wide-temperature-range (20–600 K) Hall measurements and TCAD simulations. It is revealed that the p-channel thereof is composed of the bulk holes in the p-GaN and the two-dimensional hole gas (2DHG) at the p-GaN/AlGaN interface, and both substantially contribute to the lateral p-type conduction at room temperature. Their complementary temperature responses lead to conductivity enhancement at both high- and low-temperature regimes. The high-density (1.2 × 1013 cm−2) 2DHG is formed owing to the polarization-induced potential well and the ionization of the Mg acceptors that thermally diffused into the barrier during the epi-growth. Such ionized Mg acceptors would partially deplete the two-dimensional electron gas (2DEG) at the access region in the n-channel side where the p-GaN is removed and result in a trade-off between the carrier density of 2DHG and 2DEG. [ABSTRACT FROM AUTHOR]

A physical insight into the capture and emission behavior of interface/oxide states in a GaN-based metal-oxide-semiconductor (MOS) structure is of great importance to understanding the threshold voltage (VTH) instability in GaN power transistors. A time-dependent VTH shift in Ni/Al2O3/AlGaN/GaN MOS-HFETs (heterojunction field-effect transistors) and a distribution of Al2O3/III-nitride interface states (Dit) were successfully characterized by constant-capacitance deep level transient spectroscopy. It is found that in situ remote plasma pretreatments in plasma-enhanced atomic-layer-deposition could suppress Dit (EC-ET > 0.4 eV) down to below 1.3 × 1012 cm−2 eV−1. Under high applied gate bias (e.g., VG > 8 V), tunnel filling of oxide states in the Al2O3 dielectric comes into play, contributing to remarkable VTH instability in the MOS-HFETs. The tunnel distance between the 2D Electron Gas (2DEG) channel and oxide states ET,ox in the Al2O3 dielectric decreases from 3.75 to 0.82 nm as VG increases from 2 to 8 V. A further increase of VG to 11 V makes the Fermi level approach ET,ox (EC − ET ∼ 1.62 eV), which may enable direct filling. High electric field induced tunnel filling of gate oxide states could be an assignable cause for VTH instability in normally-OFF III-nitride MOS-HFETs. [ABSTRACT FROM AUTHOR]

Enhancement-mode (E-mode) p-channel gallium nitride (GaN) field-effect transistors (p-FETs) are essential components for GaN-based complementary logic circuits. For the ease of integration with n-FETs, they could be fabricated on the commercial p-GaN gate high-electron-mobility-transistor (HEMT) platform, on which the two-dimensional electron gas at the AlGaN/GaN hetero-interface is completely depleted in as-grown epi-structures. However, under the gated region where p-GaN is recessed and depleted at thermal equilibrium, a parasitic electron channel (PEC) could appear at the AlGaN/GaN interface. This Letter reports experimental investigations on the PEC with specifically designed structures, confirming that the PEC does exist but imposes limited impacts on electrical characteristics of p-FETs. When connected with an external contact, the PEC could act as a back gate to modulate the overlaying p-channel. If isolated from external contacts, which is the case of p-FETs under normal operations, electrons in the PEC would redistribute under the active region of p-FETs in the horizontal direction (i.e., parallel to the surface) under different biases but are mostly confined near the AlGaN/GaN interface in the vertical direction (i.e., perpendicular to the surface). [ABSTRACT FROM AUTHOR]

In this work, the impact ionization-induced OFF-state breakdown is revealed and systematically investigated in 100 V Schottky-type p-GaN gate high-electron-mobility transistors. Impact ionization is found to occur in the peak electric-field region at the source-terminated field-plate edge and is initiated by electrons injected from the source-side two-dimensional electron gas channel through the buffer layer. Hot electrons generated from impact ionization, when being captured by surface traps, could lead to redistribution and peak value reduction of electric-field. Consequently, the sudden rise in the OFF-state leakage current by impact ionization could be self-clamped temporally to avoid catastrophic rupture of the device. The impact ionization is further verified by the increase in dynamic OFF-state leakage current and a negative shift in threshold voltage, both of which result from positively charged holes (generated from impact ionization) drifting toward the gated channel. [ABSTRACT FROM AUTHOR]