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Time-dependent conduction in epitaxial superlattice (SL) strain relief layers of GaN high electron mobility transistors on 200 mm engineered substrates with a poly-AlN core was observed and analyzed. This phenomenon occurs when the devices were operated with substrate bias of ∼−300 V for 101–103 s. The formation of the conduction path is related to trap-assisted leakage through the SLs on the engineered substrates; de-trapped carriers spread out vertically and laterally within a portion of the SLs, leading to a higher electrical field across the rest of the layers. This conduction mechanism may be hidden during the devices' normal operation (target 650–1200 V). It could lead to undesired effects during the operation of the devices, such as a time-dependent dynamic Ron. More resistive SLs will potentially reduce the impact of this phenomenon. [ABSTRACT FROM AUTHOR]

This work addresses the impact of the Mg activation anneal step and the resulting acceptor concentration on the channel mobility and VT stability of vertical MOSFETs. Increasing the annealing time with N2 only ambient and the annealing temperature with O2 in the ambient is shown to be effective in increasing the channel acceptor concentration. When the effective acceptor concentration is increased, the mobility is degraded due to a transition in the main scattering mechanism from Coulomb to surface roughness scattering. Degradation of the on-state current and maximum transconductance at high operating temperatures was linked to bulk mobility degradation of the drift layer due to lattice scattering. The two Mg activation annealing conditions considered here show different trends with regard to the threshold voltage stability, while N2 only ambient did not impact this parameter, including O2 increased threshold voltage instability. It is shown that increasing the Mg chemical concentration in the p-GaN layer degrades channel mobility and threshold voltage stability, irrespectively of the effective acceptor concentration, providing evidence for degradation of the channel/dielectric interface characteristics with higher Mg chemical concentration. This study shows that it is possible to achieve very low threshold voltage hysteresis and high channel mobility by reducing the Mg chemical concentration while maintaining high effective acceptor concentration. These results provide key insights for the development of vertical GaN FETs. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate the epitaxial growth of a gallium-nitride (GaN) buffer structure qualified for 1200 V applications on 200 mm engineered poly-AlN substrates with hard breakdown >1200 V. The manufacturability of a 1200 V qualified buffer structure opens doors to high voltage GaN-based power applications such as in electric cars. Key to achieving the high breakdown voltage is careful engineering of the complex epitaxial material stack in combination with the use of 200 mm engineered poly-AlN substrates. The CMOS-fab friendly engineered poly-AlN substrates have a coefficient of thermal expansion (CTE) that closely matches the CTE of the GaN/AlGaN epitaxial layers, paving the way for a thicker buffer structure on large diameter substrates, while maintaining the mechanical strength of the substrates and reaching higher voltage operation. [ABSTRACT FROM AUTHOR]

Three different diffusion models in SiGeC layers are compared and evaluated for their implementation in the process simulation program Taurus TSUPREM-4™ (TSUPREM-4 computer code from Synopsys, Inc.). The models considered in the evaluation are verified for actual process conditions of modern SiGeC heterojunction bipolar transistors in bipolar complementary metal-oxide-semiconductor technologies. Rapid thermal annealing temperatures in the range of 1020–1070 °C were used for the present study. In this study it is shown that the compared models are similar to each other despite the different physical approach. A common set of coefficients was used for the simulations of the three models under study. [ABSTRACT FROM AUTHOR]

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-gm), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si3N4, Rapid Thermal Chemical Vapor Deposition Si3N4, and Atomic Layer Deposition (ALD) Al2O3) for AlGaN/GaN Metal-Insulator- Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (Dit), the amount of border traps, and the threshold voltage (VTH) shift during a positive gate bias stress can be obtained. The results show that the VTH shift during a positive gate bias stress is highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the VTH shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract Dit needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the gm dispersion commonly attributed to border traps might be influenced by interface states. [ABSTRACT FROM AUTHOR]