1. Advance anti-PVT-variation low-power time-to-digital converter design using 90-Nm CMOS process.
- Author
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Kumar, M. Dileep, Kumar, T. Siva, and Ramaiah, G. N. Kodanda
- Subjects
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TIME-digital conversion , *COMPLEMENTARY metal oxide semiconductors , *PHASE-locked loops , *ANALOG-to-digital converters , *ELECTROSTATIC discharges - Abstract
A number of studies have recently focused on time to virtual converters. TDCs provide a wide variety of programmes, including time-of-flight (ToF), radar range, and particle lifespan dimension, among others. Now that all-virtual Phase Locked Loops and True-Diode-Control (TDC) are standard in ADCs, virtual converters can really make analogue signals work. For this one-of-a-kind PVT area, you'll need a top-notch Time-to-Digital Converter. This brief study suggests a process-variant-insensitive Time-to-Digital Converter with Process-Voltage-Temperature detection capabilities. The Process-Voltage-Temperature detector can distinguish Process-Voltage-Temperature corners using a variety of offset lines with optimum locking conditions. The proposed Time to Digital Converter is physically found using a 90-nm CMOS technology. [ABSTRACT FROM AUTHOR]
- Published
- 2024
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