Search

Hafnium oxide is one of the most promising high dielectric constant materials to replace silicon dioxide as the gate dielectric. To take the advantages of high dielectric constant of HfO[SUB2] thoroughly, the relatively low dielectric constant interfacial layer must be controlled carefully. In this work, the formation of an interfacial SiO[SUB2] layer at the HfO[SUB2]/Si interface was studied comprehensively. It is observed that during reactive sputtering deposition of the HfO[SUB2] layer, a very thick interfacial SiO[SUB2] layer, thicker than 3 nm, would be grown. O-radical signals, instead of O[SUB2]-radicl signals, are detected in the sputtering chamber. An O-radical enhanced oxidation model is proposed to explain such an unusual thick SiO[SUB2] layer. The adoption of a two-step deposition method, the thickness of interfacial SiO[SUB2] layer can be reduced only if the bottom Hf layer is thicker than 5 nm. However, the reduction of effective oxide thickness would be limited. Reoxidation of Hf film sounds a better choice. A 1.0-1.5-nm-thick interfacial SiO[SUB2] layer is still observed. This implies that the traced oxygen in the sputtering chamber plays a critical role on the formation of the interfacial layer. It is thus concluded that reactive sputtering is not a suitable method to prepare a HfO[SUB2] layer with a negligible interfacial SiO[SUB2] layer. Reoxidation of Hf film is a better choice, but the oxygen content in the sputtering chamber must be well controlled. [ABSTRACT FROM AUTHOR]

Nano-porous carbon doped oxide (CDO) is one of the potential low dielectric constant (low-k) materials that can achieve a dielectric constant as low as 2.2 and is expected to be suitable for the next generation multilevel interconnection. However, the electrical stability of CDO in contact with metal has not been addressed. In this work, metal ions’ drift into nano-porous CDO is investigated. It is observed that both the Al and Cu ions can be driven into porous CDO film easily by applying electric field or thermal treatment. This results in a severe flat band voltage shift of the metal/CDO/Si capacitor structure. It is hypothesized that the lacking formation of self-limited aluminum oxide between Al and CDO film make Al ions drift into CDO. The adhesion of Al and Cu to CDO is also very poor. A physical model, combining weak dielectric polarization and metal ions drift, was proposed to explain the observed electrical instability. The inconsistent results regarding the Al/porous low-k/Si structure reported in the previous literatures can also be explained with this proposed model. Fortunately, TaN, as a common diffusion barrier material for Cu interconnect structure, is proved to have good adhesion to CDO. Negligible metal ions would drift in CDO during electrical stress. It is concluded that with a suitable diffusion barrier, such as TaN, CDO is still a very promising material for next generation Cu-interconnect technology. © 2003 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Presents a study that investigated the characteristics of PtSi-silicided p[sup+] n shallow junctions fabricated by implanting BF[sub2][sup+] ions and low-temperature furnace annealing. Benefits of self-aligned silicide process; Procedures in preparing the samples; Summary of the sample identification number and the key process conditions.

Presents a study that investigated low-termperature reaction of thin-film platinum with silicon. Sheet resistance measurement of silicide formation sequence; Use nitrogen furnace; X-ray diffraction analysis.

Studies the capability of using platinum and platinum-silicon in the ion implantation through metal or metal silicide technique. Procedure of the experiment; Measured electrical characteristics of the sample; Results of the leakage current analysis; Conclusion.

Presents a technique based on the ion implantation of fluoride ion or species containing fluoride atoms into the silicon substrate underneath the platinum silicide (PtSi) layer. Function of PtSi; Material analysis of the PtSi under various annealing conditions; Silicide film characteristics.

Presents a study that formed a shallow silicided n[sup+]p junction by implanting arsenic ions into platinum or platinum silicide films followed by low-temperature furnace annealing in the nitrogen ambient. Benefits from implanting a dopant through metal/silicide; Reason that the ion implantation through metal sample exhibits smaller leakage than ion implantation through metal silicide sample; Annealing temperature dependence of the forward ideality factor.

Presents information on a study which examined proposed mechanisms on the role of fluorine in the thermal stability of silicide/silicon structures. Background of the study; Methodology of the study; Results and discussion.

Although high channel electron mobility has been reported after some passivation techniques, the performance of n-channel Ge metal-oxide-semiconductor field-effect transistor is still limited by the high Schottky barrier height at the metal/n-Ge contact interface, which comes from the Fermi level pinning effect. Recent experiments demonstrated that the Schottky barrier height can be reduced by inserting a thin dielectric layer between metal and Ge. However, the mechanism has not been well clarified. In this paper, the metal induced gap state model, the dipole layer model, and the fixed charge model are verified by varying contact metals, dielectric thicknesses, as well as the annealing temperatures. The pinning factor is improved slightly by dielectric insertion but its value is independent of the dielectric thickness and is still much lower than the ideal value of the non-pinning case. This pinning effect is consistent with the Fermi level pinning at the metal/TiO2 interface. After thermal process, no interfacial layer forms at the TiO2/Ge interface and the TiO2 crystallizes gradually after annealing but the Schottky barrier height increases. Since the amount of fixed charges in the thin dielectric layer estimated from a metal-insulator-semiconductor structure is about 2 × 1011 cm-2 and is insufficient to produce the observed 0.5 eV Schottky barrier height reduction, it is thus recommended that the main mechanism comes from the change of interface dipoles and the annealing effect is attributed to the short-range ordering of the TiO2 layer. Furthermore, dielectric with low conduction band offset which has good thermal stability should be explored. [ABSTRACT FROM AUTHOR]