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Nowadays, deep learning algorithm has been widely used for automatic electrocardiogram (ECG) classification. However, most algorithms can only classify single heartbeat, which requires complex heartbeat extraction preprocessing. In addition, the traditional software implementation on CPU or GPU platform faces the challenge of low computing efficiency and high resource consumption. In this work, a deep one-dimensional (1D) U-net is proposed, which can classify the original continuous ECG segment at the pixel level. And an efficient hardware architecture is presented to implement the 1D U-net. A two-stage pipeline Winograd structure is designed to increase computing efficiency. A 3D processing element (PE) array is developed to improve resource utilization and overall throughput. Implemented on Xilinx Zynq ZC706 board, experimental results show that the proposed 1D U-net achieves an average accuracy of 95.55% for the pixel-level classification of five heartbeats. In terms of hardware performance, resource efficiency and computing efficiency reach 8.27 GOPS/kLUT and 123% respectively at 200 MHz clock frequency. [ABSTRACT FROM AUTHOR]

Abstract: Embedded systems are vulnerable to buffer overflow attacks. In this paper, we propose a hardware memory monitor module that aims to detect buffer overflow attacks by analyzing the security of an embedded processor at the instruction level. The functionality of the memory monitor module does not rely on the source code and can perform security check through dynamic methods. Compared with several existing countermeasures that protect only part of the program’s data space, our proposed memory monitor module can protect the program’s entire data space. The proposed memory monitor module has negligible performance overhead because it runs in parallel with the embedded processor. As demonstrated in an FPGA (Field Programmable Gate Array) based prototype, the experimental results show that our memory monitor module can effectively resist several types of buffer overflow attacks with approximately a 15% hardware cost overhead and only a 0.1% performance penalty. [Copyright &y& Elsevier]