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In this study, a static-RAM cell using the Gnr-GDI method is proposed as a weak-type physical unclonable function (PUF) circuit to generate a unique and stable binary output for secure IoT devices. Regarding the memory level, a suitable combination of dynamic body bias, stacked networks, and multi-V th techniques has been used in the architecture of asymmetric cell-structure inverters as a latch section to reduce power consumption and improve hardware efficiency. In addition, the logic styles of virtual ground and power gating based on word and BL data lines and a tri-state buffer structure have been used to extend the write VTC and improve read stability, respectively. From the perspective of PUF performance, the body of the latch section can form skewed VTCs based on the setting of critical parameters in GnrFET technology to achieve an efficient PUF circuit design. At the memory performance level, the Monte Carlo (MC) method-based results confirm the reasonable performance of the proposed structure in terms of static noise margin (SNM) and hardware efficiency, such as 53 % delay and 72 % energy-delay product (EDP) parameters, compared with the 6 T SRAM structure in a similar 16 nm GnrFET technology. In addition, in terms of the performance as a PUF circuit, the simulation results demonstrate the superiority of the proposed cell in terms of energy consumption, BER, response time, uniqueness, and stability under non-technological variation conditions of temperature and supply voltage. The outstanding performance results of the figure of merits (FoMs), CEQM, and UR2, which are composed of variability, energy, reliability, and layout-level factors, indicate the suitability of the proposed memory architecture for use in both the memory and PUF modes. Furthermore, to investigate the application level, memory structure has been used to store fingerprint images as PUF data using a hardware algorithm. The results of the proposed comprehensive FoM, which is based on the simultaneous consideration of circuit level and quality parameters, indicate that the proposed memory scheme in a bit-interleaved architecture-compatible design can be introduced as a high-performance candidate for generating and storing unique binary data in PUF-based IoT platforms. [ABSTRACT FROM AUTHOR]

Although remote sensing sensors acquire hyperspectral images (HSI) with outstanding spectral resolution, hardware limitations prevent them from obtaining HSI with superior spatial resolution. Having high-resolution multispectral images (MSI) from the same scene has sparked the concept of HSI-MSI fusion to achieve high-resolution HSI. Recently, deep learning algorithms have shown excellent performance in HSI-MSI fusion. Deep learning algorithms can automatically extract the priors latent in the input data and reconstruct the output image. However, their performance depends on the training data's inherent characteristics. HSI volume is generally significantly larger than MSI volume. While the high-resolution MSI provides richer spatial information, its contribution to fusion is lower due to its smaller volume. To address this volume discrepancy, a deep convolutional neural network named BASFE is proposed. This network employs a two-branch structure that balances the extracted spatio-spectral features from both HSI and MSI input images, enabling effective feature fusion. Therefore, better efficiency can be achieved by using simpler structures. Experiments showed that balancing the data improves the model's performance significantly. Furthermore, to improve efficiency and reduce complexity and computational burden, the spatio-spectral feature extraction residual modules are embedded in a dense architecture to jointly extract these features. Comprehensive experiments on five challenging datasets show that BASFE surpasses state-of-the-art algorithms. Compared to the first- and second-best competing methods, the proposed method achieves an average improvement of 1.58 dB and 3.68 dB in peak signal-to-noise ratio (PSNR) across the five studied datasets. The source code of BASFE is available in https://github.com/rajaei-arash/BASFE_hyperspectral_fusion.git. • A new architecture for fusion is used to balance the priors extracted from images. • It is shown that higher accuracy can be achieved by data balancing. • The SFER modules are embedded in dense structures for effective prior extraction. • This method jointly extracts spatio-spectral features from both HSI and MSI. [ABSTRACT FROM AUTHOR]

Multipliers are one of the most commonly used parts in a system, responsible for performing computations, while significantly contributing to power consumption. In this article, by removing the least significant bits, a new architecture is presented to implement 3 multipliers (Mul-1, Mul-2 and Mul-3), in order to reduce complexity and power consumption. Compared to the previous works, Mul-1 has the most accuracy in addition to its low energy consumption, therefore, it has been able to deliver a good trade-off between accuracy and energy consumption. All proposed designs and existing multipliers have been simulated and compared in 7 nm FinFET technology using Hspice tool. Moreover, the accuracy and quality of the proposed approximate multipliers are also evaluated using MATLAB. The results show that Mul-1 and Mul-3 are very efficient in image processing applications. According to the results, Mul-1 outperforms its counterpart by 10%, 50% and 50% in PDP, NMED and MRED, respectively. Furthermore, Mul-3 has satisfactory MSSIM in DSP applications and is better than its counterpart by 23% and 16% in PDP and MRED. Meanwhile, Mul-2 improves PDP by nearly 53% compared to Mul-1 and has the lowest power consumption. [Display omitted] • To reduce power consumption, some least significant bits are set to zero. • To ensure accuracy in multipliers, compressors have been employed as exact. • The error compensation circuit is presented to enhance precision in the second stage. • The use of multipliers in real applications that have high computational volume. [ABSTRACT FROM AUTHOR]

In this work, CNTFET-based GDI (CNT-GDI) and QCA-based GDI (QCA-GDI) methods (CNT/QCA-GDI) for designing unique ultra-efficient analogue and logical blocks in voltage-mode fuzzy and quantum systems are presented. Extensive Monte-Carlo simulations by using Synopsys H-SPICE simulator at 16 nm technology demonstrate that the analogue blocks improve considerably in term of performance, absolute error and energy consumption in the presence of compact variations in compared to their counterparts. Also, the logical blocks have advantages including fast response, high polarity and lower power-consumption achieved by the QCADesigner and QCAPro tools at 18 nm in contrast to the similar designs. As applications, the half wave rectifier (HWR) and full-wave rectifier (FWR) by employing the proposed methods in two technologies are implemented. The results show improvement for the proposed circuits with correct function and very high robustness under major variations in contrast to state-of-the art rectifier architectures at similar conditions. Consequently, the proposed methods are appropriate for designing integrated circuits (ICs) with higher capacity and energy-efficient for the emerging nano-technologies. [ABSTRACT FROM AUTHOR]

Highlights • A new preprocessing method to enhance the spatial resolution of EEG. • The proposed method does not have some of the limitations of the Laplacian methods. • Providing better results than Laplacian methods in both 32- and 64-channel montages. Abstract Objective EEG is widely used in the brain-computer interface (BCI) systems. Unfortunately, the spatial resolution of EEG is low, due to the volume conduction. This degrades the performance of BCI systems. Several methods have been proposed to overcome this problem, and surface Laplacian is popular among them. In this work, we propose a novel method, local activities estimation (LAE) that enhances the spatial resolution of EEG and improves the overall performance of the BCI system. Methods In the LAE, the potential caused by sources close to an EEG electrode is estimated by a system of linear equations based on a few definitions and assumptions. Results The experimental results on both 64-channel and 32-channel motor imagery data from publicly available BCI Competition datasets indicate the superiority of the LAE over the finite difference Laplacian, spherical spline Laplacian, and common average reference in all tested conditions (p < 0.05). Conclusions LAE improves the BCI performance even better than Laplacian methods. Significance unlike the finite difference Laplacian, LAE does not have uncertainty in the neighbour electrode selection or high sensitivity to electrode positions. It also does not include mathematical complexity and parameter selection ambiguities of spline Laplacian. LAE is implemented by an easy and low-complexity algorithm. [ABSTRACT FROM AUTHOR]

Abstract To decrease the parameters like: power dissipation, propagation delay and chip area in very-large-scale integration (VLSI) circuits, the gate-diffusion input (GDI) technique is convenient to be used. One of the most important functional blocks in frequency synthesizers is the dual-modulus frequency prescaler (DMFP) circuit. In this research work, we present novel powerful and robust designs which are part of proposed divide-by-N/[N+1] DMFP schemes for moduli set {N=1,2,3,4} with more efficiency, power storing and minimizing the gate counts using carbon nano-tube field-effect transistor (CNTFET)-based modified GDI (m-GDI) method. The simulation results of architectures in two standard CMOS and CNTFET technologies, clarified that the CNTFET-based proposed circuits are more effective in terms of critical path delay, power dissipation and worst delay-power consumption-chip area product (DPA) parameters. Also, according to the simulation results, presented DMFPs are capable to work at extensive evaluate frequency ranges with higher figure of merits (FOMs) at the maximum operating frequency (f m a x.). For the proposed circuit's performance different variations process including diameter of CNTs, voltage and temperature (PVT) have been done by Monte-Carlo simulations. Thus, comparative analysis based on the Monte-Carlo simulation exhibits that the proposed structures show significant low-power consumption, sensitivity and larger noise-immunity in the presence of the impact of PVT variations. Therefore, the proposed DMFPs can be implemented in digital phase-locked loop (PLL) blocks for future wireless communication like: 5 Generation (5G) and microprocessor chips. [ABSTRACT FROM AUTHOR]

In this work, unique characteristics of carbon nano-tube field effect transistor (CNTFET) are used to propose a universal cell with a simple architecture based on the binary modified gate-diffusion input (m-GDI) method for designing fundamental gates in the voltage-mode multiple-valued logic (MVL) with any arbitrary number of logic levels for processing at nano-scales. The results of the simulations confirm more energy-efficiency, larger noise margins and lower sensitivity of the proposed designs in different logic levels as compared with the state-of-the-art designs. The effects of the process, voltage and temperature (PVT) variations are extensively evaluated by Monte–Carlo simulation. According to the results, the proposed designs are robust against PVT variations and noise. The proposed structure is applied to the MVL-based image processing. The results show that the output images of the proposed MVL-based inexact gates have an appropriate quality in compare with the images generated by the other similar exact gates. [ABSTRACT FROM AUTHOR]

The conventional complementary metal-oxide semiconductor (CMOS) design techniques confront to the limitation of designing the integrated circuits (ICs), especially memories, with multiple-valued logic (MVL) in nanotechnology. Gate diffusion input (GDI) technique, provides the possibility to design low power logic gates with small chip area and interconnection capacitors while the number of transistors is diminished. In this paper first ternary GDI (t-GDI) cell based on the proposed binary (two-valued) modified GDI (m-GDI) method, which is appropriate for designing circuits using MVL, is designed. Then, by using the standard ternary inverter (STI) gate implemented based on the proposed t-GDI cell with better noise margins and also small standard deviation of results, first novel design of a ternary SRAM (T-SRAM) cell is presented for nano process, which has smaller standby power dissipation and standard deviation for delay of writing and reading cycles, better read static noise margin (RSNM) and lower signal control complexity. The design of specific structure of 4-words×4-bits, ternary SRAM (4×4 T-SRAM) shows that the number of connections, chip area is decreased and power-delay product (PDP) criterion is improved for writing and reading cycles with significant small standard deviation in compare with the other similar T-SRAMs designed. The effects of different process variations such as density, number of CNTs and temperature variations are extensively evaluated by Monte-Carlo simulation, with respect to performance metrics such as delay, power dissipation and PDP of writing and reading cycles, also RSNM parameter for SRAM cells. The comparison exhibits that in all cases the proposed T-SRAM cell showing a substantial small standard deviation and considerable lower variability percentage than state-of-the art SRAM cells. So, the proposed T-SRAM cell design has the lowest sensitivity variations, thus it is an attractive choice for nano technology application in the presence of impact process and temperature variations. The simulation is done with Synopsys H-SPICE simulator in 32 nm technology under the condition of variations. [ABSTRACT FROM AUTHOR]

SRAM designing with greater storage capacity and lower power dissipation with desired stability by employing conventional CMOS technology seems to be impossible due to enhancement of short channel effect and leakage current due to increasing the number of the transistors. Up to now a lot of methods have been proposed in order to improve the performance of the logical circuits based on the CMOS technology, among of them the Gate-Diffusion Input (GDI) technique is an efficient method. In this paper the modified GDI cell (m-GDI) based on the basic GDI cell is proposed and then SRAM cell memory with 8 transistors (8T-SRAM) which uses the proposed GDI cell is presented. Due to the achieved results the stability-power dissipation ratio (SPR), the evaluation parameter in SRAM memories, is improved about 7 for 8T-SRAM which is implemented with a stack forcing method in similar carbon nanotube field-effect transistor (CNTFET) technology. Finally the 4×4 SRAM memory is proposed based on 1×1 SRAM with the help of 8T-SRAM. This memory is presented with array structures for reading and writing blocks. The simulation results reveal that the Power-Delay Product (PDP) term decreases 18% and 36% in the reading and writing cycles respectively for the stack forcing SRAM with the same array. The simulation is done with H-SPICE software in 32 nm technology under the condition of 0.9 V supply voltage, 500 MHz frequency and room temperature. [ABSTRACT FROM AUTHOR]

In optimal PMU placement problem, a common assumption is that each PMU installed at a bus can measure the voltage phasor of the installed bus and the current phasors of all lines incident to the bus. However, available PMUs have limited number of channels and cannot measure the current phasors of all their incident lines. The aim of this paper is to recognize the effect of channel capacity of PMUs on their optimal placement for complete power system observability. Initially, the conventional full observability of power networks is formulated. Next, a modified algorithm based on integer linear programming model for the optimal placement of these types of PMUs is presented. The proposed formulation is also extended for assuring complete observability under different contingencies such as single PMU loss and single line outage. Moreover, the problem of combination of PMUs with different number of channels and varying costs in optimal PMU placement is investigated. Since the proposed optimization formulation is regarded to be a multiple-solution one, total measurement redundancy index is evaluated and the solution with the highest redundancy index is selected as the optimal solution. The proposed formulation is applied to several IEEE standard test systems and compared with the existing techniques. [ABSTRACT FROM AUTHOR]

Highlights: [•] The effect of channel capacity of PMUs on their optimal placement is investigated. [•] A method for optimal placement of PMUs with limited number of channels is proposed. [•] The method is extended for assuring full observability under various contingencies. [•] The scalability of the method is demonstrated on several IEEE test systems. [•] The results show that the proposed method can be applied to real-world network. [Copyright &y& Elsevier]

Abstract: A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18µm CMOS technology while it works at 1.8V supply voltage. The VCO has a phase noise of −136dBc/Hz at 1MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4mW and the chip area is 10,400µm2. [Copyright &y& Elsevier]

In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to reducing power and energy consumption can show high reliability and have the least error at low voltages. This cell is completely free from the half-select issue, which is one of the important factors in increasing power and decreasing reliability, especially at low voltage levels for SRAM arrays. It is designed without the need of write-bit-line, which according to the proposed techniques reduces the power consumption and significantly improves the write margin, also the lack of this bit-line in the memory array can reduce the total power consumption. The used bit-line only performs for read operation, therefore it has least activity. Also, an 8 Kb memory array is proposed to be able to perform various operations with less complexity, simpler logic and lower power consumption by proposing several techniques on peripheral circuits. All obtained noise margins according to proposed techniques have the highest values among the compared cells. The average power and PDP of the cell are less than all the compared designs, so that the average power and presented FoM has been improved by 6.83% and 18.46% respectively as compared to the best value of other designs. [ABSTRACT FROM AUTHOR]

In this paper, a robust 12T-SRAM memory cell at sub-threshold voltage is designed to reduce power consumption for low power applications, that in addition to reducing power consumption can perform well at high frequencies and remain stable. For the write operation, a new method has been used that removes the write bit line and uses the supply voltage in each cell for this operation and only by applying control signals. Also, the embedded bit line is used only for read operations and reduces the activity of the bit line, and due to being floating and the way of writing, eliminates the Precharge and Write Driver circuits, so, part of the power and area consumption has been reduced. According to the techniques used, the write and read noise margin is significantly improved and the write operation become easier to perform. Also due to the existence of a separate path for the read operation, RSNM is equaled to the HSNM. The average cell power at the frequency of 100 MHz for low power applications and 0.2V supply voltage, as compared to the best previous designs, has been improved by 34.9% and the leakage power of the hold state has been reduced by 27.6% and PDP has been improved by more than 35.2%, further, the maximum operating frequency of the cell has been increased by 39.1%, while it operates with the sub-threshold voltage of 0.2V to the frequency of 2.173 GHz. [ABSTRACT FROM AUTHOR]

• The combination of LAE and CSP performs better than either method. • LAE-CSP achieves a mean accuracy of 78.52 % over 28 subjects using 10 training trials. • CSP, FBRCSP, EA-CSP and LAE were compared with LAE-CSP using 4 different datasets. The common spatial pattern (CSP) and its variants are popular in the EEG-based motor imagery BCIs. However, this method has some drawbacks, especially when a few labeled samples are available. The local activities estimation (LAE) method works well with small training sets, but it is more sensitive to the position of the electrodes. Here, we suggest a combination of the LAE and CSP, namely LAE-CSP, which performs better than both methods. In LAE-CSP, the EEG signal passes through regularized CSP and LAE spatial filters after band-pass filtering and then the data dimension are reduced based on the physiological data. Afterwards, the features are extracted using fast Fourier transform (FFT). In this work, CSP, FBRCSP, EA-CSP, LAE and LAE-CSP, methods were evaluated and compared. Three sets of motor imagery data from BCI competition III and IV along with Cho et al. dataset, including EEG signals from 28 subjects were used in this study. For each dataset, the training set were selected in 21 different sizes. LAE-CSP performs better than all tested methods. Particularly it has good performance using only ten labeled samples per class, with an average accuracy of almost 80 %. LAE-CSP reliably enhances the performance of the motor imagery-based brain-computer interfaces. The LAE-CSP takes advantage of the LAE and CSP and compensates for the drawbacks of both methods. [ABSTRACT FROM AUTHOR]

In this paper, a novel dual-output switched-capacitor (SC) regulator is designed for EEG acquisition. At first, an efficient reconfigurable SC is designed with conversion ratios of 2/3 and 1/4 from 1.3 V input voltage. Reconfigurable SC with pulse frequency modulation (PFM) technique produces two single output voltages of 0.8 V and 0.2 V by changing the digital bit S. Then, a novel algorithm is proposed to produce two output voltages simultaneously and reduce voltage ripple. This SC regulator is self-controlled, and its control digital bits are entirely generated by the control logic circuit. Load current range is proportional to the EEG acquisition, in the range of 5 nA-1 μA and 500 nA-260 μA, for output voltages of 0.2 V and 0.8 V, respectively. The proposed dual-output SC is simulated in TSMC 65 nm CMOS technology and occupies an area of 2.09 mm2. The proposed SC regulator achieves a maximum power efficiency and output power of 92.8% and 193 μW, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a novel design of an 11-transistor SRAM bit-cell with a single-ended structure and memory mini-array with the bit-interleaving architecture support using the gate-diffusion input (GDI) method based on the gate-wrap-around (GWA) CNTFETs technology. The cell core of the suggested design is composed of a robust cross-coupled structure of two asymmetric inverters based on circuit-level methodologies. The proposed bit-cell scheme exhibits significant features such as improved write-ability, read data stability, and reduced leakage/short-circuit power due to the asymmetric write-assist method and inverter gates with stacked transistors, respectively. The simulation analysis has been done based on criteria such as static noise margins (SNMs), power-delay product (PDP), and the electrical quality/yield-based figure of merits (FoMs) in write/hold/read operation cycles. The suggested SRAM bit-cell demonstrates the best results with an average of 9.36 %, 48.53 %, and 22.82 %, respectively, for FoMs against other SRAM bit-cell schemes. The Monte-Carlo simulations in the 16-nm node show better results for the proposed bit-cell in the energy and failure probability per operation cycles than similar designs, with the best performance on average of 27 % and 8 %, respectively. Finally, to investigate the effectiveness of the suggested memory cell in the real application domain, an on-chip scaled power supply memory architecture for storing digital data based on quick response (QR) code using the proposed hardware algorithm is evaluated. Our results certify that the suggested memory array configuration in comprehensive FoMs based on quality and hardware efficiency metrics shows better results than the counterpart memory architecture. [ABSTRACT FROM AUTHOR]

A compact microstrip diplexer for 4G wireless communication systems is proposed in this paper. This diplexer consists of two bandpass filters based on the triangular open loop asymmetric stepped impedance resonator in order to have a small size as well as simple structure. The T-shaped open stub is used for attenuating the undesired modes. Attenuation level for the proposed diplexer is less than 21 dB in the range of 0–10 GHz owing to using this T-shaped open stub. The center frequency of each filter can easily change in the range of 20 MHz through varying the gap length of the resonator without any changes in the whole structure of the diplexer. The result of this is the stability of other parameters like insertion loss, return loss and isolation. This diplexer has a narrow band frequency response that makes it suitable for modern wireless communication systems. Finally, the diplexer is fabricated at 2.30 and 2.55 GHz and measurements demonstrate a good agreement between simulated and fabricated diplexer. [ABSTRACT FROM AUTHOR]

In this paper a bandgap reference (BGR) circuit irrespective of the temperature and the supply voltage variation with very low power consumption is proposed. The proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) generators of the proposed BGR, which has four cores cascaded with each other, are used in order to increase not only the output voltage, but also the output control ability for the temperature and the voltage insensitivity. To combine produced voltage from PTAT and CTAT generator, a weight combination circuit, which uses internal capacitors of transistors, is applied. Due to the fact that all of the transistors in such a topology are worked in sub-threshold region, the power consumption is significantly diminished to 1.58 nW. Also the variation of the temperature from −25 °C to 150 °C, leads to the temperature coefficient about 34.45 ppm/°C. The design simulation is done at 960 MHz frequency in TSMC 0.18 µm CMOS technology with the help of Cadence software. Also the post layout simulation result and the layout of the proposed circuit are presented. The output and the chip area of this BGR are 141.5 mV and 1387 µm 2 respectively. [ABSTRACT FROM AUTHOR]

In this paper a low power consumption regulator has been proposed for ultra high frequency (UHF) RFID tag that has a stable output voltage. The sub-blocks of the regulator are supplied with the elementary stage output of the rectifier. The proposed operational amplifier (OPA) circuit works in class-AB and it is biased by an adaptive biasing circuit. Besides, in the proposed regulator the used bandgap reference (BGR) circuit and the sampling circuit are based on CMOS technology and they have low power consumption. The output of this regulator is 0.81 V that has ±1.5 mV ripple. The values of LIR, PSRR and the efficiency of the regulator are about 7.5 (mV/V), 42.5 dB and 53% respectively. Considering 10 KΩ load, the power consumption of the regulator has been calculated as 147 μW. The operating frequency is 960 MHz and it is simulated in TSMC 0.18 μm CMOS technology. [ABSTRACT FROM AUTHOR]

In this paper, a new compensation technique for the low noise amplifier (LNA) with the high capability and efficiency for low power applications is proposed. The supply voltage and bias of the LNA are near the sub-threshold voltage, which has excellent effect on reducing power consumption. At this voltage level, the gain decreases and the various circuit parameters become extremely sensitive to process, voltage and temperature (PVT) changes. To overcome the problem, a compensating circuit with variable current source to control the LNA bias voltage is used. The output of the compensator circuit is adjusted according to changes in temperature, voltage and five process corners, and produces a variable voltage. The temperature compensator consists of two current sources that produce a current proportional to temperature changes. Regarding process and voltage compensator, according to the state created in the circuit, the appropriate amount of current is injected through the output and finally stabilizes the main parameters of the LNA circuit. In LNA circuit, for proper performance at supply voltage near the sub-threshold and attaining the gain improvement, forward body bias and g m -boosting techniques are employed, respectively. The LNA circuit along with the PVT compensator at supply voltage of 0.35 V, consumes about 567 µW power consumption that here 91 µW is caused by the PVT compensator circuit. In the proposed circuit, the rate of noise figure (NF) and gain (S 21) changes compared to temperature changes in the five corners have decreased by 4.3 and 12.1 times versus LNA with constant bias, respectively. In this case, with 20% changes of V DD , NF and S 21 changes decreased by 23 and 11.35 times, respectively. The results are provided by Cadence software using 65 nm CMOS technology. [ABSTRACT FROM AUTHOR]

• Ultra low power and high input impedance Analog Front End for biosignals acquisition (EEG-ECG-EMG). • Design a novel structure of biomedical LNA to achieve the optimal power, noise, CMRR, and input impedance simultaneously. • Novel biomedical LNA by combining the Fully Differential Difference Amplifier (FDDA) with inverter-based. • Design a low power Programmable Gain Amplifier (PGA). In this paper, a low power and low noise analog front end (AFE) is designed for biosignal acquisition. The first stage is a low noise amplifier (LNA) that is designed by combining the fully differential difference amplifier (FDDA) structure with inverter-based to achieve the optimal power, noise, CMRR, and input impedance simultaneously. Also, to increase the output resistance of the LNA, and subsequently increase the gain without reducing the output voltage swing, the gain boosting technique has been used. To use this structure for biosignals, the second stage is designed as a programmable gain amplifier (PGA). This AFE is reconfigurable for electroencephalography (EEG), electrocardiogram (ECG), and surface electromyography (sEMG) biosignals with variable gain of 71 dB, 56 dB, and 44 dB and bandwidth of (0.9–100 Hz), (1–560 Hz) and (12 Hz–1.5 kHz), respectively. The AFE consumes only 303 nW at 0.8 V supply voltage and confers excellent input impedance of 250 GΩ and 5.2 GΩ when the chopper is "off" and "on" respectively. The chopper method has been used and the total integrated input-referred noise is obtained, 1.4 μ V rms . The proposed AFE is simulated in TSMC 65 nm CMOS technology and occupies an area of 0.16 m m 2. [ABSTRACT FROM AUTHOR]

The novel design of asymmetric single-ended ten-transistor SRAM bit-cell (SE 10T-SRAM) using gate-all-around (GAA) carbon nanotube (CNT) FETs-based GAA CNT-GDI method along with dual-chirality technique for CNTs, the asymmetric write-assist and built-in read-assist schemes in the presence of more saving area and less energy consumption is suggested for portable/mobile multimedia applications. Based on the analytical-compact model, an equation for calculating write-static margin (WSNM) is presented by expressing the degree of dependence of the metric on the power supply voltage variation for the suggested bit-cell structure. The results of extensive simulations to evaluate the proposed bit-cell in single and multi-array structures indicate better static/dynamic noise margins, less sensitivity to process, voltage and temperature (PVT) variations, improvement of basic parameters in the presence of contact length changes, more noise-immunity with scalability at cell supply voltage, and better results in other comprehensive figure of merits (FoMs) parameter compared to nanotechnology-based counterpart circuits with the same number of transistors in the 16 nm technology node. Also, evaluating the proposed structure in the presence of changes in the contact length parameter of other transistors as a contact length sizing-level solution, indicating the achievement of an improved structure in the basic parameters such as static noise margin, power consumption, and energy-delay product (EDP) parameter compared to the default structure with a minimum-sizing contact length. Finally, in order to use the proposed bit-cell in a real application, the suggested structure for storing images based on quick response (QR) code is examined with a link between MATLAB and synopsys H-SPICE simulator tools based on suggested algorithm. The results demonstrate that the suggested bit-cell is with more appropriate and significant results in terms of comprehensive FoMs, in which the evaluations concerning the appropriate accuracy in pixel-by-pixel storage of images based on the peak signal-to-noise ratio (PSNR) and the mean structural similarity index measure (MSSIM) metrics, compared to other well-known counterpart schemes confirms the superiority of the proposed design. Hence, the proposed design can be used for various areas regarding multimedia device applications. [ABSTRACT FROM AUTHOR]

In this paper, a new 10-bit 1.2 GS/s hybrid digital to analog converter (DAC) simulated in 65 nm CMOS technology is presented. The new structure benefits from a combination of a resistor ladder and current sources. By using the resistor ladder, the identical current sources are weighted, which leads to remarkably reduce the number of current sources needed for realization a 10-bit DAC. Post layout simulation results indicate that the spurious-free dynamic range (SFDR) is more than 56 dB over 600 MHz Nyquist bandwidth. The INL and DNL parameters are also obtained better than 0.4 LSB. The proposed DAC dissipates just 7.49 mW power with a single supply voltage of 1.2 V. Also, the occupied area is 0.0071 mm2. [ABSTRACT FROM AUTHOR]

this brief presents a new 11-bit 1.2 ​GS/s hybrid digital to analog converter (DAC) simulated in 65 ​nm CMOS technology. In this new structure, a combination of a resistor ladder and current sources is used to realize the 11-bit DAC structure. The current sources are connected to different nodes of the resistor ladder in a logical way. In this situation, equal current sources make different voltage values. Furthermore, the complicated binary to thermometer decoders are exchanged with the basic digital logics. This new technique remarkably reduces the number of current sources needed for realization an 11-bit DAC and leads to the circuit dissipates just 4.68 ​mW power while the power supply is 1.2 ​V. Also, the occupied area is 0.0061 ​mm2. Post layout simulation results indicate that the spurious-free dynamic range (SFDR) is more than 70 ​dB over 600 ​MHz Nyquist BW. The INL and DNL parameters are also obtained better than 1.2 LSB and 1 LSB, respectively. [ABSTRACT FROM AUTHOR]

The demand for high-performance analog-to-digital converters is pushing toward the utilization of small dynamic comparators with low power consumption, low offset voltage, high speed, and independent input common-mode voltage. In this paper, a new high-speed dynamic comparator is presented, which its delay time is decreased compared to conventional dynamic comparators. In the suggested comparator, a complementary differential pair is utilized in the input to improve the offset voltage and comparison speed. The equations related to the delay time and input referred offset voltage of the proposed structure are derived, and the effective parameters to reduce them are identified. The post-layout simulation results in 65 nm CMOS technology demonstrate that the clock frequency of the proposed comparator can be 6 GHz while the delay time is 42.7 ps. The power consumption is 381 μW when the proposed comparator is supplied with 1.2 V. Also, the occupied area is 141.7 μm2. [ABSTRACT FROM AUTHOR]