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Abstract: Focused ion beam (FIB) and nano-probing were applied for failure analysis of three-dimensional stacked circuits with copper through-silicon-vias between the stacked chips. The failure analysis was done after high temperature storage and thermal cycling tests. Passive voltage contrast in FIB allowed to pinpoint the open sites. FIB cross-sections showed the presence of opens at the bottom of the copper vias. The failure cause was suspected to be an interlayer particle, which was confirmed by optical profilometry. Nano-probing was used on another sample to pinpoint the failure location through the measurement of the local resistance within the daisy chains. The failure was traced out to be related with surface contamination. [Copyright &y& Elsevier]

Abstract: We propose an empirical law correlating the average number of walls and the average diameter in a population of multi-wall carbon nanotubes grown by catalytic chemical vapor deposition. The relationship and its dispersion are derived from the statistical analysis of a database of TEM images of nanotubes collected from more than 60 publications in literature and from our group in the last years. Considering the nanotubes were grown from independent sources in a variety of conditions and tools, it has general validity. The relationship may find applicability in a wide range of fields as it provides a simple model to quickly estimate the number of walls most likely present in a population of nanotubes from only the measure of their average diameter. [Copyright &y& Elsevier]

The epitaxial growth of Si layers on Si substrates in the presence of O atoms is generally considered a challenge, as O atoms degrade the epitaxial quality by generating defects. Here, we investigate the growth mechanisms for Si epitaxy on O atomic layers (ALs) with different O-contents and structures. O ALs are deposited by ozone (O 3 ) or oxygen (O 2 ) exposure on H-terminated Si at 50 °C and 300 °C respectively. Epitaxial Si is deposited by chemical vapor deposition using silane (SiH 4 ) at 500 °C. After O 3 exposure, the O atoms are uniformly distributed in Si-Si dimer/back bonds. This O layer still allows epitaxial seeding of Si. The epitaxial quality is enhanced by lowering the surface distortions due to O atoms and by decreasing the arrival rate of SiH 4 reactants, allowing more time for surface diffusion. After O 2 exposure, the O atoms are present in the form of SiO x clusters. Regions of hydrogen-terminated Si remain present between the SiO x clusters. The epitaxial seeding of Si in these structures is realized on H-Si regions, and an epitaxial layer grows by a lateral overgrowth mechanism. A breakdown in the epitaxial ordering occurs at a critical Si thickness, presumably by accumulation of surface roughness. [ABSTRACT FROM AUTHOR]

Incorporation of source–drain stressors (S/D) for FinFETs to boost the channel mobility is a promising scaling approach. Typically SiGe:B S/D stressors are used for p FinFETs and Si:C:P S/D stressors for n FinFETs. The deposition of such Si:C:P S/D stressors requires a low thermal budget to freeze the C in substitutional sites and also to avoid problems associated with surface reflow of Si fins. In this work, we report the material properties of Si:C and Si:C:P epitaxial layers grown by chemical vapor deposition, in terms of their defectivity and C incorporation as a function of different process conditions. The undoped Si:C layers were found to be defect free for total C contents below 1%. Above this concentration defects were incorporated and the defect density increased with increasing C content. Abrupt epitaxial breakdown occurred beyond a total C content of 2.3% resulting in amorphous layers. P doping of Si:C layers brought down the resistivity and also thicker Si:C:P films underwent epitaxial breakdown. Additionally, the use of nitrogen instead of hydrogen as carrier gas resulted in an increase of the growth rate and substitutional C incorporation both by a factor of two, while the surface defect density reduced. [ABSTRACT FROM AUTHOR]

Abstract: We report on the synthesis of Cu3Ge films by exposing Cu films to germane (GeH4). The process window was established by investigating the influence of the GeH4 partial pressure, the soak temperature, and the soak time on Cu films of different thickness. It is shown that short exposures of germane led to Cu-rich germanides, while an excessive GeH4 supply resulted in a Cu3Ge/Ge mixed phase. The germanidation reaction was found to be selective and required the prior removal of the native Cu oxide by in situ plasma cleaning. X-ray diffraction and transmission electron microscopy showed that the Cu3Ge films were crystalline as deposited in the orthorhombic phase and were textured. The films were homogenous in composition. Thin films consisted of Cu3Ge islands connected by a thin wetting layer. Fully continuous layers were however found for larger film thicknesses. The continuity of the Cu3Ge film was also found to be influenced by the pseudosubstrate: the films were more continuous on TaN/Ta than on SiO2. The electric properties of the Cu3Ge films on both TaN/Ta and SiO2 pseudosubstrates are presented and compared. [Copyright &y& Elsevier]

Abstract: In this paper we present a procedure and software allowing to predict and understand device performance by incorporating two dimensional (2D)-carrier profiles obtained from high vacuum scanning spreading resistance microscopy (HV-SSRM) into a device simulator. We demonstrate the incorporation of quantified SSRM 2D-carrier profiles obtained on p-MOSFETs into a device simulator. The simulated electrical characteristics (based on the measured 2D-carrier profiles) of the device show nice agreement with the experimentally obtained device results, whereas calculations based on process simulations with available advanced calibration showed significant discrepancies. With this approach the difficult and time consuming calibration step of the process simulation can be circumvented and device results can be interpreted directly based on the details of the real 2D-carrier profiles. [Copyright &y& Elsevier]

Abstract: A powerful method to study carbon nanotubes (CNTs) grown in patterned substrates for potential interconnects applications is transmission electron microscopy (TEM). However, high-quality TEM samples are necessary for such a study. Here, TEM specimen preparation by focused ion beam (FIB) has been used to obtain lamellae of patterned samples containing CNTs grown inside contact holes. A dual-cap Pt protection layer and an extensive 5kV cleaning procedure are applied in order to preserve the CNTs and avoid deterioration during milling. TEM results show that the inner shell structure of the carbon nanotubes has been preserved, which proves that focused ion beam is a useful technique to prepare TEM samples of CNT interconnects. [Copyright &y& Elsevier]