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This paper presents designs of ternary and quaternary up/down counters of single and multiple digits using CNTFET. The proposed counters have a special feature of counting in dual mode; up counting and down counting which makes these designs distinct from other existing designs. The proposed counters are designed using ternary/quaternary D flip-flops and a dynamic successor-predecessor circuit. The D flip-flops are built using standard ternary/quaternary inverters (STI/SQI) with an additional reset feature. The proposed dynamic successor-predecessor circuit has the capability of acting either as a successor or as a predecessor circuit based on a control signal. Counter circuits of multiple digits have been achieved with the help of a few additional transistors along with the single-digit counter circuits. All the proposed designs have been simulated in HSPICE using Stanford University's 32 nm CNTFET model and simulation results have been noted. When compared with existing designs, the proposed designs show improvements in power and energy efficiency. [ABSTRACT FROM AUTHOR]

Due to the success of artificial intelligence systems in solving complex problems, these systems have been investigated in many applications. There is an increasing demand for these systems in many new applications. The XNOR-Net, a binary neural network, is a promising candidate for implementing these systems in devices with limited power and hardware resources. Efficient hardware implementation of XNOR-Nets is critical and has been widely investigated in recent research. In this paper, a resource-sharing gate and architecture and a task-scheduling gate and architecture have been proposed. To reduce power consumption, the proposed nonvolatile logic-in-memory gates are designed based on the magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistor (CNTFET) devices. Using the proposed resource-sharing gate for hardware implementation of XNOR-Net minimizes the number of flip-flops, power consumption, PDP, and area by at least 75%, 75%, 60%, and 42%, respectively, as compared to its state-of-the-art counterparts. Also, using the proposed task-scheduling design to implement the XNOR-Net on 2, 4, and 8 datasets, the power consumption is reduced by at least 24%, 54%, and 65%, respectively, compared to its state-of-the-art counterparts. [ABSTRACT FROM AUTHOR]

The appeal of portable electronics, embedded systems, and other smart devices has been steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle the interconnect issues in binary logic. The use of ternary logic reduces the circuit complexity, power consumption in interconnects, and total chip area. The carbon nanotube field-effect transistor (CNTFET) offers some significant features like low leakage power, equal hole and electron mobility, and modulation in threshold voltage by adjusting the diameter of the carbon nanotube (CNT). In this paper, a clocked dynamic and pass transistor logic-based ternary 1-trit multiplier circuit with only 28 transistors has been proposed. The proposed logic avoids the conventional approach of using logic gates, encoder/decoder, and multiplexers, which reduces the total device count to implement the multiplier. The reduced transistor count offers a reduction in power consumption, delay, power-delay-product (PDP), and energy-delay-product (EDP) in comparison to other state-of-the-art designs. Stanford 32-nm CNTFET model file and Synopsis HSPICE simulator have been used to carry out the simulations at a supply of 0.9 V. The proposed circuit shows a 34.16 %, 66.44 %, and 82.80 % reduction in power, PDP, and EDP as compared to the lowest power, delay, and PDP of the designs under consideration. The performance of the multiplier is evaluated under different temperatures, supply voltages, loads, and oxide thickness. [ABSTRACT FROM AUTHOR]

The complexity of digital circuits is constantly rising. Analog computing can be an excellent alternative to overcome the complexity issue. Operational Amplifiers play a serious role in many analog circuit designs. This paper presents a new implementation approach to an analog subtractor. This design enjoys high speed and low power dissipation using Carbon Nanotube FETs (CNTFETs). We have also achieved a significant improvement in terms of the number of transistors and chip area. The proposed design considerably decreases power consumption and optimizes the chip area. The same performance can be achieved when designing a high-quality Differentiator. It is to remark that there is no need to use a huge number of resistors and capacitors. In this design, no additional voltage or current sources have been used. HSPICE and the Stanford 32 nm CNTFET model are used to simulate the proposed circuit. The comparisons with State-of-the-art prove the performance of this design. [Display omitted] [ABSTRACT FROM AUTHOR]

Multiple-valued logic (MVL) circuits reduce the complexity of connections, thereby decreasing power consumption and chip area. In the recent years, many studies have been conducted on multiple-valued logic due to the high potentials of carbon nanotube transistors in designing these circuits. (MVL) circuits have less noise margin in comparison to the binary ones because of the adjacency of the levels. In this paper, the quaternary logic gates were designed using a novel structure and two separated paths with diode connection to generate '1' and '2' logic levels. This allowed the better adjustment of parameters, increased noise margin, and reduced the power consumption in the '1' and '2' logic levels. A new method was also developed to design quaternary combinational circuits; this method was implemented in the full adder circuit. The designs were simulated using the HSPICE software and the 32 nm Stanford CNTFET model. The simulation results indicated significant improvements in terms of power consumption, PDP, and noise margins in the new model, as compared to the prior works. The PDP improvements were about 79% and 63% for the proposed buffer and SQI gates, respectively, while it was 70% for the quaternary full adder design, as compared to the best single supply-based work reported so far. Also, noise margins were improved in the proposed buffer, getting close to an ideal noise margin of about Vdd/6. [ABSTRACT FROM AUTHOR]

In this paper, a novel method is presented for the accurate extraction of key parameters of carbon nanotube field-effect transistors (CNTFETs) using S-parameter measurements. An equivalent circuit model, which utilizes lumped components based on the physical characteristics of the device, is employed to model the AC behavior (S-parameters) of the CNTFETs. The proposed method extracts the bias-dependent contact resistance, channel resistance, and gate-channel capacitance from the model at each gate voltage, thereby facilitating the extraction of the effective mobility of the CNT channel. At the last part of this paper, this method is used to quantitatively investigate the impact of electrostatic doping on CNTFETs. This new methodology offers an effective approach for characterizing CNTFETs, which is an important indicator for device optimization. Additionally, the proposed method can be easily applied to other types of FETs. [ABSTRACT FROM AUTHOR]

In the following paper, a single bit ternary multiplier utilizing carbon nanotube field-effect transistor (CNTFET) has been presented. Almost in the ternary circuit design, only one supply voltage V DD is used and a voltage division circuit is activated to produce V DD /2 for logic ‘1’, So the direct current from V DD to ground increases the static power considerably. In This paper, using two supply voltages, V DD and V DD /2, the circuit is designed so as V DD /2 could be transmitted to output directly for logic ‘1’ to eliminate direct current from source to ground. This is provided by proper division of truth table and using two level output gates. Also for extending to multi bit multiplier in this way, three type of half adders and one full adder are designed using two supply voltages and removing direct current. The implementation for two bits is reported. The results of simulation, using Hspice software and Stanford 32 nm CNTFET library with the voltage of 0.9 (v), as expected, indicate much lower power dissipation and power delay product (PDP) in comparison with the previous works. [ABSTRACT FROM AUTHOR]

In this paper, a new high-precision, pressure sensor for sensing gas molecules using a controllable voltage-mode instrumentation amplifier (VMIA) in carbon nanotube field-effect transistor (CNTFET) technology is designed. The sensing mechanism is based on the applied force by Oxygen atoms on the surface of the carbon nanotube (CNT), which is considered as a movable electrode of sensing capacitor. The sensing mechanism is simulated in ANSYS which justifies the variations of sensing capacitance, while the sensor’s output voltage is applied to an accurate instrumentation amplifier (IA) via a switched-capacitor sensor driver. Therefore, due to the controllability of the transconductance and gain parameters of a CNTFET, the IA circuit provides a constant and controllable differential gain of up to 52 dB in a flat −3dB bandwidth of up to 3.6 MHz, which provides a tunable common-mode rejection ratio (CMRR) of up to 121 dB in a 1.8 GHz flat, −3dB frequency bandwidth. Moreover, due to the use of the differential pair stage, the total harmonic distortion (THD) value is obtained less than 0.67%. Finally, the proposed IA circuit consumes only 45.1 µW with a 22.52 nV/√Hz equivalent input referred noise value at ±0.5 V supply. [ABSTRACT FROM AUTHOR]

Presently, the battery life and high spectral efficiency are found to be a perennial problem in smartphones. With the advancement in the technologies towards 5 G, it has become mandatory to meet these challenges before problems are aggravated. Besides, CNTFET technology is found to be a promising field of research that is recommended in this review to solve these problems. The intention of this study is to provide an overview of most recent research on the state-of-the-art of CNTFETs. Several papers were reviewed that include the device modeling, simulation, device fabrication and its applications. However, the majority of these papers were observed to deal with digital applications, while the papers related to analog applications were limited. Moreover, this review provides the information regarding the results obtained from the device circuit performance and the scope for future prospects. [ABSTRACT FROM AUTHOR]

Multilevel electronic systems offer the reduction of implementation’ complexity, power consumption, and area. Ternary system is a very promising system where more information is represented in the same number of digits compared to the binary systems. In this paper, ternary logic gates and some of their ternary circuit applications are presented using memristors and CNTFET inverter. This integration between memristors and CNTFET offers low static power, small area and high performance. The proposed circuits do not require refreshment like the previously published circuits and are not initial state dependent because the memristors switch between the low resistance and high resistance states according to each input. In addition, we investigate the mathematical analysis of the proposed memristor ternary logic gates circuits. In the circuit simulations, a VTEAM model is used to verify the proposed circuits. Finally, a comparison between the proposed circuits with the previously published implementations is discussed showing better performance in terms of power, delay and area. [ABSTRACT FROM AUTHOR]

This paper presents three new power-efficient designs of ternary SRAM using carbon-nanotube-field-effect-transistors (CNTFETs). Two of the proposed ternary SRAM designs are cycle-operator based and the third design is buffer-based. The cycle operators and buffer used in the design of the proposed ternary SRAM consume low power as they use two power supplies for operation. Ternary logic implementation using CNTFETs is largely being used lately due to the advantages it provides in terms of reduced interconnect complexity and chip area. The proposed ternary SRAM designs are compared with the existing designs using HSPICE simulations that use a standard Stanford CNTFET model. All the three proposed designs show considerable improvement in power consumption for read and write operations than their existing counterparts in literature. The read, and write delays and noise margins of the proposed designs are also analysed and are found to be comparable to the existing designs. [ABSTRACT FROM AUTHOR]

Many researchers are working to develop a static random access memory (SRAM) cell that uses low power, has good stability, better I o n / I o f f ratio and speed. This paper presents a single sided Schmitt-trigger driven read decoupled 12 transistors (STRD 12T) carbon nanotube field-effect transistor (CNTFET) SRAM cell with controlled power gating approach. The Schmitt-trigger (ST) inverter along with power gating and read decouple approach has low power, good read and write delay, better stability and I o n / I o f f ratio. The stacking effect reduces the leakage power of the proposed cell. The proposed STRD 12T SRAM illustrates the maximum reduction in static power consumption, write delay, read delay, and maximum improvement in I o n / I o f f ratio is 1544.34, 112.37, 1.40, and 8107.88 times respectively, than the considered SRAM cells. The simulation is performed with Cadence Virtuoso utilizing the 32 nm CNTFET model from Stanford University. [Display omitted] • It employs single bitline structure which reduces dynamic power consumption. • It employs read decoupled technique to enhance RSNM. • The use of ST inverter and controlled power gating technique improves write delay. • It uses stacked transistors which lower leakage power and increase I o n / I o f f ratio. [ABSTRACT FROM AUTHOR]

This paper presents a new design of three-valued logic gates on the basis of carbon nanotube transistors. Next, the proposed circuit is compared with the existing models of circuits. The simulation results, using HSPICE indicate that the proposed model outperform the existing models in terms of power and delay. Moreover, using load-transistor results in 48.23% reductions in terms of power-delay-product (PDP) compared with the best model ever observed. Furthermore, the implementation of ternary arithmetic circuits such as half adder and multiplier using load-transistor has been investigated. An added common term between Sum and Carry output in half-adder (HA) and Carry and Product output in lower multiplier (MUL) has been used in arithmetic circuits. Considering the fact that a better proposal with higher performance has been utilized for the implementation of three-valued gates, our model results in the reduction of 9.95% and 23.87% PDP in HA and MUL respectively compared with the best models observed. [ABSTRACT FROM AUTHOR]

The emergence of multi-valued logic (MVL) is a substitute to binary logic approaches for realizing high-information density logic systems and high-operating speed systems. In this paper, a design for standard ternary inverter (STI), ternary NAND (TNAND), ternary NOR (TNOR) using carbon nanotube field effect transistors (CNTFETs) is proposed in which a p-type dynamic diode is used with the goal of lowering the energy consumption expressed as power delay product (PDP) and thereby reducing battery usage. Additionally, the basic arithmetic operations are then performed using proposed ternary logic circuits, which can be extended to realize more complex operations. The proposed designs are simulated in HSPICE using a 32 nm Stanford CNTFET model. With respect to variation in process parameters, the reliability of the proposed STI circuit is examined. Simulation results verify that the proposed designs show improvement in terms of power consumption and power delay product (PDP) compared to the other CNTFET based ternary logic circuits. Moreover, less variations are observed in power and PDP of the proposed logic gates with variation in process parameters, capacitance, temperature, frequency and supply voltage. The proposed circuit designs of STI, TNAND, TNOR, ternary half adder (THA), ternary multiplier (TMUL) show 78 %, 98 %, 99 %, 99 %, 99 % improvement in PDP respectively, as compared to the conventional CNTFET based circuit designs and 99 % PDP improvement in all proposed circuits compared to CNTFET based logic circuits with resistive load. [ABSTRACT FROM AUTHOR]

Carbon nanotube field effect transistor (CNTFET) is swiftly becoming an alternative to conventional CMOS transistors due to superior transport properties, improved current handling characteristics, and better gate control. This work presents a new Carbon nanotube field effect transistor (CNTFET) based low power, stable static random access memory (SRAM) cell design with reduced write delay. The proposed eight-transistor (8T) CNTFET-based SRAM cell improves read/write static noise margin by 1.98 × /1.25 × , respectively, at 0.3 V compared to conventional 6T SRAM that uses similar CNTFET parameters. The write access time and leakage power of the proposed cell are improved by 1.90 × and 2.14 × , respectively, compared to the conventional 6T design. The proposed design parameters are also compared with two already presented 8T SRAM cells. The simulation is performed with the Cadence Virtuoso using the Stanford University 32 nm CNTFET Verilog model. [ABSTRACT FROM AUTHOR]

Ternary logic has been investigated for several years as it can provide substantial advantages in reducing the complexity of operations and the number of interconnects. On the other hand, with the advancement of technology and the reduction of the feature size and supply voltage, the sensitivity of memory elements to radiation effects has increased. In this paper, a robust ternary SRAM (TSRAM) cell is designed using a novel ternary C-element based on carbon nanotube field-effect transistors (CNTFETs). Besides, a 2m×2n ternary memory array architecture is designed and simulated based on the proposed TSRAM cell. Unlike the previous TSRAM cells, our proposed cell is hardened against radiation effects caused by high-energy particle strikes, which is a significant achievement in ternary memory design. Our extensive simulations demonstrate that the proposed radiation-hardened TSRAM offers up to 77× higher critical charge and up to 98 % higher SNM at the cost of 47 % to 65 % area overhead. It is also noteworthy that the proposed design only needs only two threshold voltages. Moreover, the proposed TSRAM is robust against the process and temperature variations. Our results emphasize that the proposed design is a milestone for designing high-performance, radiation-hardened, and robust ternary memory chips. • This paper presents a robust ternary SRAM cell using a novel CNTFET-based ternary C-Element. • A 2m×2n ternary memory array architecture is designed and simulated based on the proposed cell. • Unlike the previous TSRAM cells, our proposed cell is hardened against radiation effects caused by high-energy particles strikes. • The proposed design is a milestone for designing high-performance, radiation-hardened, and robust ternary memory chips. [ABSTRACT FROM AUTHOR]

Three different methods for the extraction of the contact resistance based on both the well-known transfer length method (TLM) and two variants of the Y-function method have been applied to simulation and experimental data of short- and long-channel CNTFETs. While for TLM special CNT test structures are mandatory, standard electrical device characteristics are sufficient for the Y-function methods. The methods have been applied to CNTFETs with low and high channel resistance. It turned out that the standard Y-function method fails to deliver the correct contact resistance in case of a relatively high channel resistance compared to the contact resistances. A physics-based validation is also given for the application of these methods based on applying traditional Si MOSFET theory to quasi-ballistic CNTFETs. [ABSTRACT FROM AUTHOR]

This paper presents a new ternary operator for cyclic redundancy check in ternary logic with high hardware efficiency. It shows the essential properties of a ternary operator for calculating CRC. Gate-level implementation of CRC-16 is exemplified and comprehensively explained in this paper. Transistor-level realizations of the new and the previous operators are also given in full detail. This paper demonstrates that the employment of the proposed operator reduces hardware components such as the elimination of one entire operator in both transmitter and receiver sides in comparison with ternary SUM . In addition, simulation results by HSPICE and 32 nm CNTFET technology shows about 20.6% energy reduction for one of the implementation methods of the proposed operator with respect to the previously presented one ( CCW CYCLE ). Furthermore, five fewer transistors are needed to design the proposed operator in contrast with both operators SUM and CCW . [ABSTRACT FROM AUTHOR]

Two novel ternary CNTFET-based SRAM cells are proposed in this paper. The first proposed CNTFET SRAM uses additional CNTFETs to sink the bit lines to ground; its operation is nearly independent of the ternary values. The second cell utilizes the traditional voltage controller (or supply) of a binary SRAM in a ternary SRAM; it consists of adding two CNTFETs to the first proposed cell. CNTFET features (such as sizing and density) and performance metrics (such as SNM and PDP) and write/read times are considered and assessed in detail. The impact of different features (such as chirality and CNT density) is also analyzed with respect to the operations of the memory cells. The effects of different process variations (such as lithography and density/number of CNTs) are extensively evaluated with respect to performance metrics. In nearly all cases, the proposed cells outperform existing CNTFET-based cells by showing a small standard deviation in the simulated memory circuits. [ABSTRACT FROM AUTHOR]

In this paper energy-efficient multiple valued logic (MVL) circuits based on carbon nanotube field effect transistor (CNTFET) are proposed. These circuits are designed based on the unique properties of CNTFETs, such as having same mobility for electrons and holes and also capability of adopting desirable threshold voltage by adjusting the CNTs diameters. The proposed designs have high driving capability, larger noise margins and higher robustness as compared to the previous CNTFET-based designs. The proposed quaternary circuits are examined using HSPICE simulator with the standard CNTFET technology. Simulation results demonstrate more energy-efficient and robust operation of the proposed designs, as compared to the other state-of-the-art CNTFET-based MVL circuits, recently presented in the literature. According to the simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45% lower power-delay product (PDP), respectively as compared to their state-of-the-art counterparts. In addition, the proposed QNOT, QNAND and QNOR circuits have the average PDP improvements of 79%, 42% and 61%, respectively, as compared the other recently presented CNTFET-based quaternary designs. [ABSTRACT FROM AUTHOR]

This paper presents different low-leakage power Carbon NanoTube FET (CNTFET) based SRAM cells at nano technology. These SRAM cells are obtained by applying different circuit level leakage power reduction techniques called Sleep transistor, Forced stack, Data-Retention sleep transistor and Stacked sleep. All these cells are designed and simulated to assess their performance. All these techniques are compared in terms of leakage power, dynamic power, read delay, write delay, SNM and Area. Among all the SRAM cells, stacked sleep CNTFET SRAM cell is best in terms of leakage power saving with state saving capability. [ABSTRACT FROM AUTHOR]

Carbon nanotubes have some unique features and special properties that offer a great potential for nano-electronic devices. In this paper, we have analyzed the effect of chiral vector, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage of CNTFET over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as of MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime especially when the gate length is around 10 nm; which is quite contrary to the well known short channel effects in MOSFET. It is observed that at or below 10 nm channel length the threshold voltage increases rapidly in case of CNTFET device whereas in case of MOSFET device the threshold voltage decreases drastically. [ABSTRACT FROM AUTHOR]

Many researchers are trying to create a low power, high stability, and high-speed static random access memory (SRAM) cell. This paper introduces an SRAM cell consisting of 12 transistors (12 T) developed by carbon nanotube field-effect transistor (CNTFET) to support such an endeavor and be a milestone in creating a better SRAM cell. The proposed 12 T CNTFET SRAM cell is a modified Schmitt-trigger (ST)-based SRAM cell design. The ST-based SRAM cell feedback-cutting and single-ended read decupled techniques are introduced to improve the SRAM cell's static noise margin (SNM) and access time. The presence of stacked N-CNTFETs reduces the proposed cell's power consumption. In addition to conventional 6 T [9] and 8 T [10] SRAM cells, it has been compared with some of the existing SRAM cells such as 12 T SRAM [11] , 12 T SRAM [12] , 12 T SRAM [13] and 12 T SRAM [14] , for calculating the relative performance of the proposed 12 T CNTFET SRAM cell design in terms of fundamental design metrics. The simulation results at 0.9 V show that compared to the afromentioned bit cells, the proposed design accomplishes low power consumption while writing, reading, and holding modes of operation. It has a high SNM during all the operations. The proposed cell has the least read access time. The power, SNM, and access time performance of the bit cells are evaluated for the variation of CNTFET parameters and reported in this article. The proposed cell is also implemented using MOSFET, and the performance of MOSFET and CNTFET is compared. The simulation is done with the HSPICE simulation tool using the Stanford University 32 nm CNTFET model. [ABSTRACT FROM AUTHOR]

• It is proposed the approximate current mode adder circuits as binary converters based on CNTFET technology. • The simulation results show reduced power consumption, reduced delay and improved PDP and EDP. • The approximate current mode adder circuit based on CNTFET using three-value logic was a suitable solution for high-speed and high-performance VLSI nanotechnology systems. In this paper, the approximate current mode adder circuit was proposed using CNTFET technology based on ternary value logic. This design was evaluated relying on binary converters and HSPICE simulator and it used the standard 32 nm CNTFET technology. In addition, by using the HSPICE tool, the parameters such as power consumption, delay, PDP, and EDP were estimated. The simulation results were shown to reduce power consumption and delay, and improve PDP and EDP. Due to the importance of data security, the performance of the approximate current mode adder circuit using image encryption algorithms based on chaotic systems has been investigated by MATLAB software. Analysis of the approximate adder circuit performance in the image encryption was indicated an increase in system speed, security, and reduced power consumption. Simulation and encryption results indicate the supremacy of the proposed circuit compared to others. [Display omitted] [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) have been seen as a potentially future material to provide an ultrasmall device (CNTFET (Carbon Nanotube Field Effect Transistor)). Therefore, the studies of sub-bands effects are needed in order to find the enhancement of carrier transport in CNTFET. Also in this paper the band structure of the rolled-up nanotube can be obtained by zone-folding from the band structure of the graphene sheet. This method is used in this work and we simulated and analyzed the band structure of carbon nanotube. We present analytical modeling of carrier concentration in a zigzag semiconducting of carbon nanotube field effect transistor (CNFET) using the dispersion relation E ( k ) (the first three sub-bands) and given the density of states (DOS), the carrier concentration is obtained based on a numerical method as an alternative to the usual Fermi–Dirac integrals. In order to find the influence of the first three sub-bands energy and diameter d t of CNT in non-degenerate and degenerate region of the carrier concentration in CNTFET. The results obtained showed that the diameter and the energy of sub-band have a significant impact on the carrier concentration of CNTFET. [ABSTRACT FROM AUTHOR]

Electrical stress and 10-keV X-ray irradiation and annealing responses are evaluated for carbon nanotube field effect transistors for nonvolatile memory applications. Less than 3% change in the drain current is observed during constant-voltage stress. Irradiation and annealing under positive gate bias induces more degradation in both drain current and memory window than under negative bias. Cycling of the on/off state leads to significant degradation in the memory window. [ABSTRACT FROM AUTHOR]

This paper deals with the tests of carbon nanotube field effect transistors (CNTFETs) for gas sensing applications, exploiting an original sensing technique to dramatically improve selectivity. Such devices exploit the extremely gas-sensitive change of the Schottky barrier heights between carbon nanotubes (CNTs) and drain/source metal electrodes. This effect is at the origin of the change of the CNTFET transfer characteristics. Indeed the main effect is related to the gas adsorption creating an interfacial dipole that modifies the Fermi levels alignment and so the bending and the height of the Schottky barrier at the contacts with the CNTs. This change is strictly dependent on the metal/CNTs junction and on the gas involved. We have fabricated on the same chip an array of four CNTFETs composed of four different metals (Pd, Pt, Au, Ti) as electrodes and we have demonstrated that each CNTFET interacts in a very specific way, identifying a sort of electronics fingerprinting. This array has been tested after exposure to NO2, NH3 and di-methyl-methyl-phosphonate (DMMP, a sarin gas simulant) with gas concentrations varying from 10 ppb to 10 ppm using air as gas carrier. [ABSTRACT FROM AUTHOR]

Abstract: The effects of lightly doped drain and source (LDDS) and hetero-material-gate (HMG) structure on the static characteristics and switching speed performance for a carbon nanotube field effect transistor (CNTFET) have been theoretically investigated by a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green׳s functions (NEGF) solved self-consistently with Poisson׳s equation. A comparison study of electrical characteristics in conventional single-material-gate CNTFET (C-CNTFET), LDDS-CNTFET, HMG-CNTFET and LDDS-HMG-CNTFET structures has been performed. Simulations show that, compared with the other structures, LDDS-HMG-CNTFET significantly decreases leakage current, subthreshold swing, and increases on/off current ratio. In addition, effects of the gate electrode work function of the LDDS-HMG-CNTFET have been studied theoretically. The results indicate that the electron transport efficiency, and the cutoff frequency of the device, can be optimized by reasonably selecting the gate electrode work function. This work illustrates that the proposed LDDS-HMG-CNTFET might be useful for low-power high-speed CNTFET digital design. [Copyright &y& Elsevier]

Abstract: Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32nm CNTFET technology at various realistic conditions such as different power supplies, load capacitors, frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even in the presence of PVT variations. In addition, new noise injection circuits for ternary logic are also presented to perform noise immunity analysis. [Copyright &y& Elsevier]

Abstract: In this paper, we propose new universal designs of ternary-valued logic (TVL) with high-speed, low-power and full swing output using carbon nanotube FETs (CNTFETs). All of the TVL functions (39 functions) can be implemented in these designs. Ternary value logic is a promising alternative to binary logic due to the reduced integrated circuit (IC) interconnects and chip area. Therefore, a universal design of TVL is a good direction for the future of FPGA design using CNTFET. In this paper, new universal designs of ternary-valued logic based on CNTFETs are proposed and compared with the existing resistive-load CNTFET universal TVL designs. Extensive simulations have been performed in HSPICE to investigate the distribution of power consumption and the delay of the CNTFET-based universal cells due to variations in the supply voltage, the diameter of the CNT, and the room temperature. Simulation results show that the proposed universal TVL designs result in significantly lower power consumption and delay compared with previous resistive-load CNTFET universal TVL implementations. [Copyright &y& Elsevier]

Abstract: SPICE compatible CNT interconnect and CNTFET models in Verilog-A hardware description language are presented in this paper. Metallic CNTs are shown to have current saturation characteristics above a threshold voltage and then modelled with piecewise linear functions. On the other hand, the CNTFET model developed utilizes the calculation of the self-consistent potential of the CNT channel depending on gate and drain voltages. Unlike the previous SPICE-enabled CNTFET models using approximations and curve fittings, the proposed model employs a self-consistent method for the calculation of the channel potential in SPICE, providing more accuracy. The versatility of the CNT interconnect model and that of the CNTFET model are shown in CNT circuit simulations. [Copyright &y& Elsevier]

Abstract: Carbon nanotube field-effect transistors (CNTFETs) can be fabricated with Ohmic- or Schottky-type contacts. We focus here on Ohmic CNTFETs. The CNTFETs suffer from band-to-band tunneling which in turn causes the ambipolar conduction. In this paper, to suppress the ambipolar behavior of CNTFETs and improve the performance of these devices, we have proposed application of symmetric double-halo (DH)-doping in CNTFETs. In this new structure, the source-side halo doping reduces the drain-induced barrier lowering (DIBL) and the drain-side halo reduces the band-to-band tunneling effect. Simulation results show in the DH-CNTFET, subthreshold swing below the 60mV/decade conventional limit can be achieved. Also it decreases significantly the leakage current and drain conductance and increases on–off current ratio and voltage gain as compared to conventional CNTFET. [Copyright &y& Elsevier]

Abstract: In this paper we present recent studies concerning gas sensors based on carbon nanotube field effect transistors (CNTFETs). Although these devices have allowed one to realize sensors with an impressive sensitivity compared to existing technologies, the physical interpretation of the interaction between the gas molecules and the CNTFETs has not been clarified yet. In this contribution, we try to find some consistency between the physical interpretations advanced by the different scientific teams working on the subject and to answer some unsolved questions. Moreover, considering that the selectivity is the main issue, we analyze the different routes that have been proposed to overcome this problem: functionalization using polymers, diversification of the source/drain metal electrodes, metal decoration of SWCNT mats, exploitation of the desorption time of the different gases. For each technique we try to evaluate the advantages and the drawbacks. [Copyright &y& Elsevier]

Abstract: For the first time, a new type of carbon nanotube field-effect transistor (CNTFET), the dual material gate (DMG)-CNTFET, is proposed and simulated using quantum simulation that is based on self-consistent solution between two-dimensional Poisson equation and Schrödinger equation with open boundary conditions, within the nonequilibrium Green''s function (NEGF) framework. The proposed structure is similar to that of the conventional coaxial CNTFET with the exception that the gate of the DMG-CNTFET consists of two laterally contacting metals with different work functions. Simulation results show DMG-CNTFET significantly decreases leakage current, drain conductance and subthreshold swing, and increases on–off current ratio and voltage gain as compared to conventional CNTFET. We demonstrate that the potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed short-channel effects like the drain-induced barrier lowering (DIBL) and hot-carrier effect. [Copyright &y& Elsevier]

Abstract: For the first time, we present a scaling study of carbon nanotube field-effect transistors (CNTFETs) using a two-dimensional model. We investigate the scaling issues in device performance focusing on transconductance characteristics, output characteristics, average velocity, I on/I off ratio, subthreshold swing and drain-induced barrier lowering (DIBL) with different gate oxide thicknesses and carbon nanotube (CNT) diameters. We concluded that the I on/I off ratio increases with the gate oxide thickness reduction and increase in the CNT diameter and lead to a high on-state current. Furthermore, leakage current reduces with decrease in the gate oxide thickness, but it becomes higher in CNTFETs with larger CNT diameter. Also, our results show the output conductance, transconductance, voltage gain and average electron velocity at the top of the barrier improve in CNTFETs with thinner gate oxide and larger CNT diameter. In addition, the investigation of short channel effects shows that CNTFETs with thinner gate oxide offer lower DIBL and subthreshold swing, but in the CNTFETs with larger CNT diameter DIBL and subthreshold swing become worse. [Copyright &y& Elsevier]

Abstract: For the first time, the impact of single halo (SH) implantation on the carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions has been investigated using quantum simulation. The simulations are based on the self-consistent solution of the two-dimensional Poisson–Schrödinger equation, within the non-equilibrium Green''s function (NEGF) formalism. The results show SH-CNTFET decreases significantly leakage current and drain conductance and increases on–off current ratio and voltage gain as compared to conventional CNTFET. It is seen that short-channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. [Copyright &y& Elsevier]

Abstract: We present a study of carbon nanotube field effect transistors (CNTFET) operation and performance using Monte Carlo simulation including phonon scattering. In CNTFETs, operating in the quantum capacitance regime, the low driving electric field in the channel yields a high fraction of ballistic transport. In terms of ballisticity, I ON/I OFF ratio and intrinsic delay, the performance of 100nm-long CNTFET is shown to be as high as that of much smaller Si transistors. [Copyright &y& Elsevier]

Ternary number system offers higher information processing within the same number of digits when compared to binary systems. Such advantage motivated the development of ternary processing units especially with CNTFET which offers better power and delay results compared to CMOS-based realization. In this paper, we propose a variety of circuit realizations for the ternary memory elements that are needed in any processor including ternary D-latch, and ternary D-flip-flop. These basic building blocks are then used to design a ternary register file with multiple read and write ports. This paper is an attempt to investigate the performance aspects of using ternary RF to open the gate of more contributions and research in the direction of full ternary computer architecture. The proposed designs have been compared in terms of power, area, and latency at different supply voltages and operating temperatures. [ABSTRACT FROM AUTHOR]

This paper presents a CNTFET based ultra-low-power ternary SRAM design which consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as compared to the other CNTFET ternary SRAM designs reported in the literature. The 6-Transistor (6T) Standard Ternary Inverter (STI) cell or the 3T-STI cell form the basic building block of the conventional SRAM cells. These conventional STI designs have an undesirable direct path between V DD and ground during certain ternary input signals, resulting in higher power consumption. In this paper, a highly power-efficient 4T-STI based Ternary SRAM design is presented, which prevents a direct path between the power supply V DD and ground in all the possible ternary logic states. While CNTFET is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed ultra-low-power ternary SRAM design has been implemented with both 32 nm CNTFET and 45 nm CMOS devices. The performance of both the CNTFET and CMOS based ultra-low-power ternary SRAM circuits have been benchmarked with corresponding conventional SRAM circuits. The overall decrease in Power Delay Product (PDP) is 86–97% in the proposed ultra-low-power ternary 32 nm CNTFET SRAM circuit and 87–99% in the proposed 45 nm CMOS SRAM with respect to corresponding conventional ternary SRAM circuits. [ABSTRACT FROM AUTHOR]

In this paper, a novel method has been proposed to implement a Carbon Nanotube Field-Effect Transistor (CNTFET) based with 8T SRAM cells 32 at nm technology and triple-value transistor memory cell. Instead of using a read buffer and a transmission gate, we have used a tri-state buffer, this reduces cell standby power. We have also used dynamic diode connection to implement the standard tri-state inverter (STI) gate instead of a transistor with a static diode connection. Then, the proposed memory cell, unlike the memory cell, is off while holding data 0 and 2 off, has been compared with a memory cell, simulation results using the HSPICE circuit simulator show that the cell stability has increased by 23.03% due to the use of dynamic diode connection transistors and, 14.36% of data storage power consumption "0″ and 32.15% data storage power consumption "2″ is reduced due to the use of tri-state buffer. Also, the proposed memory cell provides a good SNM in a supply voltage range from 0 to 0.9 V, and also this scheme has a stable read and writes stability due to the variation diameter between the smallest squared inscribed between two VTC curves in the butterfly diagram. [ABSTRACT FROM AUTHOR]

In recent decades, due to the problems with the use of MOSFET transistors in Nanoscale, various alternatives have been introduced. Among them, CNTFET transistors are much more attractive due to their structural and behavioral similarities to the MOSFET transistors. Besides, using binary logic has made some issues that can be solved by applying multiple-valued logic. CNTFETs are also more suitable than MOSFETs in MVL circuits since their threshold voltage can be changed through a change of nano diameter. In this article, newly quaternary half-adder and single-digit multiplier through applying CNTFET technology based on the newly decoder and multiplexer are presented. Simulation of proposed designs is done with Synopsys HSPICE using 32 nm Stanford compact model. The functional results indicate the correct and perfect operation of all designs. Also, compared to some recent designs in literature, obtained 81.34% and 74.07% improvement in PDP for the half-adder and the multiplier designed, respectively. The simulation results under various load capacitors, supply voltage, process variations, frequency, and temperature confirm the stable operation of proposed designs. [ABSTRACT FROM AUTHOR]

This paper presents a new design for the implementation of Vedic mathematics based discrete wavelet transform for biomedical signal processing. The design of the low power architecture using alternate devices is the background of the work. The DWT architecture consists of the adder, multiplier, Multiply Accumulate (MAC) unit and RAM or ROM to store the co-efficients. The existing Complementary Metal Oxide Semiconductor based design suffers from leakage. The proposed FinFET and CNTFET technology will overcome the problem faced in CMOS technology. The processor core of the system on chip (SoC) designed using Vedic mathematics sutras. The efficiency of Vedic mathematics and advances of low power VLSI is combined in this paper. The CNTFET design reduces the power by about 95% and has controllability of the threshold voltage. The design is carried out in 32 nm FinFET technologyThe design is mainly focused on the complete Processor Core block implemented using a MAC with a Vedic multiplier using FinFET technology. The experiments were carried out using Synopsis HSpice. [ABSTRACT FROM AUTHOR]

In recent years, carbon nanotube FETs with their astounding electrical properties have been in the spotlight of nanoelectronics designers. Therefore, they have introduced as a promising candidate for VLSI applications. The aim of this work is to represent a robust energy-efficient SRAM cell based on wrap-gate CNTFET transistors. The proposed SRAM cell has been designed in a particular way that mitigates the need to utilize complex bit-conditioning circuitries to precharge the bit-lines during operations. Moreover, the proposed design utilizes high-threshold voltage multi-tube CNTFET transistors which are biased in the near-threshold region to achieve a power-efficient and a reasonable data transfer speed rate operation. To benchmark the functionality of the proposed SRAM cell, performance parameters including power, delay, etc. have been evaluated through rigorous simulations. The simulation results demonstrate that the proposed SRAM consumes 14.59 pW and 1.25 nW static and dynamic powers respectively (@ V dd = 0.5 V). The proposed design has 180 mV and 340 mV read and write static noise margins respectively and no failure has observed up to 5000 times repetition in Monte Carlo simulations. Based on the simulation results, the proposed CNTFET-based SRAM cell has the potential to be exploited as the basic platform for modern high-performance large memory arrays. [ABSTRACT FROM AUTHOR]