Search

In this paper, we present, for the first time, a detailed investigation of the drain current local variability in advanced n-MOS devices from 28 and 14 nm FDSOI technology nodes. A simple MOSFET compact model is built to reproduce the local variability I d – V g characteristics of paired transistors using a Monte Carlo simulation with normally distributed MOSFET parameters ( V th , β and R sd ). [ABSTRACT FROM AUTHOR]

Highlights: [•] Low frequency noise and its variability through CMOS planar bulk technologies. [•] Evolution with technology generation of oxide trap density as a function of EOT. [•] Improvement of LFN statistical variability with decrease of EOT. [Copyright &y& Elsevier]

Abstract: A detailed characterization and modeling of the low frequency noise in a CMOS inverter is presented for the first time. A low frequency noise model for the load current and the output voltage is developed based on the carrier number fluctuations scheme. This model allows obtaining a consistent description of the noise characteristics of CMOS inverters issued from a 45nm bulk CMOS technology. It should constitute a reliable theoretical framework for further analysis of the impact of time fluctuations on the static and dynamic operation of CMOS inverter based circuits. [Copyright &y& Elsevier]

Low-frequency noise is for the first time investigated in 0.12 μm Partially Depleted (PD) Silicon-On-Insulator (SOI) N-MOSFETs in comparison with established results on the 0.25 μm SOI CMOS technology node. The transfer and output characteristics of the devices are first addressed as well as an evaluation of the static performances. Then, we present low-frequency noise measurements carried out in both linear and saturation regimes taking into consideration the usually admitted 1/f noise models in MOS devices and their applicability in our case. A comparison is achieved with previously published results on 0.25 μm PD SOI N-MOSFETs, showing the drain current noise spectral densities, as well as the Kink-related excess noise occurring in the saturation regime. [Copyright &y& Elsevier]

The impact of the front oxide quality on the performance of SOI devices is investigated. In this respect, a Fowler–Nordheim stress is performed for both partially (PD) and fully (FD) depleted N-MOSFETs. Various special SOI mechanisms are analyzed, as floating body effects for PD devices and coupling effects, between front and back interfaces, for FD ones. In the first part, the influence of the front oxide quality in PD transistors on transient effects and low-frequency noise (LFN), which both are influenced by the floating body, is analyzed. In the second part, the impact of the front oxide and coupling effects on the LFN in FD MOSFETs is investigated. [Copyright &y& Elsevier]

In this paper, the impact of silicon film thickness on the electrical properties of deep submicron SOI devices is thoroughly investigated down to ultra-thin Si layers. Particular attention is paid to the behavior of the low frequency noise and hot-carrier-induced degradation for Si films down to 10 nm. [Copyright &y& Elsevier]

In this paper, a parametric statistical analysis of the low-frequency noise (LFN) in very small area ( W · L ≈ 10 −3 μm 2 ) 14 nm fully depleted silicon-on-insulator (FD-SOI) n-MOS devices is presented. It has been demonstrated that the LFN origin is due to carrier trapping/detrapping into gate dielectric traps near the interface and the mean noise level in such small area MOSFETs is well approached by the carrier number fluctuations model in all measurement conditions. The impact of gate voltage bias and temperature on the LFN variability, as well as the standard deviation dependence on frequency have been studied for the first time, focusing on their relation to the Random Telegraph Noise (RTN) effect and its characteristics. [ABSTRACT FROM AUTHOR]

Abstract: Extensive investigation of the low-frequency noise in n-channel and p-channel MOSFETs, with high-k gate stack and channel length varying from 1.8μm down to 26.4nm, has been carried out. The results demonstrate that the carrier number fluctuation with correlated mobility fluctuations describes accurately and continuously the 1/f noise for all operation regions, i.e. from weak to strong inversion and from linear to saturation. It has been found that the product of the Coulomb scattering coefficient and the effective carrier mobility is constant over a wide range of the drain current due to the interplay of the Coulomb scattering coefficient αsc and the effective carrier mobility μeff variations. In addition, a non-linear increase in the square root of the input gate voltage noise with the gate voltage overdrive was observed explained by the surface roughness scattering. The overall results lead to an analytical expression for the 1/f noise model, enabling to predict the noise level of a transistor with any channel dimensions using its transfer characteristic. This finding makes the noise model suitable for circuit simulation tools. [Copyright &y& Elsevier]

In this work, we investigate the impact of the source - drain series resistance mismatch on the drain current variability in 28 nm bulk MOSFETs. For the first time, a mismatch model including the local fluctuations of the threshold voltage ( V t ), the drain current gain factor ( β ) and the source – drain series resistance ( R SD ) in both linear and saturation regions is presented. Furthermore, it is demonstrated that the influence of the source – drain series resistance mismatch is attenuated in the saturation region, due to the weaker sensitivity of the drain current variability on the series resistance variation. The experimental results were further verified by numerical simulations of the drain current characteristics with sensitivity analysis of the MOSFET parameters V t , β and R SD . [ABSTRACT FROM AUTHOR]

A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental I d – V g measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel lengths on nano-scale FDSOI devices, demonstrating its simplicity, accuracy and robustness. [ABSTRACT FROM AUTHOR]

This work presents an investigation of DC and Low Frequency Noise dispersion in 0.13 μm SiGe:C BiCMOS Heterojunction Bipolar Transistors (HBTs) used for mm-Wave to Terahertz applications. Therefore, DC and Low Frequency Noise measurements have been performed over a half wafer on a large number of transistors. A statistical 1/ f noise compact model is presented as well as a study of the repartition of generation-recombination components. The main Low Frequency Noise sources are found to be homogenously distributed in the intrinsic base-emitter junction. The mean 1/ f noise level, evaluated by the figure of merit K Bmean , is equal to 6 10 −10 μm 2 . [ABSTRACT FROM AUTHOR]

Highlights: [•] Impact of UTBOX with GP and local Vb on bitcells performance improvement. [•] The V T variation increases when opposite GP doping is used for NMOS and PMOS. [•] As the BOX thickness is reduced this V T variation versus Vb increases. [•] Back bias improve bitcells performance in FBB and RBB as in bulk. [•] For gated and STI diodes, hybrid technology improves TLP at the same level as bulk. [ABSTRACT FROM AUTHOR]

Highlights: [•] Some key information about device fabrication is given. [•] Information about Poisson-Schrödinger simulations is added. [•] Details on Maserjian function are added. [•] Figure captions are made more consistent. [•] A TEM figure is added to table 1 for device description. [ABSTRACT FROM AUTHOR]

Abstract: In this paper we explore for the first time the impact of an ultra-thin BOX (UTBOX) with and without ground plane (GP) on a 32nm fully-depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50mV DIBL reduction by using 10nm BOX thickness for NMOS and PMOS devices at 33nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299μm2 SRAM cell while maintaining an SNM of 296mV@Vdd 1.1V. [Copyright &y& Elsevier]