1. A dynamic power-efficient 4 GS/s CMOS comparator.
- Author
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Dehkordi, Mehrdad Amirkhan, Dousti, Massoud, Mirsanei, Seyed Mehdi, and Zohoori, Soorena
- Subjects
- *
COMPARATOR circuits , *SUCCESSIVE approximation analog-to-digital converters , *KICKBACKS , *BANDWIDTHS , *VOLTAGE , *NOISE - Abstract
This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator. The advantages of the proposed circuit are low kickback noise and offset. Moreover, low-power and high-speed characteristics are obtained by avoiding direct connection between the pre-amplifier and latch stages using another stage between them. The power-delay product (PDP) of the comparator is reduced due to the reduction in charging and discharging delays at the latching nodes. The proposed comparator consumes only 244.19 µW using a 1 V supply voltage. Furthermore, the bandwidth, delay, offset, and kickback noise of the proposed comparator are 4 GHz, 26.91 ps, 3 mV, and 38 mV, respectively. Results indicate the proper performance of the proposed comparator in low-power applications. [ABSTRACT FROM AUTHOR]
- Published
- 2023
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