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A fully-integrated 2.9 MHz RC relaxation oscillator is presented in this paper. In order to eliminate performance degradation caused by propagation delay at low power, the delay equivalent electric charges technique based on comparator offset cancellation structure is utilized. The oscillator is designed in 180 nm CMOS process and 1-point trimmed to operate within 0.2% precision by a specific mathematical model. With core area of 0. 115 mm 2 , the oscillator achieves a frequency stability of 45 ppm/°C in range from −40 ∼ +125 °C and demonstrates an energy efficiency of 2.49 μ W/MHz. [ABSTRACT FROM AUTHOR]

Nowadays, deep learning algorithm has been widely used for automatic electrocardiogram (ECG) classification. However, most algorithms can only classify single heartbeat, which requires complex heartbeat extraction preprocessing. In addition, the traditional software implementation on CPU or GPU platform faces the challenge of low computing efficiency and high resource consumption. In this work, a deep one-dimensional (1D) U-net is proposed, which can classify the original continuous ECG segment at the pixel level. And an efficient hardware architecture is presented to implement the 1D U-net. A two-stage pipeline Winograd structure is designed to increase computing efficiency. A 3D processing element (PE) array is developed to improve resource utilization and overall throughput. Implemented on Xilinx Zynq ZC706 board, experimental results show that the proposed 1D U-net achieves an average accuracy of 95.55% for the pixel-level classification of five heartbeats. In terms of hardware performance, resource efficiency and computing efficiency reach 8.27 GOPS/kLUT and 123% respectively at 200 MHz clock frequency. [ABSTRACT FROM AUTHOR]