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Generally the accelerators type identifies the edge computing performance hugely and it includes Integrated Circuit (IC), Graphical Processing Unit (GPU) and Field Programmable Gate Array (FPGA). Among these accelerator FPGAs are widely used in several edge computing areas since it has the ability to reconfigure and has high energy efficient. The consequence also comes out with the paradigm of scheduling efficiency on CPU’s (software tasks) and FPGA (hardware tasks). However the conventional schemes not entirely exploited the variations among hardware and software tasks which results in low scheduling efficiency. Therefore a task scheduling system is proposed on basis of fully active reconfigurable system. The scheduling efficiency for the proposed scheme can be increased by switching the task overheads and by predicting the execution time for hardware with minimum task switching times.

In the recent past, the FPGA mechanism is a leading achievement medium for electronic digital circuit design. The digital systems are operated with both asynchronous and synchronous mode with multiple clocks. This paper presents fault tolerance to a grid of asynchronous clocked run time reconfigurable modules with dynamic and partially reconfigurable on FPGA. The fault tolerance of dynamic partial reconfiguration (DPR) model based on fault tolerance system in asynchronous clock operation model is implemented for FPGA. The proposed algorithm for DPR in the presence of faults uses the equalizer technique to eliminate the faults during the processing. The DPR reduces the runtime and memory space is saved by the partial reconfiguration in parallel computing of FPGA. The overall throughput of the development system is high for multiple clock domains within the grid. The performance of the proposed system is compared with the synchronous clocked grid system to prove the efficiency of the DPR. Experimental results show that the high efficiency and accuracy of the DPR with fault tolerance of FPGAs.