1. Task mapping and mesh topology exploration for an FPGA-based network on chip
- Author
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Suying Yao, Ke Pang, Virginie Fresse, and Otavio Alcantara de Lima
- Subjects
Emulation ,Computer Networks and Communications ,Computer science ,business.industry ,Mesh networking ,Task mapping ,Energy consumption ,Network on a chip ,Artificial Intelligence ,Hardware and Architecture ,Embedded system ,business ,Field-programmable gate array ,Software - Abstract
Task mapping strategies on NoC (Network-on-Chip) have a huge impact on the timing performance and power consumption. So does the topology. In this paper, we describe the exploration flow of task mapping algorithms using different NoC mesh shapes. The flow is used to evaluate timing and energy consumption based on a NoC emulation platform. It is open to any task mapping algorithms and to any shapes of NoC mesh. A heterogeneous (PC and FPGA) platform is used to fully perform each step of the flow. The experiments demonstrate that the most appropriate task mapping strategy and the most suitable NoC shape strongly depend on the algorithm used. Depending on the timing latency results obtained and the FPGA resources used, the designer can select the appropriate task mapping strategy on the suitable shape in a short exploration time and with precise timing evaluation.
- Published
- 2015
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