Search

Your search keyword '"V. Mazzocchi"' showing total 3 results
Start Over Author "V. Mazzocchi" Publisher hal ccsd
3 results on '"V. Mazzocchi"'

1. Opportunities and challenges brought by 3D-sequential integration

Author

Benoit Sklenard, Bastien Giraud, Sebastien Thuries, Mikael Casse, Joris Lacord, Cm. Ribotta, V. Lapras, P. Acosta-Alba, O. Billoint, M. Mouhdach, N. Rambal, Pascal Besson, Francois Andrieu, Perrine Batude, Didier Lattard, Laurent Brunet, Gilles Sicard, Xavier Garros, Christoforos G. Theodorou, L. Brevard, Maud Vinet, V. Mazzocchi, P. Sideris, M. Ribotta, Claire Fenouillet-Beranger, F. Ponthenier, Pascal Vivet, Sebastien Kerdiles, G. Cibrario, J.M. Hartmann, Frank Fournel, Bernard Previtali, Frédéric Mazen, Claude Tabone, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
Presentation, Reliability (semiconductor), Materials science, CMOS, Process (engineering), media_common.quotation_subject, Key (cryptography), Systems engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Active devices, Sketch, ComputingMilieux_MISCELLANEOUS, media_common
Abstract

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

Published
2021

2. High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration

Author

J. Micout, M. Casse, J.-P. Colinge, L. Desvoivres, Vincent Delaye, C. Fenouillet-Beranger, S. Barraud, X. Garros, Perrine Batude, J.M. Hartmann, R. Bortolin, V. Mazzocchi, Frédéric Mazen, G. Romano, B. Mathieu, N. Rambal, V. Balan, Zineb Saghi, F. Allain, M.-P. Samson, P. Besombes, C. Comboroure, M. Vinet, Quentin Rafhay, Joris Lacord, Claude Tabone, Alain Toffoli, Gerard Ghibaudo, C. Vizioz, Benoit Sklenard, V. Lapras, L. Lachal, Laurent Brunet, Virginie Loup, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire des technologies de la microélectronique (LTM ), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
Materials science, Fabrication, business.industry, 020208 electrical & electronic engineering, Doping, Recrystallization (metallurgy), 02 engineering and technology, Epitaxy, Logic gate, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, 020201 artificial intelligence & image processing, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.

Published
2017

3. High performance CMOS FDSOI devices activated at low temperature

Author

Louis Hutin, J. Mazurier, D. Barge, L. Pasini, Olivier Weber, Frédéric Mazen, F. Piegas Luce, Claire Fenouillet-Beranger, M. Vinet, Antoine Cros, E. Ghegin, B. Mathieu, S. Chhun, J. Borrel, Frederic Boeuf, Quentin Rafhay, Anthony Payet, Michel Haond, Perrine Batude, M. Casse, Fuccio Cristiano, Benoit Sklenard, Zineb Saghi, Joris Lacord, D. Blachier, J.P. Barnes, Gerard Ghibaudo, Francois Andrieu, V. Mazzocchi, N. Rambal, J. Micout, Vincent Delaye, V. Lapras, Laurent Brunet, R. Daubriac, Pascal Besson, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Équipe Matériaux et Procédés pour la Nanoélectronique (LAAS-MPN), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Nano 2017, ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées

Subjects
010302 applied physics, Materials science, business.industry, 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, PMOS logic, CMOS, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [PHYS.COND.CM-MS]Physics [physics]/Condensed Matter [cond-mat]/Materials Science [cond-mat.mtrl-sci], Optoelectronics, business, NMOS logic
Abstract

International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).

Published
2016

Catalog

Books, media, physical & digital resources
See catalog results