Search

Five years ago, few would have predicted that a software company like Google would build its own computers. Nevertheless, Google has been deploying computers for machine learning (ML) training since 2017, powering key Google services. These Tensor Processing Units (TPUs) are composed of chips, systems, and software, all co-designed in-house. In this paper, we detail the circumstances that led to this outcome, the challenges and opportunities observed, the approach taken for the chips, a quick review of performance, and finally a retrospective on the results. A companion paper describes the supercomputers built from these chips, the compiler, and a detailed performance analysis [Jou20]. [ABSTRACT FROM AUTHOR]

Ising machines are expected to solve combinatorial optimization problems efficiently by representing them as Ising models or equivalent quadratic unconstrained binary optimization (QUBO) models. However, upper bound exists on the computable problem size due to the hardware limitations of Ising machines. This paper propose a new hybrid annealing method based on partial QUBO extraction, called subQUBO model extraction, with multiple solution instances. For a given QUBO model, the proposed method obtains $N_I$ N I quasi-optimal solutions (quasi-ground-state solutions) in some way using a classical computer. The solutions giving these quasi-optimal solutions are called solution instances. We extract a size-limited subQUBO model as follows based on a strong theoretical background: we randomly select $N_S$ N S $(N_S

Lattice-based cryptography, as an active branch of post-quantum cryptography (PQC), has drawn great attention from side-channel analysis researchers in recent years. Despite the various side-channel targets examined in previous studies, detail on revealing the secret-dependent information efficiently is less studied. In this paper, we propose adaptive EM side-channel attacks with carefully constructed ciphertexts on Kyber, which is a finalist of NIST PQC standardization project. We demonstrate that specially chosen ciphertexts allow an adversary to modulate the leakage of a target device and enable full key extraction with a small number of traces through simple power analysis. Compared to prior research, our techniques require fewer traces and avoid building complex templates. We practically evaluate our methods using both a reference implementation and the ARM-specific implementation in pqm4 library. For the reference implementation, we target the leakage of the output of the inverse NTT computation and recover the full key with only four traces. For the pqm4 implementation, we develop a message-recovery attack that leads to extraction of the full secret key with between eight and 960 traces, depending on the compiler optimization level. We discuss the relevance of our findings to other lattice-based schemes and explore potential countermeasures. [ABSTRACT FROM AUTHOR]

Recent advances in quantum technologies pave the way for noisy intermediate-scale quantum (NISQ) devices, where the quantum approximation optimization algorithm (QAOA) constitutes a promising candidate for demonstrating tangible quantum advantages based on NISQ devices. In this paper, we consider the maximum likelihood (ML) detection problem of binary symbols transmitted over a multiple-input and multiple-output (MIMO) channel, where finding the optimal solution is exponentially hard using classical computers. Here, we apply the QAOA for the ML detection by encoding the problem of interest into a level- $p$ QAOA circuit having $2p$ variational parameters, which can be optimized by classical optimizers. This level- $p$ QAOA circuit is constructed by applying the prepared Hamiltonian to our problem and the initial Hamiltonian alternately in $p$ consecutive rounds. More explicitly, we first encode the optimal solution of the ML detection problem into the ground state of a problem Hamiltonian. Using the quantum adiabatic evolution technique, we provide both analytical and numerical results for characterizing the evolution of the eigenvalues of the quantum system used for ML detection. Then, for level-1 QAOA circuits, we derive the analytical expressions of the expectation values of the QAOA and discuss the complexity of the QAOA based ML detector. Explicitly, we evaluate the computational complexity of the classical optimizer used and the storage requirement of simulating the QAOA. Finally, we evaluate the bit error rate (BER) of the QAOA based ML detector and compare it both to the classical ML detector and to the classical minimum mean squared error (MMSE) detector, demonstrating that the QAOA based ML detector is capable of approaching the performance of the classical ML detector. [ABSTRACT FROM AUTHOR]

Distributed storage systems (DSSs) in the presence of an external wiretapper are considered. A DSS is parameterized by $(n, k, d)$ , in which the data are stored across $n$ nodes (each with storage capacity $\alpha $ ), and must be recoverable by accessing the contents stored on any $k$ out of $n$ nodes. If a node fails, any $d \geq k$ out of $(n-1)$ nodes help in the repair (regeneration) of the failed node (by sending $d\beta $ units of repair data, where $\beta \leq \alpha $ ), so that the data can still be recovered from the DSS. For such a $(n, k, d)$ -DSS, security from the two types of wiretappers is investigated: 1) Type-I (node data) wiretapper, which can read the data stored on any $\ell

Events and information of interest to Computer Society members. [ABSTRACT FROM AUTHOR]

Events and information of interest to Computer Society members. [ABSTRACT FROM PUBLISHER]

The aim of this paper is to propose a numerical controller design methodology. This methodology is based on two steps. In the first step, the tensor product (TP) model transformation is applied, which is capable of transforming a given nonlinear state-space dynamic model into TP model form. Then, in the second step, the linear matrix inequality (LMI) theorems are used within the parallel distributed compensation (PDC) controller design frameworks. The main novelty of this paper is the TP model transformation of the first step. It is also capable of dealing with the tradeoff between complexity and accuracy of the resulting TP model. The TP model transformation is a numerical method that leads to the following advantages: it is capable of functioning with models given either by analytic explicit forms or by various soft-computing based identification techniques; it does not need problem dependent analytic derivations, but can be executed "automatically" by computers. Numerical simulations are used to provide empirical validation of the proposed control design methodology. In order to demonstrate the effectiveness of the TP model transformation a controller is derived for the prototypical aeroelastic wing section that exhibits limit cycle oscillation and chaotic behavior. [ABSTRACT FROM AUTHOR]

Computer communication systems are complex systems in which both computing power and communications capabilities play a key role. Examples of such systems range from worldwide data and voice communications networks to local area networks, and even encompass the more recent multiprocessor computer systems. In the past, the design and development of such systems has been done in a fairly ad hoc manner. However, it is increasingly apparent that in order to understand and develop sucy systems, it is necessary to have a more systematic approach to designing and studying such systems.

Ultrahigh definition (UHD), such as 4K/8K, is becoming the mainstream of video resolution nowadays. High Efficiency Video Coding (HEVC) is the emerging video coding standard to process the encoding and decoding of UHD video. This paper first develops multiple techniques that allow the proposed hardware architecture for intra prediction of HEVC working in full pipeline. The proposed techniques include: 1) a novel buffer structure for reference samples; 2) a mode-dependent scanning order; and 3) an inverse method for reference sample extension. The size of the buffer is 3K b for luma component and 3K b for chroma components, providing sufficient accessing to the reference samples. Since the data dependency between two neighboring blocks is addressed by the mode-dependent scanning order, the proposed fully pipelined design can produce 4 pixels/clock cycle. As a result, the throughput of the proposed architecture is capable to support $3840 \times 2160$ videos at 30 frames/s. [ABSTRACT FROM PUBLISHER]

A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and the BCD-4221/5211 code. The signed-digit radix-10 recoding is used to recode the BCD multiplier to the digit set [-5, 5] from [0, 9]. The redundant BCD XS-3 code is adopted to generate the multiplicand multiples in a carry-free manner. The XS-3 coded partial products (PPs) are converted to ODDS PPs to fit binary partial product reduction (PPR). In this paper, a regular decimal PPR tree using ODDS and BCD-4221/5211 codes is proposed; it consists of a binary PPR tree block, a non-fixed size BCD-4221 counter block and a BCD-4221/5211 PPR tree block. The decimal carry-save algorithm based on BCD-4221/5211 is used in the PPR tree to obtain high performance multipliers. Moreover, an improved PPG circuit and an improved parallel prefix/carry-select decimal adder are proposed to further improve the performance of the proposed multipliers. Analysis and comparison using the 45 nm technology show that the proposed decimal multipliers are faster and require less hardware area than previous designs found in the technical literature. [ABSTRACT FROM PUBLISHER]

This paper models a real-time warm standby system that has to accomplish a specified amount of task by a hard deadline. The system is subject to corrective replacements (CRs) upon failure of its operating element. It can also be renewed according to a predetermined schedule through preventive replacements (PRs). To facilitate an effective recovery of system operation after replacements, periodic backups are performed so that warm standby elements, upon being activated, can take over the mission task from the last backup point instead of from scratch. This paper presents a novel integrated model that considers effects of periodic backups, CRs and PRs in analyzing and optimizing real-time warm standby systems. Mission success probability and expected mission completion time are evaluated. Impacts of different mission and element parameters on mission success probability, optimal backup and PR policies, and optimal element activation sequence are investigated. It is shown that in warm standby systems with periodic backups and tight deadlines, PRs can improve the mission success probability even when they take the same time as CRs. When the maximum allowed mission time exceeds a certain level, PRs become ineffective and the optimal policy can involve only periodic backups. [ABSTRACT FROM PUBLISHER]

Nowadays, data reduction is becoming increasingly important in dealing with the large amounts of scientific data. Existing multilevel compression algorithms offer a promising way to manage scientific data at scale, but may suffer from relatively low performance and reduction quality. In this paper, we propose MGARD+, a multilevel data reduction and refactoring framework drawing on previous multilevel methods, to achieve high-performance data decomposition and high-quality error-bounded lossy compression. Our contributions are four-fold: 1) We propose to leverage a level-wise coefficient quantization method, which uses different error tolerances to quantize the multilevel coefficients. 2) We propose an adaptive decomposition method which treats the multilevel decomposition as a preconditioner and terminates the decomposition process at an appropriate level. 3) We leverage a set of algorithmic optimization strategies to significantly improve the performance of multilevel decomposition/recomposition. 4) We evaluate our proposed method using four real-world scientific datasets and compare with several state-of-the-art lossy compressors. Experiments demonstrate that our optimizations improve the decomposition/recomposition performance of the existing multilevel method by up to $70 \times$ 70 × , and the proposed compression method can improve compression ratio by up to $2 \times$ 2 × compared with other state-of-the-art error-bounded lossy compressors under the same level of data distortion. [ABSTRACT FROM AUTHOR]

Heterogeneous systems on a single chip composed of a central processing unit, graphics processing unit (GPU), and field-programmable gate array (FPGA) are expected to emerge in the near future. In this context, the system on chip can be dynamically adapted to employ different architectures for execution of data-intensive applications. Motion estimation (ME) is one such task that can be accelerated using FPGA and GPU for high-performance H.264/Advanced Video Coding encoder implementation. This paper presents an inherent parallel low-complexity rate-distortion (RD) optimized fast ME algorithm well suited for parallel implementations, eliminating various data dependencies caused by a reliance on spatial predictions. In addition, this paper provides details of the GPU and FPGA implementations of the parallel algorithm by using OpenCL and Very High Speed Integrated Circuits (VHSIC) Hardware Descriptive Language (VHDL), respectively, and presents a practical performance comparison between the two implementations. The experimental results show that the proposed scheme achieves significant speedup on GPU and FPGA, and has comparable RD performance with respect to sequential fast ME algorithm. [ABSTRACT FROM AUTHOR]

For practical use of microwave simulations in industry applications such as high frequency product design, this paper presents a conceptual design of 3-D finite difference time domain (FDTD) dedicated computer with dataflow architecture as one of the portable high performance computing technologies. A basic concept of the dataflow architecture for the FDTD dedicated computer itself was presented already in 2003 for 2-D microwave simulations. Detail design of 3-D FDTD dataflow machine is considered in this paper. [ABSTRACT FROM PUBLISHER]

Huang and Wu in [IEEE Transactions on Computers 46 (1997) 484-490] introduced the balanced hypercube BH_n as an interconnection network topology for computing systems, and they proved that BH_n is vertex-transitive. However, some other symmetric properties, say edge-transitivity and arc-transitivity, of BH_n remained unknown. In this paper, we solve this problem and prove that BH_n is an arc-transitive Cayley graph. Using this, we also investigate some reliability measures, including super-connectivity, cyclic connectivity, etc., in BH_n. First, we prove that every minimum edge-cut of BH_n (n\ge 2) isolates a vertex, and every minimum vertex-cut of BH_n (n\ge 3) isolates a vertex. This is stronger than that obtained by Wu and Huang which shows the connectivity and edge-connectivity of BH_n are 2n. Second, Yang [Applied Mathematics and Computation 219 (2012) 970-975.] proved that for n\ge 2, the super-connectivity of BH_n is 4n-4 and the super edge-connectivity of BH_n is 4n-2. In this paper, we proved that BH_n (n\ge 2) is super-\lambda^\prime but not super-\kappa^\prime . That is, every minimum super edge-cut of BH_n (n\ge 2) isolates an edge, but the minimum super vertex-cut of BH_n (n\ge 2) does not isolate an edge. Third, we also obtain that for n\ge 2, the cyclic connectivity of BH_n is 4n-4 and the cyclic edge-connectivity of BH_n is 4(2n-2). That is, to become a disconnected graph which has at least two components containing cycles, we need to remove at least 4n-4 vertices (resp. 4(4n-2) edges) from BH_n (n\ge 2). [ABSTRACT FROM AUTHOR]

With the increasing call for green cloud, reducing energy consumption has been an important requirement for cloud resource providers not only to reduce operating costs, but also to improve system reliability. Dynamic voltage scaling (DVS) has been a key technique in exploiting the hardware characteristics of cloud datacenters to save energy by lowering the supply voltage and operating frequency. This paper presents a novel stochastic framework for energy efficiency and performance analysis of DVS-enabled cloud. This framework uses virtual machine request arrival rate, failure rate, repair rate, and service rate of datacenter servers as model inputs. Based on a queuing-network-based analysis, this paper gives analytic solutions of three metrics. The proposed framework can be used to help the design and optimization of energy-aware high performance cloud systems. [ABSTRACT FROM AUTHOR]

In this paper, we study the graphical structure of elementary trapping sets (ETSs) of variable-regular low-density parity-check (LDPC) codes. ETSs are known to be the main cause of error floor in LDPC coding schemes. For the set of LDPC codes with a given variable node degree \(d_{l}\) and girth \(g\) , we identify all the nonisomorphic structures of an arbitrary class of \((a,b)\) ETSs, where \(a\) is the number of variable nodes and \(b\) is the number of odd-degree check nodes in the induced subgraph of the ETS. This paper leads to a simple characterization of dominant classes of ETSs (those with relatively small values of \(a\) and \(b\) ) based on short cycles in the Tanner graph of the code. For such classes of ETSs, we prove that any set \({\cal S}\) in the class is a layered superset (LSS) of a short cycle, where the term layered is used to indicate that there is a nested sequence of ETSs that starts from the cycle and grows, one variable node at a time, to generate \({\cal S}\) . This characterization corresponds to a simple search algorithm that starts from the short cycles of the graph and finds all the ETSs with LSS property in a guaranteed fashion. Specific results on the structure of ETSs are presented for \(d_{l} = 3, 4, 5, 6\) , \(g = 6, 8\) , and \(a, b \leq 10\) in this paper. The results of this paper can be used for the error floor analysis and for the design of LDPC codes with low error floors. [ABSTRACT FROM AUTHOR]

This paper studies information sharing in a supply chain where a contract manufacturer (CM) acts as both an upstream partner and a downstream competitor to an original equipment manufacturer (OEM). To better explore the effect of information sharing on a coopetitive supply chain, we consider a sequential game with the OEM as the Stackelberg leader under two different wholesale pricing methods, which is close to the practical situation. Our analysis shows that when the wholesale price is exogenously given, information sharing is beneficial for the OEM but hurts the CM, and a side-payment contract is designed to induce Pareto-optimal information sharing. When the wholesale price is a decision variable, the CM benefits from information sharing while the OEM does not and a discount-based wholesale price contract is designed to induce truthful information sharing. The numerical examples analysis further finds that the OEM benefits from the exogenous wholesale price scenario while the CM benefits from the endogenous wholesale price scenario. The study sheds lights on the decision-making processes for operating and managing the coopetitive supply chain and extends the research scope of information sharing. Our findings also provide some scientific references about information sharing in daily production. [ABSTRACT FROM AUTHOR]

Retweeting is a powerful driving force in information propagation on microblogging sites. However, identifying the most effective retweeters of a message (called the ”key retweeter prediction” problem) has become a significant research topic. Conventional approaches have addressed this topic from two main aspects: by analyzing either the personal attributes of microblogging users or the structures of user graph networks. However, according to sociological findings, author-retweeter dependencies also play a crucial role in influencing message propagation. In this paper, we propose a novel model to solve the key retweeter prediction problem by incorporating the auxiliary relations between a tweet author and potential retweeters. Without loss of generality, we formulate the relations from four relational factors: status relation, temporal relation, locational relation, and interactive relation. In addition, we propose a novel method, called “Relation-based Learning to Rank (RL2R),” to determine the key retweeters for a given tweet by ranking the potential retweeters in terms of their spreadability. The experimental results show that our method outperforms the state-of-the-art algorithms at top-k retweeter prediction, achieving a significant relative average improvement of 19.7–29.4 percent. These findings provide new insights for understanding user behaviors on social media for key retweeter prediction purposes. [ABSTRACT FROM AUTHOR]

Recent progress in quantum physics shows that quantum computers may be a reality in the not too distant future. Post-quantum cryptography (PQC) refers to cryptographic schemes that are based on hard problems which are believed to be resistant to attacks from quantum computers. The supersingular isogeny Diffie-Hellman (SIDH) key exchange protocol shows promising security properties among various post-quantum cryptosystems that have been proposed. In this paper, we propose two efficient modular multiplication algorithms with special primes that can be used in SIDH key exchange protocol. Hardware architectures for the two proposed algorithms are also proposed. The hardware implementations are provided and compared with the original modular multiplication algorithm. The results show that the proposed finite field multiplier is over 6.79 times faster than the original multiplier in hardware. Moreover, the SIDH hardware/software codesign implementation using the proposed FFM2 hardware is over 31 percent faster than the best SIDH software implementation. [ABSTRACT FROM AUTHOR]

Computer programming has for decades posed several difficulties for students of all educational levels. A number of teaching approaches have been proposed over the years but none seems to fulfil the needs of students nowadays. Students use computers mainly for playing games and the Internet and as quite a few researchers state this aspect of computers should be taken into account in the way we educate them. Towards this direction, this paper aims to examine the effects of using an educational Massive Multiplayer Online Role Playing Game (MMORPG) on teaching and learning computer programming. The educational features of an MMORPG called CMX are presented along with a design framework that was devised taking into account previous work in designing educational games. The effects of CMX on teaching and learning computer programming are assessed through a study with first-year undergraduate students. Seventy six students used CMX over a period of five weeks for learning various procedural programming concepts. Students evaluated various aspects of CMX by filling in a questionnaire that was based on an evaluation framework, which was devised in accordance with the design framework of CMX. Moreover, the results of a midterm exam that took place prior to using CMX and students’ accomplishments in the context of CMX were recorded and analyzed. The results show that the majority of the students was entertained by playing the game while learning, and felt motivated to continue based on the game's scenario due to the variety of activities included. In regards to the students’ performance, a pre-test and a post-test were carried out in the experimental group, i.e., the participants of this study, and the control group, i.e., students of the course that continued to get taught the same concepts and performed the same assignments as the experimental group, but traditionally. The pre-test and post-test analysis of the performance results for both groups showed that the majority of the students in the experimental group increased their performance in computer programming. Furthermore, students stated they had a positive attitude in regards to re-using CMX in the future in order to learn additional programming concepts. The positive results of this study pave the way for CMX being used in the classroom and expanding the game's functionalities that will further increase students’ performance and support teachers in delivering the required knowledge. Moreover, the work reported in this paper offers game designers and teachers methodological and empirical results for game-based learning in such a difficult domain as is computer programming. What is more, the design and evaluation frameworks presented are general enough that they can be easily adjusted and/or extended for designing and assessing educational games in other domains as well. [ABSTRACT FROM PUBLISHER]

In this paper, we address the problems of enumerating siphons and minimal siphons in ordinary Petri nets (PNs) by resorting to the semi-tensor product (STP) of matrices. First, a matrix equation, called the siphon equation (SE), is established by using STP. Second, an algorithm is proposed to calculate all siphons in ordinary PNs. An example is presented to illustrate the theoretical results and show that the proposed method is more effective than other existing methods in calculating all siphons of PNs. Third, an efficient recursion algorithm is also proposed, which can be applied to computing all minimal siphons for any ordinary PNs. Last, some results on the computational complexity of the proposed algorithms, in this paper, are provided, as well as experimental results. [ABSTRACT FROM PUBLISHER]

The increasing complexity of the new breed of distributed intelligent systems, such as the Internet of Things, which require a diversity of languages and protocols, can only be tamed with design and programming best practices. Interest is also growing for including the human factor, as advocated by the ambient intelligence (AmI) research field, whose focus is on transparently and intelligently supporting people. These new design methodologies are increasingly needed in the toolbox of new electronic and computer engineers, and teaching strategies should be devised that allow students to acquire a systems-level view instead of getting lost in technology-oriented approaches. This paper describes a study carried out over two academic years, in a course in AmI at Politecnico di Torino, Italy. In the course, a project-based learning approach was adopted, in which students design and prototype an AmI system, and their progress is closely monitored throughout the semester. This paper presents the learning goals and teaching strategies, analyzes the learning outcomes from the qualitative and quantitative points of view, and highlights the lessons learned in the process. [ABSTRACT FROM PUBLISHER]

The interpretations of logical expressions found in most introductory textbooks are not suitable for use in software engineering applications because they do not deal with partial functions. More advanced papers and texts deal with partial functions in a variety of complex ways. This paper proposes a very simple change to the classic interpretation of predicate expressions, one that defines their value for all values of all variables, yet is almost identical to the standard definitions. It then illustrates the application of this interpretation in software documentation. [ABSTRACT FROM AUTHOR]

This paper presents characterization of 300-GHz wireless channel on a computer motherboard, where several different measurement scenarios have been considered. Results indicate that the presence of the ground plane and/or vertical parallel-plate structures in the channel introduces multipath that, if constructively superimposed, may create a path loss lower than free-space propagation path loss. In addition, it has been found that a few centimeters of vertical misalignment between the transmitter and the receiver result in a path loss greater than 5 dB. Furthermore, the results indicate that vertical components such as dual in-line memory modules with reflection coefficient close to one for all incident angles can be used to create directed non-line-of-sight (LoS) links with wide coherence bandwidth. Finally, for LoS propagation obstructed by large objects, such as a heatsink, the path-loss exponent of 1.77 is found, while the rotating fan causes periodic fading in the received power, indicating that channel equalization techniques will be needed to overcome deep fades. All these results indicate that optimal communications can be achieved by carefully positioning the antennas with respect to the motherboard layout. [ABSTRACT FROM PUBLISHER]

This paper deals with accelerating typical optimization scenarios for electrical machine designs. Besides the advantage of a reduced computation time, this leads to a reduction in computational power and thus to a lower power consumption when running the optimization. If machines of high power density are required, usually highly utilized assemblies that feature nonlinear characteristics are obtained. Optimization scenarios are considered where the evaluation of a potential design requires computationally expensive nonlinear finite element (FE) simulations. Improving the speed of optimization runs takes top priority and various measures can be considered. This paper is about basic and easily achievable measures, and techniques for a time-wise and computationally efficient exploration of the design space. Suggested improvements comprise sophisticated emerging techniques for modeling machine characteristics by paring the number of required FE simulations down to the minimum and nonlinear modeling of the targets of the optimization scenario as functions of the design parameters to further reduce the number of FE evaluations. In the case study, the analysis of a typical optimization task is given, and achievable speed improvements as well as still present issues are discussed. [ABSTRACT FROM AUTHOR]

The finite-difference time-domain (FDTD) method is an effective and widely used time-domain method for solving electromagnetic problems. Conventionally, its solutions are obtained numerically in a march-on-in-time manner. In this paper, based on the eigenmatrix theory, we derive the analytical expression for the FDTD solution. The FDTD solution is analytically expressed in terms of spatial modes modulated by discrete time sequences related to the eigenvalues of the FDTD system equation. Based on our results, we propose an alternative approach to the FDTD solutions and it could open a new horizon for applying advanced signal processing techniques as well as offering the possibility of storing the FDTD results in an analytical form for a structure after computation. [ABSTRACT FROM PUBLISHER]

Keeping up with novel methods and keeping abreast of new applications are crucial issues in engineering education. In brain research, one of the most significant research areas in recent decades, many developments have application in both modern engineering technology and education. New measurement methods in the observation of brain activity open a new frontier in engineering applications. Electroencephalogram (EEG)-based brain activity observation processes are very promising and have been used in several engineering studies, primarily for the implementation of control tasks. This paper presents the development, implementation, and assessment of an EEG-based engineering education project, in which engineering students applied the theory they had learned and improved their knowledge and skills in the area of observation and evaluation of electrical signals generated by brain activity and measured by biosensors. The main project goal was to develop and test a brain–computer interface that is able to measure the average attention level. The effectiveness of this project-based learning was evaluated by student questionnaire responses and analysis of students' exam results; students who had participated in the project were shown to have higher levels of acquired knowledge. [ABSTRACT FROM AUTHOR]

Standby power refers to the electric power consumed by electronic appliances while they are in a standby mode. As the electronic appliance have become smarter, they consume more standby power. To reduce wasted electricity, techniques to save standby power have been developed in conjunction with network and communication technologies. Automatic standby power saving systems have been developed, but the proposed systems do not consider the cost reduction, user satisfaction, and personalized environment. Furthermore, to provide automation, an intelligent system for collected information is required, which increases the cost of system integration. Therefore, this paper proposes cloud based ondemand standby power management using consumer pattern racking to address these problems to deal with these issues. The proposed system offers rule based management services with three usage types determined by user preferences and living patterns. The total power consumption is measured to verify the performance of the system. The proposed system reduces the power consumption up to 9.3%1. [ABSTRACT FROM PUBLISHER]

Teaching in university engineering departments is currently facing a number of challenges, especially for those involved in the most innovative and dynamic areas of information and communication technology. Learning model developments that place greater weight on laboratory activities require investment in specific equipment that is often very expensive, difficult to manage, and soon obsolete. This paper describes a virtual laboratory education platform, QoSLab, for training in and research into quality-of-service (QoS) mechanisms used for Metro Ethernet access in next-generation networks (NGNs). QoSLab integrates three experiments and 21 tasks with a pedagogical model to help students achieve learning goals; it also promoting student teamwork, iteration with lecturers, and autonomy. QoSLab was developed using OMNeT++, an open-source framework environment that allows students to run the code on their personal computers. Evaluations have shown that since 2013, QoSLab has produced a significant increase in student grades on NGN-related topics, as well as good results in student satisfaction surveys. [ABSTRACT FROM PUBLISHER]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Recovering a sparse signal from an undersampled set of random linear measurements is the main problem of interest in compressed sensing. In this paper, we consider the case where both the signal and the measurements are complex-valued. We study the popular recovery method of \ell 1-regularized least squares or LASSO. While several studies have shown that LASSO provides desirable solutions under certain conditions, the precise asymptotic performance of this algorithm in the complex setting is not yet known. In this paper, we extend the approximate message passing (AMP) algorithm to solve the complex-valued LASSO problem and obtain the complex approximate message passing algorithm (CAMP). We then generalize the state evolution framework recently introduced for the analysis of AMP to the complex setting. Using the state evolution, we derive accurate formulas for the phase transition and noise sensitivity of both LASSO and CAMP. Our theoretical results are concerned with the case of i.i.d. Gaussian sensing matrices. Simulations confirm that our results hold for a larger class of random matrices. [ABSTRACT FROM AUTHOR]

High-performance heterogeneous computers that employ field programmable gate arrays (FPGAs) as computational elements are known as high-performance reconfigurable computers (HPRCs). For floating-point applications, these FPGA-based processors must satisfy a variety of heuristics and rules of thumb to achieve a speedup compared with their software counterparts. By way of a simple sparse matrix Jacobi iterative solver, this paper illustrates some of the issues associated with mapping floating-point kernels onto HPRCs. The Jacobi method was chosen based on heuristics developed from earlier research. Furthermore, Jacobi is relatively easy to understand, yet is complex enough to illustrate the mapping issues. This paper is not trying to demonstrate the speedup of a particular application nor is it suggesting that Jacobi is the best way to solve equations. The results demonstrate a nearly threefold wall clock runtime speedup when compared with a software implementation. A formal analysis shows that these results are reasonable. The purpose of this paper is to illuminate the challenging floating-point mapping process while simultaneously showing that such mappings can result in significant speedups. The ideas revealed by research such as this have already been and should continue to be used to facilitate a more automated mapping process. [ABSTRACT FROM AUTHOR]

The issue of plagiarism is discussed in the context of university education in disciplines related to computing. The focus is therefore mainly on software plagiarism. First, however, a case is made for the claim that the most important reason that plagiarism cannot be tolerated lies in the essence of the concept of a university as it is rooted in the Western cultural tradition. The main contribution of this paper is in providing firsthand insight into students' views on some of the delicate questions related to student plagiarism. However, this paper presents views from both sides of the question, including the views of staff members. This paper is quite unique in that it is coauthored by students who provide independent comments and recommendations. [ABSTRACT FROM PUBLISHER]

In the past years, quantum computers more and more have evolved from an academic idea to an upcoming reality. IBM’s project IBM ${Q}$ can be seen as evidence of this progress. Launched in March 2017 with the goal to provide access to quantum computers for a broad audience, this allowed users to conduct quantum experiments on a 5-qubit and, since June 2017, also on a 16-qubit quantum computer (called IBM QX2 and IBM QX3, respectively). Revised versions of these 5- and 16-qubit quantum computers (named IBM QX4 and IBM QX5, respectively) are available since September 2017. In order to use these, the desired quantum functionality (e.g., provided in terms of a quantum circuit) has to be properly mapped so that the underlying physical constraints are satisfied—a complex task. This demands solutions to automatically and efficiently conduct this mapping process. In this paper, we propose a methodology which addresses this problem, i.e., maps the given quantum functionality to a realization which satisfies all constraints given by the architecture and, at the same time, keeps the overhead in terms of additionally required quantum gates minimal. The proposed methodology is generic, can easily be configured for similar future architectures, and is fully integrated into IBM’s SDK. Experimental evaluations show that the proposed approach clearly outperforms IBM’s own mapping solution. In fact, for many quantum circuits, the proposed approach determines a mapping to the IBM architecture within minutes, while IBM’s solution suffers from long runtimes and runs into a timeout of 1 h in several cases. As an additional benefit, the proposed approach yields mapped circuits with smaller costs (i.e., fewer additional gates are required). All implementations of the proposed methodology are publicly available at http://iic.jku.at/eda/research/ibm_qx_mapping. [ABSTRACT FROM AUTHOR]

Computer vision systems have attracted much attention in recent years for use in detecting surface defects on rails; however, accurate and efficient recognition of possible defects remains challenging due to the variations shown by defects and also noise. This paper proposes a coarse-to-fine model (CTFM) to identify defects at different scales. The model works on three scales from coarse to fine: subimage level, region level, and pixel level. At the subimage level, the background subtraction model exploits row consistency in the longitudinal direction, and strongly filters the defect-free range, leaving roughly identified subimages within which defects may exist. At the next level, the region extraction model, inspired by visual saliency models, locates definite defect regions using phase-only Fourier transforms. At the finest level, the pixel subtraction model uses pixel consistency to refine the shape of each defect. The proposed method is evaluated using Type-I and Type-II rail surface defect detection data sets and an actual rail line. The experimental results show that CTFM outperforms state-of-the-art methods according to both the pixel-level index and the defect-level index. [ABSTRACT FROM AUTHOR]

$\sf{ NTRUEncrypt}$  is one of the most promising candidates for quantum-safe cryptography. In this paper, we focus on the $\sf{ NTRU743}$  parameter set. We give a report on all known attacks against this parameter set and show that it delivers 256 bits of security against classical attackers and 128 bits of security against quantum attackers. We then present a parameter-dependent optimization using a tailored hierarchy of multiplication algorithms as well as the Intel AVX2 instructions, and show that this optimization is constant-time. Our implementation is two to three times faster than the reference implementation of $\sf{ NTRUEncrypt}$ . [ABSTRACT FROM AUTHOR]

In this article, author discusses about how to submit a paper to the premier new open access journal in computing and information technology.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Multithreading and multicore processing are powerful ways to take advantage of parallelism in applications in order to boost a system's performance. However, exploring sufficient parallelism and achieving data locality with low communication overhead are still important research issues in embedded multithreading/multicore design. This paper introduces the design of a fast data switching mechanism between multilevel storage structures in a new multicore architecture. This paper makes several contributions to the development of contemporary sophisticated multimedia applications with advanced standards such as H.264. The first contribution, collaborative-multithreading, tightly unifies reduced instruction set computer and collaborative multithreading digital signal processing (DSP) in order to exploit high parallelism to provide sufficient computing power to applications. Each collaborative thread of our DSP is constructed by a heterogeneous-simultaneously multithreading single instruction, multiple data structure, and four media processing cores, which is connected by a fast switch for providing a fast data exchange mechanism among correlative streams on a thread-level basis. Our second contribution is one-stop streaming processing, which aims to keep data in the system for as long as possible until it is no longer needed, thus making data more efficient to access. Our third contribution is a chunk threading programming model, including a thread management library and threading communication directives for reducing data communication and synchronization overhead. By a combination of coarse-grained and fine-grained threading, programmers can choose various threading levels based on the amount of data exchange in a program. With our proposed techniques and an appropriate programming model, we can reduce processing time by 54.9% in H.264 video encoding (common intermediate format video at 16.574 f/s) with the 1-virtual independent and streaming processing by open collaborative multithreading configuration, compared to the Texas Instruments C62 core that owns 8 function units. We realize our design as a prototype by chip implementation, and fabricate it as a chip based on the Taiwan Semiconductor Manufacturing Company Ltd. 0.13 μm process. The die size of the processor core is 16.12 mm2, including 414k logic transistors and 34.4 kB of on-chip static random access memory. The processor runs at 180 MHOz/1.2-V and consumes 245mW by postsimulation results. [ABSTRACT FROM AUTHOR]

This article focuses on the quality of articles published in the periodical "IEEE Transactions on Parallel and Distributed Systems." (TDPS)Through a tremendous effort by editorial board, staff, and reviewers, the periodical is in its best state in recent years. Editor has observed a dramatic reduction in the average review time for papers, a very healthy increase in the number of paper submissions, an extremely high level of satisfaction among authors in surveys conducted. TPDS is also among the five titles in the Computer Society that have held or improved the subscriber retention rate past year. Editor has improved peer review process over the last few years and has cleared all of the backlog from before 2001. He is in the process of completing a small number of remaining papers submitted in 2002. Submission to publication time has been reduced by almost one third since 2000. Current goal is to further reduce the average processing time. This is an extremely challenging goal.

Application-specific instruction set processor (ASIP) design is a promising technique to meet the performance and cost goals of high-performance systems. ASIPs are especially valuable for embedded computing applications (e.g., digital cameras, color printers, cellular phones, etc.) where a small increase in performance and decrease in cost can have a large impact on a product's viability. Sutherland, Sproull, and Molnar originally proposed a processor organization called the counterflow pipeline (CFP) as a general-purpose architecture. We observed that the CFP is appropriate for ASIP design due to Its simple and regular structure, local control and communication, and high degree of modularity. This paper describes a new CFP architecture, called the wide counterflow pipeline (WCFP), that extends the original proposal to be better suited for custom embedded instruction-level parallel processors. This work presents a novel and practical application of the CFP to automatic and quick turnaround design of ASIPs. The paper introduces the WCFP architecture and describes several microarchitecture capabilities needed to get good performance from custom WCFPs. We demonstrate that custom WCFPs have performance that is up to four times better than that of ASIPs based on the CFP. Using an analytic cost model, we show that custom WCFPs do not unduly increase the cost of the original counterflow pipeline architecture, yet they retain the simplicity of the CFP. We also compare custom WCFPs to custom VLIW architectures and demonstrate that the WCFP is performance competitive with traditional VLIWs without requiring complicated global interconnection of functional devices. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient hardware architecture to accelerate adaptive deblocking filter of H.264/AVC video coding. Compact data access unit, Line-of- Pixel (LOP) is defined in this paper. Line-of-Pixel and build- in data buffer are employed to simplify data exchange between deblocking filter and outside data memory. Edge filter, which is designed to process each group of pixels on both sides of one edge, is kernel of deblocking filter. It is implemented in multiple parallel pipelines to increase efficiency. By carefully design, the proposed deblocking filter can be embedded in general-purpose processor or DSP to support special instructions for acceleration of software codec. This filter also can be used to full hardware H.264/AVC codec. [ABSTRACT FROM AUTHOR]

Large-scale design optimization of electric machines is oftentimes practiced to achieve a set of objectives, such as the minimization of cost and power loss, under a set of constraints, such as maximum permissible torque ripple. Accordingly, the design optimization of electric machines can be regarded as a constrained optimization problem (COP). Evolutionary algorithms (EAs) used in the design optimization of electric machines including differential evolution (DE), which has received considerable attention during recent years, are unconstrained optimization methods that need additional mechanisms to handle COPs. In this paper, a new optimization algorithm that features combined multi-objective optimization with differential evolution (CMODE) has been developed and implemented in the design optimization of electric machines. A thorough comparison is conducted between the two counterpart optimization algorithms, CMODE and DE, to demonstrate CMODE’s superiority in terms of convergence rate, diversity and high definition of the resulting Pareto fronts, and its more effective constraint handling. More importantly, CMODE requires a lesser number of simultaneous processing units which makes its implementation best suited for state-of-the-art desktop computers reducing the need for high-performance computing systems and associated software licenses. [ABSTRACT FROM PUBLISHER]

The paper deals with a multiple attribute decision making methodology when a decision maker (DM) specifies her/his preferences in imprecise ways, which is basically an extended version of Malakooti's prior work. Usually, it is said that the DM is willing, or able, to provide partial information, because of time pressure, lack of domain knowledge, or data and the like. In this paper, we consider two categories of partial preference information. First, partial information is related to holistic preference judgments about some pair of alternatives. Second, in a situation where the characteristics of some attributes considered are abstract, or non-commensurate, it is sometimes difficult to make an exact performance evaluation of alternatives with respect to those attributes. To circumvent this difficulty, we allow the DM to specify partial information on performance evaluations, which is similar to the types of preference judgments on some pairs of alternatives. Prioritizing multiple attribute alternatives under two categories of partial information causes an intractable nonlinear program, which is the first issue we try to resolve in the paper. We further propose a measure of preference strength as a decision rule. With partial information, often the use of strict dominance rule yields a larger number of non-dominated candidates than the DM wants. Assume a situation where the DM is not willing to provide additional information to reduce the number of non-dominated candidates, but she/he wants to have a single optimal candidate or rank ordering of alternatives. It is then necessary to develop a method like one we propose as a preference strength measure. [ABSTRACT FROM AUTHOR]