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This paper studies simultaneous scheduling of production and material transfer that arises in the semiconductor photolithography area. In particular, the right reticle and right job both need to be present to process the job. Jobs are transferred by a material handling system that employees a fleet of vehicles. Reticles serving as an auxiliary resource are also transferred from one place to another by a different set of vehicles. This intricate scheduling challenge, encompassing jobs, reticles, machines, and two distinct sets of vehicles, is explored here for the first time. The paper introduces a multi-stage methodology that involves relaxation, a constructive heuristic, constraint programming, and a warm-start approach to address this complex problem. [ABSTRACT FROM AUTHOR]

This paper addresses the quality control of the photolithography process in the semiconductor industry. Overlay errors in the process seriously affect the wafer yield, and cause the wafer to be forced to rework and affect the production efficiency of the equipment. We examine the current state of its process control, develop a novel overlay predict model, and verify the prediction results. This study proposes a Global Attention Generative Adversarial Networks (GAGAN) model to precisely predict the overlay error for the feed-forward data of the front layer, which is used as the important information and process parameters for the advanced process control of the current layer. Experiment results on a semiconductor shop-floor confirms that our proposed method achieves high predictive performance while maintaining extensibility and visual quality. [ABSTRACT FROM AUTHOR]

This paper studies the problem of scheduling machines in the photolithography area of a semiconductor manufacturing facility. The scheduling problem is characterized as an unrelated parallel machine scheduling problem with machine eligibilities, sequence- and machine-dependent setup times, auxiliary resources and transfer times for the auxiliary resources. Each job requires two auxiliary resources: a reticle and a pod. Reticles are handled in pods and a pod contains multiple reticles. Both reticles and pods are used on multiple machines and a transfer time is required if transferred from one machine to another. A novel constraint programming (CP) approach is proposed and is benchmarked against a mixed-integer programming (MIP) method. The results of the study, consisting of a real-world case study at a global semiconductor manufacturer, demonstrate that the CP approach significantly outperforms the MIP method and produces high-quality solutions for multiple real-world instances, although optimality cannot be guaranteed. [ABSTRACT FROM AUTHOR]

The targeting of transistor gate length is a primary driver of device performance. The targeting of the physical gate critical dimension (CD) greatly impacts the electrical gate dimension. Traditionally, continual monitoring and manual offsets to compensate for lithographic and etch equipment variability have been used to control gate CDs. This paper discusses how advanced process control techniques were applied to the 0.13-μm polysilicon (poly) patterning process. Both scanner and etch equipment were controlled using a combination of feedforward and feedback loops. As a result, significant engineering labor was saved, and gate CD 3 sigma results improved 12%, correlating to improved device performance and enhanced yield. [ABSTRACT FROM AUTHOR]

A novel semiconductor manufacturing system minimal fab for customized semiconductor devices and micro electro mechanical systems on a half-inch wafer is developed. A distinct feature of the minimal fab is its clean-localized system eliminating a need of cleanroom environment. The clean level of the system is estimated by measuring separately each clean-localized component of the system including a minimal shipping case, wafer carrier, wafer load-lock system, and machine process chamber using a particle counter. The clean level of the system is analyzed to be in the ISO class 4, which is in the same class of a super clean room. In order to confirm the cleanliness needed for device fabrications, we employ a lithography system of the minimal fab consisting of a minimal coater, a minimal maskless exposure system using digital light processing technique, and a minimal developer hybridizing with conventional fab equipment to fabricate a metal-oxide-semiconductor (MOS) field-effect-transistors (FET). The minimum gate-length of the MOSFET is realized at 1 \boldsymbol \mu \textm with a good transistor characteristic. The measured interface states density of 2.33~\boldsymbol \times 10^\boldsymbol 10 cm ^\boldsymbol -2 indicates that the whole processes during the fabrication are in the level of a sufficiently low contamination. [ABSTRACT FROM AUTHOR]