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This paper examines near-capacity dirty-paper code designs based on source-channel coding. We first point out that the performance loss in signal-to-noise ratio (SNR) in our code designs can be broken into the sum of the packing loss from channel coding and a modulo loss, which is a function of the granular loss from source coding and the target dirty-paper coding rate (or SNR). We then examine practical designs by combining trellis-coded quantization (TCQ) with both systematic and nonsystematic irregular repeat-accumulate (IRA) codes. Like previous approaches, we exploit the extrinsic information transfer (EXIT) chart technique for capacity-approaching IRA code design; but unlike previous approaches, we emphasize the role of strong source coding to achieve as much granular gain as possible using TCQ. Instead of systematic doping, we employ two relatively shifted TCQ codebooks, where the shift is optimized (via tuning the EXIT charts) to facilitate the IRA code design. Our designs synergistically combine TCQ with IRA codes so that they work together as well as they do individually. By bringing together TCQ (the best quantizer from the source coding community) and EXIT chart-based IRA code designs (the best from the channel coding community), we are able to approach the theoretical limit of dirty-paper coding. For example, at 0.25 bit per symbol (b/s), our best code design (with 2048-state TCQ) performs only 0.630 dB away from the Shannon capacity. [ABSTRACT FROM AUTHOR]

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation. [ABSTRACT FROM AUTHOR]

We compare the capacity of dirty-paper coding (DPC) to that of time-division multiple access (TDMA) for a multiple-antenna (multiple- input multiple-output (MIMO)) Gaussian broadcast channel (BC). We find that the sum-rate capacity (achievable using DPC) of the multiple-antenna BC Is at most min(M, K) times the largest single-user capacity (i.e., the TDMA sum-rate) in the system, where M is the number of transmit antennas and K is the number of receivers. This result is Independent of the number of receive antennas and the channel gain matrix, and is valid at all signal-to-noise ratios (SNRs). We investigate the tightness of this bound In a time-varying channel (assuming perfect channel knowledge at receivers and transmitters) where the channel experiences uncorrelated Rayleigh fading and In some situations we find that the dirty paper gain is upper-bounded by the ratio of transmit-to-receive antennas. We also show that min(M, K) upper-bounds the sum-rate gain of successive decoding over TDMA for the uplink channel, where M is the number of receive antennas at the base station and K is the number of transmitters. [ABSTRACT FROM AUTHOR]

Torsional oscillations greatly affect performance and. determine the bandwidth (BW) and damping of speed loops. Backlash due to gear reducers can also contribute to the triggering of oscillations, especially when the drive runs at very low load torque. This paper presents a detailed evaluation of these effects in typical electromechanical drive trains applied to paper machine sections. The cases evaluated consider torsional oscillations in two-mass and three-mass systems, and the effect of shaft diameter and length on the resonant frequencies of three typical paper machine sections. Time-domain response plots are evaluated to show the effect of speed response overshoot, reducer backlash, and step or ramp speed commands. Based on these results, mechanical design guidelines are given for the most significant drive train components in order to minimize torsional oscillations of the speed-controlled drive system. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

The IEEE TRANSACTIONS ON SIGNAL PROCESSING is fortunate to attract submissions of the highest quality and to publish articles that deal with topics that are at the forefront of what is happening in the field of signal processing and its adjacent areas. In this column, we are pleased to announce the TRANSACTIONS articles that have been selected to receive 2004 best paper awards. We would also like to encourage our readers to nominate TRANSACTIONS papers for awards. Nominations can be submitted online through the TRANSACTIONS website. [ABSTRACT FROM AUTHOR]

This paper presents a comparison of online to traditional face-to-face delivery of undergraduate digital systems material. Two specific components of digital content were compared and evaluated: a sophomore logic circuits course with no laboratory, and a microprocessor laboratory component of a junior-level computer systems course. For each of these, a baseline level of student understanding was evaluated when they were being taught using traditional, face-to-face delivery. The course and lab component were then converted to being fully online, and the level of student understanding was again measured. In both cases, the same purpose-developed assessment tools were used to carry out the measurement of understanding. This paper presents the details of how the course components were converted to online delivery, including a discussion of the technology used to accomplish remote access of the electronic test equipment used in the laboratory. A comparison is then presented between the control and the experimental groups, including a statistical analysis of whether the delivery approach impacted student learning. Finally, student satisfaction is discussed, and instructor observations are given for the successful remote delivery of this type of class and laboratory. [ABSTRACT FROM PUBLISHER]

This paper introduces the simultaneous partial-inverse problem (SPI) for polynomials and develops its application to decoding interleaved Reed–Solomon codes beyond half the minimum distance. While closely related both to standard key equations and to well-known Padé approximation problems, the SPI problem stands out in several respects. First, the SPI problem has a unique solution (up to a scale factor), which satisfies a natural degree bound. Second, the SPI problem can be transformed (monomialized) into an equivalent SPI problem where all moduli are monomials. Third, the SPI problem can be solved by an efficient algorithm of the Berlekamp–Massey type. Fourth, decoding interleaved Reed–Solomon codes (or subfield-evaluation codes) beyond half the minimum distance can be analyzed in terms of a partial-inverse condition for the error pattern: if that condition is satisfied, then the (true) error locator polynomial is the unique solution of a standard key equation and can be computed in many different ways, including the well-known multi-sequence Berlekamp–Massey algorithm and the SPI algorithm of this paper. Two of the best performance bounds from the literature (the Schmidt–Sidorenko–Bossert bound and the Roth–Vontobel bound) are generalized to hold for the partial-inverse condition and thus to apply to several different decoding algorithms. [ABSTRACT FROM AUTHOR]

Recently demonstrated CMOS circuits based on Ge nanowires (Ge-FET) promise sustained technology scaling because higher mobility Ge guarantees target ${I}_{\text {ON}}$ at a lower ${V}_{{\textit {DD}}}$. Unfortunately, this promise is counterbalanced by the fact that Ge is a poor thermal conductor, thus, the thermal confinement of the surround-gate topology may exacerbate self-heating (SHE) and erode the intrinsic performance gain associated with the high channel mobility. In this paper, we use: 1) electrical and optical methods to, respectively, characterize channel and surface SHE of Ge-FET with various channel lengths ( ${L}_{\text {ch}}$ ), widths ( ${W}_{\text {ch}}$ ), and the number of the nanowires (NWs) (#NW); 2) interpret the results obtained by the 3-D thermal modeling, and compare theoretically the SHE in Ge-FET configured in various topologies, such as bulk FinFET, silicon-on-insulator FinFET, and gate-all-around NW-FET; and 3) embed the results in an electrothermal SPICE simulator to compare the performance of ring oscillators based on Ge-FET and Si-FET. Our results show that the existing Ge-FET (with an airgap) is thermally suboptimal, but once optimized, SHE in Ge-FET would be comparable to that of Si-FET. The results encourage sustained development of Ge-FETs. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) is an unconventional computing technique using digital circuits. It performs arithmetic computation on stochastic bit streams (SBSs), which encode real values through the ratios of ones in the streams. Despite its advantages such as simple arithmetic units and strong error tolerance, SC faces two big challenges: 1) long computation latency and 2) large hardware overhead to generate independent SBSs. A recent work proposes to insert D flip-flops (DFFs) into the stochastic circuit to reduce the overhead to generate SBSs. In this paper, observing that DFFs can also be exploited to reduce circuit delay, we propose a novel method to insert DFFs into a stochastic circuit to simultaneously reduce the computation latency of the circuit and the overhead of generating SBSs, thus addressing both challenges at the same time. Experimental results showed that compared to the state-of-the-art method in optimizing stochastic circuits with DFF insertion, our method can reduce the computation latency by 14.3% and the number of DFFs by 48.1%. [ABSTRACT FROM AUTHOR]

Integrated circuits operated in the near-threshold region exhibit specific merit with high energy efficiency. A near-threshold model is highly required for the circuit design. In this paper, a near-threshold drain current model is proposed based on the surface inversion layer charge model for analyzing digital circuits. The short-channel effect in deep submicrometer is also included in the model. Moreover, the delay and energy parts based on the near-threshold drain current model are derived and integrated in the model. Two process design kits (PDKs) are used for parameter extraction to demonstrate the feasibility of the proposed model. The results show that the proposed model can be used for the near-threshold circuit calculation, with the benefit of high accuracy. [ABSTRACT FROM AUTHOR]

This paper presents a novel and effective logic synthesis flow able to identify threshold logic functions during the technology mapping process. It provides more efficient logic covering, exploring also redundant cuts. Moreover, the proposed design flow takes into account different circuit area estimations, such as the sum of input weights and threshold values, the gate fanin and the number of threshold logic gates. As a result, the mapped circuits present a reduction up to 47% and 67% in area and logic depth, respectively, in comparison to the most recent related approaches. [ABSTRACT FROM AUTHOR]

Timing analysis and timing closure are critical steps in digital circuit design. To ensure an error-free design, timing constraints are usually set-based upon the longest path delay from static timing analysis. However, a circuit could have dramatically different internal activity because of the variation of input workload. The path with the longest delay may not be active for certain input workloads, which would enable timing speculation for increased performance. This paper describes an approach to identify the greatest contributors of timing errors and mitigate those errors by replacing certain standard cells in the design. We evaluated our mitigation for several benchmark designs and demonstrated an error-free performance gain up to 37%. The entire design flow uses Synopsys electronic design automation tools and customized scripts, which can be adapted for other designs. [ABSTRACT FROM AUTHOR]

Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests for single stuck-at faults. DR-scan is able to test memory elements in dual-rail logic without breaking local feedback loops. To reduce test time, we choose a minimum set of selected test configurations (TCs). If there are more than one selected TCs, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our test methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve test coverage up to nearly 94% for various asynchronous circuits. [ABSTRACT FROM AUTHOR]

In this paper, several fundamental pseudo-CMOS digital circuits with n-type indium tin oxide-stabilized ZnO thin-film transistors (TFTs) were implemented and investigated. The optical transmittance of circuits varied from 77% to 92% throughout the visible wavelength band. Electrically, the operation frequency of inverters, nor gates, nand gates, D latches, and D flip flops were all found to exceed 10 kHz with a supply voltage of 10 V. Besides, 13-stage ring oscillators could be operated at 42 kHz with a propagation delay time of $0.92~\mu \text{s}$ when the supply voltage was set as 20 V. Among the state-of-the-art transparent designs, these proposed circuits based on the ITO-stabilized ZnO TFTs exhibited high-speed performance, which were promising as building blocks for transparent electronics with moderate frequency requirements. [ABSTRACT FROM AUTHOR]

In this paper, gate resistance thermometry (GRT) was used to determine the channel temperature of AlGaN/GaN high electron-mobility transistors. Raman thermometry has been used to verify GRT by comparing the channel temperatures measured by both techniques under various bias conditions. To further validate this technique, a thermal finite-element model has been developed to model the heat dissipation throughout the devices. Comparisons show that the GRT method averages the temperature over the gate width, yielding a slightly lower peak temperature than Raman thermography. Overall, this method provides a fast and simple technique to determine the average temperature under both steady-state and pulsed bias conditions. [ABSTRACT FROM PUBLISHER]

This paper describes an extensive analysis of the degradation of (InAlGa)N-based UV-B light-emitting diodes (LEDs) submitted to constant current stress. This paper is based on combined electrical characterization, spectral analysis of the emission, deep-level transient spectroscopy (DLTS) and photocurrent (PC) spectroscopy. The results of this analysis demonstrate that: 1) UV-B LEDs show a gradual degradation when submitted to constant current stress; the decrease in optical power is stronger for low measuring current levels, indicating that degradation is related to the increase in Shockley–Read–Hall (SRH) recombination; 2) the current–voltage characteristics measured before/during stress show an increase in the current below the turn-on voltage, that is ascribed to the increase in trap-assisted tunneling (TAT) components; and 3) DLTS analysis and PC spectroscopy measurements were carried out to identify the properties of the defects responsible for the degradation of the optical and electrical characteristics. The results indicate that stress induces or activates defects centered around 2.5 eV below the conduction band edge. These defects, close to midgap, can explain both the increased SRH recombination and the increase in TAT components detected after stress. Moreover, the DLTS measurements allowed to identify the signature of Mg-related acceptor traps. [ABSTRACT FROM PUBLISHER]

This paper addresses theoretical aspects of arithmetic circuit verification based on algebraic rewriting. Its goal is to advance the understanding of algebraic techniques for arithmetic circuit verification in the context of symbolic computer algebra. The paper offers a new insight into the arithmetic circuit verification problem, by viewing the computation performed by the circuit as the flow of digital data. In the proposed bit-flow model, the circuit is modeled as a network of logic components satisfying a bit-flow conservation law. We prove that the value of the flow of data in the circuit is invariant throughout the circuit and use this to prove soundness and completeness of the rewriting technique, independently from the computer algebra arguments. The efficiency of the method is illustrated with impressive results for large integer multipliers. The verification system and benchmarks are offered in an open source software environment. [ABSTRACT FROM AUTHOR]

In this paper, the performance of dual-k spacer asymmetric underlap FinFET (DKAU-FinFET) is analyzed. The significance of using dual-k spacers is illustrated considering the parasitic outer fringing capacitance. The study also presents physical insights into inversion charge modulation by dual-k spacers in DKAU-FinFETs. In addition, the proposed device structure is analyzed for analog, RF, and digital circuit performances. Based on the performance analysis, the use of optimum inner high-k spacer thickness is proposed for reliable device performance. [ABSTRACT FROM PUBLISHER]

Viterbi detectors are widely used in all communication systems dealing with transmission and storage. In this paper, we develop the theory and design architecture for a 2-D separable iterative soft-output Viterbi detector (SISOVD) for applications in 2-D storage channels extending the original work from Wu et al. (IEEE Trans. Magn., vol. 39, no. 4, pp. 2115–2120, Jul. 2003). The contribution of this paper is twofold. First, we design a non-binary soft Viterbi detector that will be used as the core engine for the SISOVD and show its equivalence to the max-log-MAP algorithm implementation. We also study the performance of the algorithm through simulations under various design parameter constraints toward a systems architecture. Second, we propose a novel digital circuit that incorporates non-uniform quantization within a sliding block design framework. The proposed detector system architecture is tested within an field programmable gate array platform and proved to be efficient in terms of resource utilization, timing, and power compared with a conventional uniform quantizer with no signal-to-noise ratio performance degradation. It shows a 13.28% reduction in the total number of slice registers, 30.26% reduction in the slice lookup tables, 21.23% reduction in the critical path delay, and 14.84% reduction in the power consumption compared with the uniform quantizer. [ABSTRACT FROM AUTHOR]

This paper presents the design and verification of a proposed 30-GHz power-efficient phase-locked loop (PLL) frequency synthesizer for 60-GHz applications. Fabricated by a commercial 0.18- \mu \textm SiGe BiCMOS process, the synthesizer employs coupled LC tank voltage-controlled oscillator, high power-added efficiency amplifier, reconfigurable divider realizing fractional division ratios for choice of multiple reference frequencies and low operation power, a programmable charge pump, an internal loop filter, and an integrated slave serial peripheral interface. The PLL synthesizer (PLLS) provides output frequency from 29.5 to 33.4 GHz with phase noise of −97 dBc/Hz at 1-MHz offset. The integrated phase noise over the frequency of 10 kHz–10 MHz is 2.05° rms at a frequency of 30.24 GHz. Operating with a single 1.8-V supply voltage, the PLLS consumes a low power of 63 mW and occupies an area of 2.8 mm $\times$ 1.86 mm. [ABSTRACT FROM PUBLISHER]

This paper discusses improvements to a lateral bipolar device capable of integration into the existing CMOS process flow. With the help of simulations, we demonstrate that the emitter transit time limits the cutoff frequency of a lateral bipolar device. We show that with the introduction of a heterojunction and a partially depleted base, we can decrease the emitter transit time and increase the current gain and the cutoff frequency ( ft) of the device. For a balanced design, our simulations indicate an n-p-n device with an ft of 812 GHz and an fmax of 1.08 THz; and a p-n-p device with an ft of 635 GHz and an fmax of 1.15 THz. The collector current at cutoff frequency for both n-p-n and p-n-p devices is $\sim 0.03$ mA—roughly 100 times lower than commercial vertical heterojunction bipolar transistors. [ABSTRACT FROM AUTHOR]