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This paper focuses on the in-depth analysis of the physical mechanism of the broadband frequency domain spectroscopy of oil-paper insulation. The complex permittivity shows two low-frequency dispersion phenomena, and the real part of the complex conductivity exhibits two slope changes under the synergistic effect of aging and moisture. The two slope changes are mainly attributed to the migration characteristics of water molecules and polar aging products with a degradation of the oil-paper insulation, resulting in the transition of the frequency dependence between the DC conductivity and AC conductivity. When the oil-paper insulation deteriorates seriously, the imaginary part of the dielectric modulus shows double relaxation peaks. Physical models of parasitic capacitance and molecular polarity interface polarization are proposed to reveal the physical mechanism of the double relaxation peaks. The left peak of the double relaxation peaks is caused by the accumulation of water molecules and polar aging products at the electrode/insulation interface, and the right peak is due to the charge disturbance of the cellulose molecular chain surface. This paper can provide theoretical support and technical guidance for the condition diagnosis and evaluation of oil-paper insulation. [ABSTRACT FROM AUTHOR]

A capacitor formed of fluid-impregnated paper metalized on one side and a polymer film results in a relaxation peak caused by the much more rapid polarization of the dielectric fluid impregnated paper relative to the polymer film. This results in the capacitance being a function of frequency, with a substantial increase in capacitance at very low frequencies. A theory for such a capacitor is developed and compared with measurements on actual capacitors with relatively good agreement. The implications of the theory for discharge current and discharge efficiency are discussed. [ABSTRACT FROM AUTHOR]

The Potential Transformer (PT) plays an important role in the measurement and monitoring of the power system. The accurate modeling of the PT is very important but not yet perfect. The stray capacitance will have a non-negligible effect on the performance of a PT. However, the influence of stray capacitance is rarely considered in existing models, which makes the broadband simulation performance weak and provides limited references in engineering. In this paper, a calculation method of PT stray capacitance is proposed to analyze the performance of the PT at different frequencies and extract the capacitive current of the PT port. This paper used a non-destructive method to obtain the test data of a PT, calculated the value of the stray capacitance, and drew the hysteresis loops of the iron core. A corresponding simulation model was established to predict the PT performance at different frequencies. The simulation results are in good agreement with the experimental data, which proves the accuracy of the modeling parameters. The data processing logic is clear and is easy to be simplified by programming, which makes it promising in engineering. [ABSTRACT FROM AUTHOR]

In this paper, an inner ultrathin oxide metal–oxide–semiconductor (MOS) capacitor is fabricated with another outer MOS-gate ring as a coupling controller. Capacitance–voltage characteristics of inner MOS capacitor show that the excess minority carriers supplied from the outer MOS-gate ring can efficiently change the inner capacitance (${C} _{\text {inner}}$). It is observed that outer MOS-gate ring under the conditions at floating and at ground has quite different coupling effects on ${C} _{\text {inner}}$ when the inner MOS is biased at 1 V. Comparing to ${V} _{\text {outer}} = \text {floating}$ , ${C} _{\text {inner}}$ reduces significantly when ${V} _{\text {outer}} = {0}$ V at 1k Hz. The transient behavior of ${C} _{\text {inner}}$ as ${V} _{\text {outer}}$ changes from 0 V to floating is long enough to read, and the difference of two capacitance values can be regarded as two states. As a result, a two capacitance states operation is proposed for possible memory application. Based on the experimental results, the possible memory cell configuration is designed. Comparing to the present emerging memories, since the two states in this paper are in conditions of floating and 0 V, ultralow power is consumed, which is believed a promising concept for future memory application. [ABSTRACT FROM AUTHOR]

Virtual synchronous generator (VSG)-based control approaches for AC machine drivers have attracted much attention in recent years. The contradiction between the strong motor loading capacity and the small DC voltage fluctuation is disregarded in previous studies. A larger virtual inertia is required to raise the torque gain and drive the motor with heavier loads, thus resulting in greater DC voltage variations. A systematic method is proposed for the optimal design of the virtual inertia for VSG-based motor starting systems to achieve the maximal motor loading capacity and the low DC voltage fluctuation in this paper. Firstly, the relationship between the virtual inertia and the loading capacity is revealed on the basis of the closed-loop analysis. Considering the DC voltage variation, the constraint on the maximal value of the virtual inertia is proposed from the energy-balance perspective despite the unknown contribution of the DC capacitors to the virtual inertia. To fully exploit the energy storage capacity of the DC capacitors and raise the upper limit of the virtual inertia under the same permitted DC voltage variation, a modified DC voltage reference is introduced. Extensive simulation and experimental results are presented to validate the effectiveness of the proposed methods. [ABSTRACT FROM AUTHOR]

Ground wires (GW) struck by lightning are often exposed to transient impulse voltages in the MV range. This results in intense negative streamer-type corona, causing a considerable increase in the effective wire capacitance and a corresponding reduction in its surge impedance. Such variables have a significant influence on the tower top potential and on the electromagnetic coupling between the ground wire and phase conductors. Presently there is considerable uncertainty regarding the impulse corona parameters to be used in back flashover calculations. In the present paper a new method is formulated for determination of GW impulse corona parameters. The new approach is compared with two existing methods and with available experimental results. It is found that the method usually used within the IEEE has little physical justification and is excessively conservative. It is also shown that such corona parameters significantly depend on the GW height above ground, which has been totally ignored in the CIGRE method. This and other unjustified simplifying assumptions explain the surprisingly large discrepancy between values of the negative impulse corona constant recommended by CIGRE and IEC. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

Isentropic compression experiments (ICEs) are an important method to study the dynamic characteristics of materials at pressures, temperatures, and stress or strain rate not attainable in conventional shock experiments. Yet it makes high demands toward the precise current pulse tailoring capability of the source. The China Academy of Engineering Physics is now developing a 20-brick parallel discharge driver and a 256-brick parallel discharge driver (CQ-7) to improve the performance and flexibility of compact magnetic compression devices. The load current of ICEs is tailored by optimizing the switch trigger sequence and the brick charging voltage. This paper establishes the equivalent circuit model of the 20-brick parallel discharge driver, taking the distributed inductance, resistance, and capacitance of transmission plates into account based on the partial-element equivalent circuit method. Besides, the equivalent circuit model of discharge brick based on the switch arc resistance model is also established to study the influence of key structural parameters on the output current. Furthermore, by comparing the simulation and experimental results of simultaneous discharge of 20-brick driver, the accuracy of simulation model is confirmed. This paper is of great significance to the design and optimization of multibrick parallel discharge drivers. [ABSTRACT FROM AUTHOR]

In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with L\mathrm{ eff}= 36 nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for fT , f\mathrm {\mathrm {MAX}} , and NFmin at 26 GHz up to ~13%, ~24%, and ~18% compared with the reference layout scheme, respectively. [ABSTRACT FROM PUBLISHER]

DC shipboard power systems have been considered as a promising solution for stricter environmental regulations on ships due to their main benefits in fuel savings with variable speed engines and easy integration of energy storage systems. In order to employ the dc solution in the shipboard power systems, the dc power systems have to be protected from a system fault with protection selectivity to minimize impacts of the fault or to avoid other undesirable situations in the system. For low-voltage dc shipboard power systems, a three-level protection has been proposed: 1) fast action (first)—bus separation by solid-state dc bus-tie switch; 2) medium action (second)—feeder protection by high-speed fuse; and 3) slow action (third)—generator–rectifier fault controls. This paper proposes a new method by means of additional bus capacitance added in main dc buses to help reliable operation of the three-level protection. The principle of the proposed method is introduced and the sizing of the additional bus capacitance is addressed in this paper. With the modeling of the dc shipboard power systems, the analyses of voltage drops for the bus separation failure and fault clearing time for the feeder protection are carried out to verify the proposed method. The results show that the proposed method not only mitigates the voltage drop for the bus separation failure, but also achieves the selectivity and the sensitivity for the feeder protection. [ABSTRACT FROM AUTHOR]

This paper presents a unique methodology to calculate the filtering capacitances of the OpAmp already reported in the literature. The methodology aims to show that there is an optimal solution that can be used to increase the electromagnetic interference (EMI) immunity of any OpAmp for a wide range of frequencies. By using this proposed methodology, an OpAmp structure that reduces the EMI effect is designed in standard 0.18\ \mu \textm mixed-mode CMOS technology. Detailed mathematical analyses and simulation results are presented and discussed. Simulation results show that the maximum EMI-induced offset voltage in the frequency range from 1 MHz to 1 GHz for the OpAmp is 4.4 mV. In contrast, the standard Miller OpAmp exhibits a maximum EMI-induced offset voltage of 92.4 mV under the same operating conditions. [ABSTRACT FROM PUBLISHER]

In this paper, we present a surface potential-based explicit continuous model for a metal-ferroelectric-insulator-semiconductor (MFIS) type gate-all-around negative capacitance transistor (GAA-NCFET). Unlike previously reported models, an explicit formulation to calculate the electrical characteristics of GAA-NCFET is proposed. Our model includes the radial dependence of the electric field in the ferroelectric, ignored in the previous works and accurately captures ferroelectric material parameter variations in the nonhysteretic regime. In contrast to bulk NCFETs, GAA-NCFET characteristics show different bias dependence due to the absence of bulk charge. We also present analytical expressions for the terminal charges which are essential to obtain the trans-capacitances for transient simulations. We find that, compared with conventional MOSFETs, the gate charge saturates to a different fraction of its maximum value. Furthermore, the modeling of quantum mechanical effect and overlap capacitances in an MFIS NCFET structure is discussed. Finally, the proposed model has been implemented in Verilog-A and tested for the transient response of ring oscillator in a commercial circuit simulator. [ABSTRACT FROM AUTHOR]

In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III-V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor charges by considering the wave function penetration into the gate insulator, effective mass discontinuity at the semiconductor-oxide interface, 2-D confinement in the NW, and Fermi-Dirac statistics. The semiconductor charge expression proposed in this paper is completely explicit in terms of applied gate voltage, therefore, making it highly suitable for large circuit simulations. The model is also compared with the results from self-consistent Schrödinger-Poisson solver for different NW sizes and materials and found to be accurate over a wide range of gate voltages. [ABSTRACT FROM AUTHOR]

In this paper, we report a physics-based compact model for monolayer graphene field-effect transistors (m-GFETs) based on the 2-D Density of States of monolayer graphene and the drift-diffusion equation. Furthermore, the Ward-Dutton charge partitioning scheme has been incorporated to the model extending its capabilities to AC and transient simulations. The model has been validated through comparison with DC and RF measurements from two different long-channel m-GFET technologies. Moreover, values of parasitic elements included in the model are extracted from measurements on dedicated test structures and verified through electromagnetic simulations (EM). Finally, an EM-SPICE co-simulation has been carried out to assess the applicability of the developed m-GFET model for the design of “balun” circuits. [ABSTRACT FROM PUBLISHER]

The fault resistance and infeeded currents from tapped transmission lines are the two main challenges to establish correct fault location estimation in multi-terminal transmission lines. Also, fault location estimation in double-circuit lines is more complicated than single-circuit lines due to the effect of mutual coupling and inter-circuit faults. This paper proposes a negative-sequence network-based method to estimate the fault location of double-circuit multi-terminal transmission lines. In the presented method, signals are measured in the relay location and then, communication links are not required as it uses only one end measurements. Also, in conventional distance relays, six elements are needed to calculate the fault location in all types of faults. Furthermore, in this method, by using only one element for each transmission line, accurate fault location can be estimated. Also, high fault resistance, mutual coupling, and infeeded currents from tapped transmission lines do not have impact on the performance of the presented scheme. To investigate the effects of the line shunt capacitances on the proposed method, a PI model of the transmission lines is used in all the investigations. Simulation results carried out using MATLAB software indicate that the proposed scheme is able to produce excellent performance for the fault location estimation. [ABSTRACT FROM AUTHOR]

This paper investigates the fin-width ($\text{W}_{\textsf {Fin}}$) sensitivity of threshold voltage ($\text{V}_{\textsf {T}}$) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ for NC-FinFETs. Our study may provide insights for future scaling of FinFETs. [ABSTRACT FROM AUTHOR]

In this paper, uniformly doped drift region of silicon carbide (SiC) super-junction (SJ) MOSFET is replaced with vertical variable doping profile (VVD) to achieve a better tradeoff between breakdown voltage (BV) and specific ON-resistance (${R}_{\text {sp,on}}$). While it is known that the SJ device consists of two vertical columns of n- and p-type, SJ VVD feature lies in increasing the doping concentration from top to bottom in the N-column and vice-versa in the P-column within the drift region. The proposed SJ VVD allows $\text {R}_{{\text {sp, on}}}$ to reduce further due to increased average doping concentration in conducting N-column and BV to increase further due to shifting of an electric field from corners to the center of the drift region. BV and ${R}_{\text {sp,on}}$ improved by 10% in an SJ VVD MOSFET and these parameters follow linear relationship similar to SJ MOSFET. The 2-D numerical simulations from Synopsys TCAD are used for investigating the static and dynamic characteristics of the device. In addition to 30% improvement in Baliga figure of merit, 35% improvement is obtained over SJ MOSFET in turn on and turn off switching energies for a clamped inductive circuit at 1200 V–20 A. Improved dynamic characteristics of SJ VVD can be attributed to reduction in gate charge (${Q}_{g}$) and miller capacitance (${c}_{\text {rss}}$) compared to SJ MOSFET. [ABSTRACT FROM AUTHOR]

This paper presents the accurate modeling of HVdc links for the dynamic studies of automatic generation control/load frequency control (AGC/LFC) of the multiarea interconnected power system. In earlier AGC studies, HVdc links were simply modeled by using the first-order transfer function with system time constant ${T_{{\rm{dc}}}}$. It was argued that ${T_{{\rm{dc}}}}$ is the time required by HVdc links to establish dc current after following a load disturbance in the power system. However, no mathematical or analytical justification was provided in support to the existing transfer function model of HVdc links. This paper presents the accurate modeling of HVdc links for AGC studies. The comparative analysis has also been performed to demonstrate error being accrued due to the use of the conventional model of HVdc links. Furthermore, this paper also implements the inertia emulation based control strategy in AGC, which allows us to harness the stored energy from the capacitance of HVdc links for AGC operations. [ABSTRACT FROM AUTHOR]

Photoelectric characteristics are an important reference for high-voltage discharges and are closely related to the excited mode of the high-voltage source. In this paper, we built a large-scale volume dielectric barrier discharge (DBD) system, which is composed of multilayer parallel-plate DBD electrodes and is excited by a high-voltage source in the power density modulation (PDM) mode. Subsequently, we analyzed the applied energy equation and evaluated the DBD systems photoelectric characteristics. The results show that the energy values of different applied voltage cycles during a PDM period exhibit significant differences. However, the average energy in a PDM period is approximately constant. Moreover, the equivalent capacitance of the DBD cell is a function of both the applied voltage and energy density. For the DBD cell, with the increase in both the applied voltage and energy loaded on the DBD cell, the total equivalent capacitance ($C$) is approximately constant, the dielectric capacitance ($C_{\mathrm{ d}}$) increases exponentially and decreases linearly, while the discharge gap capacitance ($C_{\mathrm{ g}}$) decreases and increases in the same cases. In addition, the relative intensities of the discharge emission increase and the energy efficiency ratios of the relative photoquantum yield of active species decline with the increase in both the applied voltage and energy density loaded on the DBD cell. The experimental results have been analyzed by evaluating the influence of the electrical parameters, and the underlying physical principles have been discussed. This paper clearly demonstrates that the photoelectric characteristics of the DBD reactor are significantly influenced by both the applied voltage and energy density, thus providing helpful insights into the energy evaluation and application of high-voltage discharges. [ABSTRACT FROM AUTHOR]

This paper presents an efficient parameter extraction method applied to GaN high electron mobility transistors. The procedure only relies on ${S}$ -parameter measurements at cold bias conditions to extract the extrinsic parameters of a 19-element small-signal model. Hybrid technique of particle-swarm-optimization and direct fitting has been developed and implemented. The extraction procedure has been optimized to consider measurements uncertainty and improve the reliability of the extraction. The procedure has been validated by multibias extraction for different device sizes. A very good agreement between simulations and measurements has been obtained. [ABSTRACT FROM AUTHOR]

Compact flicker noise models used in SPICE circuit simulators are derived from the seminal BSIM unified noise model. In this paper, we show that use of this model can give anomalous bias dependence of input referred noise. In addition, we find that the state-of-the art flicker noise models are not adequate to capture the drain bias dependence of flicker noise in short channel devices. In this paper, we address both the issues with a new compact model. [ABSTRACT FROM AUTHOR]

This paper presents a novel oscillation wave test system (OWTS) to detect the partial discharge (PD) of mounting defects in power cable insulation. In the proposed system, a charging capacitor is added to the circuit topology based on the traditional OWTS. The charging capacitor is charged to the desired voltage by a high-voltage DC power source. After the charging process, the test cable sample is charged by the capacitor. The resonant circuit is formed by the charging capacitor, the test cable, and the resonant reactor to create an oscillating decay voltage. With this novel method, no space charge is injected into the cable insulation. The effect of the charging capacitance on the charging efficiency is calculated with the Multisim software. This paper describes the working principle and the assembly of a laboratory prototype for the PD detection of a 500 m cable circuit. The test results show the feasibility of the novel OWTS method. [ABSTRACT FROM AUTHOR]

In this paper, we explore the electrical characteristics of ring oscillator (RO) by optimizing fabrication inline windows of 16-nm high- \kappa /metal-gate bulk FinFET devices. Key process parameters are ranked according to ROs’ performance, including effective capacitance ( C_{\mathrm {eff}}) , effective resistance ( R_{\mathrm {eff}}) , and integrated circuit quiescent current (IDDQ). Process-dependence factors are then extracted and classified to reveal the actual root cause of each cluster. The findings of this paper indicate the dual gate spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant affect C\mathrm {eff} , R\mathrm {eff} , and IDDQ significantly, but the variation source of these parameters is the thickness of the dual gate spacer. Furthermore, impacts of the ON-state current ratio of N/P devices on delay and IDDQ of RO are examined by replacing dual spacers with single ones, the uniformity of implantation can be enhanced. Thus, the fluctuation of IDDQ is seven times reduced (from 252 to 37 nA) and RO characteristic can fit to designing target. [ABSTRACT FROM PUBLISHER]

In this paper, the performance of dual-k spacer asymmetric underlap FinFET (DKAU-FinFET) is analyzed. The significance of using dual-k spacers is illustrated considering the parasitic outer fringing capacitance. The study also presents physical insights into inversion charge modulation by dual-k spacers in DKAU-FinFETs. In addition, the proposed device structure is analyzed for analog, RF, and digital circuit performances. Based on the performance analysis, the use of optimum inner high-k spacer thickness is proposed for reliable device performance. [ABSTRACT FROM PUBLISHER]

Circuit-level models are developed to determine the upper bound on the performance of a 3-D IC link with through silicon vias (TSVs). It is shown that the performance of a 3-D link is limited not only by the on-chip interconnect RC, driver resistance, and TSV capacitance, but also by the current carrying capacity of the on-chip wires connecting the TSV to the input/output (I/O) driver. The models developed in this paper are used to optimize the I/O driver size, the number of on-chip wires connecting the TSV to the driver, and the data-rate to maximize the aggregate bandwidth per unit energy. Furthermore, in order to maximize the aggregate bandwidth of a 3-D link, it is shown that splitting the TSV array into smaller subarrays and placing the I/O drivers closer to the TSVs is better compared with having large TSV arrays. [ABSTRACT FROM AUTHOR]

Light-emitting diode (LED) components used in lighting or backlighting applications remain operational for a long time, but in some cases, early catastrophic failures and degradation of the photocolorimetric characteristics are observed. Hence, manufacturers are highly interested in early detection of degradation mechanisms and the relationship between electrical signature evolutions and aging in order to predict the remaining lifetime of LED components. This paper describes a methodology to identify future characteristics degradation based on electrical signatures observed within the first hundred hours using an accelerating aging method. For that purpose, four kinds of high-power LEDs are submitted to temperature stress conditions that provide early aging electrical signatures. The first part of this paper describes the experimental setup and the aging protocol. In the second part, we present signatures obtained via current–voltage ( $I$– $V$) and capacitance–voltage ( $C$– $V$) data. [ABSTRACT FROM AUTHOR]

This paper presents an improved dc-link voltage balancing algorithm for a three-level neutral-point-clamped inverter by considering phase current direction. Detailed studies on the effects of change in load current direction on the dc-link capacitor voltages are presented. A maximum value of power factor is numerically derived, above which it affects the capacitor voltage balancing capability. Compared with the previously presented research work, the inputs to the space-vector pulsewidth-modulation block are the three phase currents and the difference between the two capacitor voltages. Depending on the states of the two dc-link capacitor voltages and phase current direction, redundant voltage vector sequences are selected. The selected vectors keep the capacitor voltage deviations within 5% of the total dc-link voltage. Two zero switching vectors (i.e., PPP and NNN) are also removed from all subsectors of the earlier proposed strategy, which one used to produce higher common-mode voltages. Detailed simulation and experimental results are presented in this paper for a 6.0-kW surface permanent-magnet synchronous machine. Both the simulation and experimental results show the required performance of the proposed system. [ABSTRACT FROM AUTHOR]

A space vector modulation (SVM) technique of a dual-inverter system for an open-end winding motor drive is described in this paper, where one inverter has a battery power source and the other has an only capacitor across the dc bus. The SVM must be achieved to operate the motor with field-oriented control and simultaneously to control the capacitor voltage at a constant value by using redundant switching states of the dual-inverter system. The control of the capacitor voltage is carried out by selecting a charging or a discharging mode in each redundant switching state, taking the instantaneous motor power factor into account. In addition, it is also required to reduce the error voltage pulses, which are generated in output multilevel voltage waveforms during the dead time. The compensation method of the existing dead-time scheme and the improved SVM sequence to reduce the error voltage vectors are proposed in this paper. The proposed methods are examined through several experimental tests and are confirmed to generate superior output voltage waveforms from the viewpoint of the measured total harmonic distortion and dv/dt. [ABSTRACT FROM AUTHOR]

This paper investigates the dependence of the supercapacitor Peukert constant on its terminal voltage, aging condition, and operating temperature. Recent studies show that the charge delivered by a supercapacitor during a constant current discharge process increases when the discharge current decreases if the discharge current is above a certain threshold, i.e., Peukert's law applies. By conducting extensive experiments using three supercapacitor samples with different rated capacitances from different manufacturers, this paper reveals that the Peukert constant increases when the initial voltage of the constant current discharge process is lower, the supercapacitor is more heavily aged, or the operating temperature is lower. The physical mechanisms accounting for the Peukert constant dependence are illustrated by analyzing an $RC$ ladder circuit model. When the supercapacitor terminal voltage is higher, the aging condition is lighter, or the operating temperature is higher, more charge is stored in the supercapacitor. Consequently, when the same discharge current is applied, the discharge time is longer and the branch capacitors are more deeply discharged. Therefore, the relaxation effects of the slow branches are reduced and the supercapacitor behaves more like a single capacitor rather than a distributed capacitor network, which ultimately leads to a lower Peukert constant. [ABSTRACT FROM AUTHOR]

The design and development of a new nonintrusive-type true-rms ac voltage measurement probe are presented in this paper. The measurement circuit of the capacitively coupled nonintrusive voltage sensor is designed to provide an output that is directly proportional to the rms value of unknown ac voltage $\text{V}_{\mathrm {X}}$ , which contains the power frequency (50 or 60 Hz) component along with the typical harmonic frequency components due to nonlinear loads. This is accomplished by a specially designed autobalancing signal conditioning circuit. The existing noncontact probes are designed for a set frequency and will not provide accurate rms value of a signal that has multiple frequency components. The output is independent of the coupling capacitance between the probe electrode and the insulated wire/cable under measurement. Thus, the sensor has low sensitivity to the variation due to the probe-to-wire capacitance, good linearity (0.95%), and accuracy (0.88%) over a range of voltages (0–1000 V) tested. Various parameters that affect the performance of the probe are analyzed, quantified, and discussed in this paper. A prototype of the probe along with the proposed autobalancing circuit has been designed and developed. The prototype has been tested in detail to evaluate the accuracy, linearity, and repeatability. The results obtained established the practicality of the proposed scheme. [ABSTRACT FROM AUTHOR]

The capacitance of sub-module capacitor has a great impact on the cost, size, and operation of the modular multi-level converter (MMC). However, the capacitance selected by the existing methods does not always meet the requirement in practice. To find out the reasons for this improper selection, the existing selection methods are analyzed in this paper. Based on the analysis, a new capacitance-selection method is proposed. In the new method, the problems of the existing methods are solved, and the calculation of capacitor voltage is based on a proposed capacitor-voltage model whose calculation error can be smaller than 0.1%. Furthermore, the Secant Method is used in the capacitance selection to quickly calculate the required capacitance. The new capacitance-selection method can be applicable to the MMC not having a circular operating region. In addition, this paper found that the capacitor voltage and the capacitor-voltage ripple reach their maximum values when the power-factor angles of the MMC are –π/2 and π/2, respectively, and the dc component in the capacitor voltage changes according to the operating condition of the MMC. Finally, the proposed selection method and theoretical analyses are verified by both simulation and experiment. [ABSTRACT FROM AUTHOR]

In low-power applications of photovoltaic (PV) systems, the transformerless grid-connected inverters have been preferred to increase the efficiency and reduce the cost, size, and power losses when they are compared to the ones with the transformer. A transformerless single-phase inverter topology with a single dc-link capacitor for the grid-connected PV systems is proposed in this paper. The proposed inverter has been simulated by using a cooperation process of the MATLAB and SPICE package programs and it has been implemented for experimental verification. The proposed inverter reduces the high-frequency common-mode leakage current caused by parasitic capacitances of PV panels, whereas it is controlled with the unipolar sinusoidal pulsewidth modulation. Also, the results show that the common-mode voltage remains constant. The efficiency of the proposed inverter has been compared to that of the most common topologies having the dc-link decoupling during the zero voltage states. This paper is accompanied by a video file demonstrating the power loss distribution in the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a series-capacitor-based interleaving buck power factor correction (PFC) converter is proposed, the intermediate energy storage capacitance of which is operated at discontinuous capacitor voltage mode (DCVM), and automatic power factor (PF) correction for this converter is obtained. Moreover, the voltage across the series capacitor of the proposed PFC converter is clamped at the input voltage, and thus peak voltage stress existed in the traditional DCVM buck PFC could be relieved. By effectively regulating the charge/discharge time for the series capacitor, ultrahigh step-down conversion ratio of the proposed converter is achieved, the conversion ratio of which is independent of the duty cycle and only related to the switching frequency and circuit parameters. Therefore, high PF can be obtained due to very narrow deadtime of the input current. Meanwhile, the proposed PFC converter can realize the soft turn-on of part power switch and soft turn-off of part power diodes. In addition, comparing with the traditional discontinuous inductor current mode PFC, the input current of the proposed PFC converter is continuous so that the peak value and root-mean-square value of input current can be reduced. The operational principle, performance analysis, and parameter design principle are given in this paper. The analysis results show that the PF and total harmonic distortion are also independent of the duty cycle. Finally, a 220-Vac input, 60 W/15 V output experimental prototype is built to verify the validity of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents the reduction of noise and vibration concerning the magnetostriction effects for a single-phase power transformer with a large capacity of 200 MVA. Two magnetic core shapes are investigated: 1) D-yoked core and 2) square-yoked core. The D-yoked core is used for the construction of the transformer prototype in this paper. The magnetostriction and the hysteresis loop of the core material are measured for the simulation and analysis of noise and vibration. The transformer prototype is assembled with an external clamping force applied on the core, and the core vibration and sound-level are observed. The transformer operates with a periodic excitation that may induce resonance in the core. To avoid this, a finite-element analysis is used for modal analysis to identify the natural frequencies of the core. A tank is also designed with a sufficiently rigid structure to avoid resonances. The sound-level of the fully assembled transformer prototype is measured, and it is found to have a low-noise level below 65 dB. [ABSTRACT FROM AUTHOR]

The overwhelming trend within the industry today is to pair electric machines with variable-frequency drives. It is well known that the use of these drives can introduce high-frequency bearing currents during semiconductor switching events. This paper focuses on bearing discharge currents that gradually degrade the bearings by pitting their surfaces and can lead to premature failure. Common solutions include insulating the bearings, installing common-mode filters, or using a brush to ground the rotor shaft. These solutions are not universally scalable and may require periodic maintenance. This paper presents a new approach using noncontact (brushless) capacitive coupling. Here, a rotating capacitor is placed electrically in parallel with the bearing. At high frequencies, the impedance of the rotating capacitor is far lower than the bearing impedance, thereby shunting current around the bearings and reducing shaft voltage. The technique is experimentally demonstrated on a 3-hp (2.2-kW) induction machine. The experiment demonstrates a bearing current reduction factor of at least 8x. [ABSTRACT FROM PUBLISHER]

This paper presents a procedure for evaluating self-capacitances and parasitic capacitors between physically adjacent turns in multiconductor systems—with a special focus on single-layer air-core inductors. To this end, the paper proposes the use of standard cells, which correspond to a minimal and basic turn, layer, or macrolevel arrangement of a winding in reference to its patterns of stored electrostatic energy. A standard cell embraces mathematical rules derived by means of a curve fitting approach through a set of finite element analysis (FEA) simulations. Besides, it is applied in a matching routine wherein self- and stray capacitances are evaluated according to the relative position of each turn, layer, or macrolevel arrangement along the length of the winding. Finally, the analytical technique is validated by comparing frequency-domain results obtained from an implemented SPICE model and laboratory measurements. [ABSTRACT FROM PUBLISHER]

This paper presents a detailed analysis of the time dynamics of the gate-induced drain leakage (GIDL)-assisted increase of the string potential in vertical-channel 3-D NAND Flash arrays. The string potential and the GIDL current waveforms are first studied with close attention by means of technology computer-aided design simulations, highlighting the major phases of their time evolution. A compact model able to reproduce the string behavior is then presented and successfully tested for a variety of electrical waveforms applied to the string contacts, for increasing number of cells in the string and for different string geometrical parameters. The compact model represents a valuable tool to design and optimize the GIDL conditions for the best erase performance. [ABSTRACT FROM AUTHOR]

This paper discusses the impact of small dc capacitance in a motor drive using a floating capacitor H-bridge topology. The proposed topology is intended for applications where variable frequency control is not required. Special attention is paid on investigating the second-order dc capacitor voltage ripples, whose influence on the induction motor as well as on the motor drive itself is of importance. This issue is addressed in this paper through rigorous mathematical formulations. It is found that by inverting the second-order dc ripple voltage using the conventional SVPWM, no harmful harmonics will be generated in the motor line voltage. This demonstrates the possibility of drastically reducing the dc capacitance of the proposed system. Induction motor as well as H-bridge performance with respect to different dc capacitance values is demonstrated by experiments, which lays the foundation for cost reduction and reliability enhancement of the proposed system. [ABSTRACT FROM PUBLISHER]

Through numerical simulations corroborated by an analytical subthreshold model considering drain coupling, this paper systematically investigates the short-channel effects in negative-capacitance FETs with 2D MoS2 channel (2D-NCFET). Our study indicates that, due to the impact of drain coupling on the negative-capacitance effect, the 2D-NCFET exhibits distinct short-channel behaviors such as improved average subthreshold swing and threshold-voltage roll-up with decreasing gate length. In addition, the fringe field through the high-k interlayer dielectric can significantly alter the subthreshold characteristics of the short-channel 2D-NCFET, and hence needs to be carefully taken into account. Our study may provide insights for device design using negative-capacitance FETs. [ABSTRACT FROM AUTHOR]

The metal--insulator--semiconductor capacitor formed by a through-silicon via (TSV) with its insulating layer and the p-type Si substrate may show an anomalous inversion behavior in the C--V characteristic. The dominant cause is the presence of positive charges in the backside (BS) passivation layer. In this paper, a dedicated test structure is proposed and characterized to confirm this hypothesis. Furthermore, a charge-free oxide/nitride BS passivation layer for preventing the anomalous C--V inversion, proposed in our previous work, is validated by experimental results on TSV structures manufactured up to the complete BS metallization processing. [ABSTRACT FROM AUTHOR]

In this paper, a new method for equivalent oxide thickness extraction from accumulation capacitance measurements is proposed, which is suitable for fully depleted channels with a body contact such as bulk fin field-effect transistor (FinFET) devices. First, the limitation of the previous approaches reported in the literature is discussed. A new implicit relationship between the semiconductor charge and the surface potential taking into account the increase in the sub-band energies above the conduction/valence band edge is proposed and utilized as a basis for the new extraction method. The efficiency of this method is tested through experimental measurements on a FinFET capacitance and TCAD simulations. [ABSTRACT FROM AUTHOR]

In this paper, we propose and simulate a new structure of a line tunnel FET employing gate over source--channel overlap pockets (GO-SCOPs). The SCOPs create vertical tunneling path within the source and the channel extension that lead to a faster thinning of the lateral tunneling barrier between the source and channel regions. As a result, an inverted C-shaped tunnel junction is formed providing both lateral tunneling and vertical tunneling. A calibrated 2-D simulation study shows that an ON-current improvement by one order is achieved in comparison with the gate over source only (GoSo) tunnel field-effect transistors with pockets. Further, the OFF-state leakage and average subthreshold swing are reduced by 44% and 21%, respectively, with an improved parasitic capacitance. This has improved the cutoff frequency from 8.3 MHz in GoSo with pockets structure to 1.19 GHz in the proposed GO-SCOP structure. Furthermore, by employing Ge SCOPs, the ON current is boosted by 4 orders of magnitude, maintaining leakage at ~0.25 fA/µm, giving ION/ IOFF > 109, and a much improved average subthreshold swing of ~48 mV/dec at VGS = 2 V, VDS = 0.5 V. [ABSTRACT FROM AUTHOR]

To optimize the lifetime of switching power semiconductors, this paper presents a methodology to control power device junction temperature T_j and its change during power cycles \Delta T_j at thermal boundaries. This paper proposes a supervisory state machine to interrupt nominal system-level control only when temperature bounds are exceeded, and coordinates smooth transitions as T_j(k) and \Delta T_j(k) approach their respective boundaries. To ensure that thermal states are regulated via precise and independent modulation of conduction and switching loss elements, decoupling methods are proposed. Also proposed is a \Delta T_j control law that closes a control loop on the rate of change state \bar\dotT_j , and introduces active thermal capacitance and conductance into the closed-loop thermal system dynamics. Experimental evaluation of the proposed system illustrates well damped T_j(k) and \Delta T_j(k) responses, and gradual adjustment of the manipulated inputs switching frequency and duty ratio. Finally, comparison with a current limit-based T_j regulation method illustrates how the proposed system allows power converters to push harder against their thermal limits. [ABSTRACT FROM AUTHOR]

Electric vehicles (EVs) have received considerable attention in dealing with severe environmental and energy crises. The capacity planning of public charging stations has been a major factor in facilitating the wide market penetration of EVs. In this paper, we present an optimization model for charging station capacity planning to maximize the fuzzy quality of service (FQoS) considering queuing behavior, blocking reliability, and multiple charging options classified by battery technical specifications. The uncertainty of the EV arrival and service time are taken into account and described as fuzzy numbers characterized by triangular membership functions. Meanwhile, an $\alpha$ -cuts-based algorithm is proposed to defuzzify the FQoS. Finally, the numerical results illustrate that a more robust plan can be obtained by accounting for FQoS. The contribution of the proposed model allows decision-makers and operators to plan the capacity of charging stations with fuzzy EV arrival rate and service rate and provide a better service for customers with different charging options. [ABSTRACT FROM AUTHOR]

In this paper, we consider a scenario where a source node wishes to broadcast two confidential messages for two respective receivers via a Gaussian multiple-input multiple-output (MIMO) broadcast channel. An eavesdropper also receives the transmitted signal via another MIMO channel. We first consider the discrete memoryless channel and obtain the capacity region of the degraded channel. The secret dirty paper coding (SDPC) region as an achievable rate region for the general discrete channel is introduced. Relying on the results for the discrete channel, we fully characterize the secrecy capacity region of MIMO broadcast channel. It is shown that the SDPC scheme is optimal. The converse part of the proof relies on the generalized Costa's entropy power inequality and a new channel enhancement strategy in which we only need to enhance the channels of the legitimate receivers, and the channel of the eavesdropper remains unchanged. [ABSTRACT FROM PUBLISHER]