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Due to the increasing size of integrated circuits (ICs), their design and optimization phases (i.e., computer-aided design, CAD) grow increasingly complex. At design time, a large design space needs to be explored to find an implementation that fulfills all specifications and then optimizes metrics like energy, area, delay, reliability, etc. At run time, a large configuration space needs to be searched to find the best set of parameters (e.g., voltage/frequency) to further optimize the system. Both spaces are infeasible for exhaustive search typically leading to heuristic optimization algorithms that find some tradeoff between design quality and computational overhead. Machine learning (ML) can build powerful models that have successfully been employed in related domains. In this survey, we categorize how ML may be used and is used for design-time and run-time optimization and exploration strategies of ICs. A metastudy of published techniques unveils areas in CAD that are well explored and underexplored with ML, as well as trends in the employed ML algorithms. We present a comprehensive categorization and summary of the state of the art on ML for CAD. Finally, we summarize the remaining challenges and promising open research directions. [ABSTRACT FROM AUTHOR]

A rule-based expert system for the integrated control and supervision of the dry-end sections of a paper machine is proposed. This. system is capable of recognizing all the normal and abnormal changes in process operating conditions, including acceleration of sections, threading of paper sheet, nip pressure activation, activation and deactivation of tension control loops, change of parent roll, and sheet break. A core part of the system is the supervision of the sensorless tension control of the dry-end sections, assuring its long-term stability. [ABSTRACT FROM AUTHOR]

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation. [ABSTRACT FROM AUTHOR]

This paper deals with a low-cost method for the assembly of flexible substrate antennas and UHF RF identification silicon (Si) chips. Such a method exploits a magnetic coupling mechanism, thus not requiring for galvanic contacts between the Si chip and antenna itself. The magnetic coupling is established by a planar transformer, the primary and secondary windings of which are implemented on flexible substrate and Si chip, respectively. As a result, the Si chip can be assembled on the antenna with a mere placing and gluing process. First, the idea has been validated by theory. Electromagnetic simulations of a square heterogeneous transformer (1.0-mm side) show a maximum available power gain (MAG) of -0.4 dB at 868 MHz. In addition, the heterogeneous transformer is also quite tolerant with respect to misalignment between primary and secondary. An offset error of 150 \mu\ m reduces the MAG to -0.5 dB. A sub-optimal matching strategy, exploiting a simple on-chip capacitor, is then developed for antennas with 50-\Omega input impedances. Finally, the idea has been experimentally validated exploiting printed circuit board (PCB) prototypes. A PCB transformer (1.5-mm side) and a transformer rectifier (two-diode Dickson multiplier) have been fabricated and tested. Measurements indicates a MAG of -0.3 dB at 868 MHz for the transformer and the capability of the developed rectifier to supply a 220-\k\Omega load at 1.5 V with a -2-dBm input power. [ABSTRACT FROM AUTHOR]

The article presents the information on authors involved in the journal.

It is known that the determination of the good-dice-in-bad-neighborhoods (GDBNs) has been regarded as an effective technique to reduce the value of the defect parts per million (DPPM) by identifying and rejecting the suspicious dice even though they are good in testing. Instead of examining eight immediate neighbors in a small-sized $3\times 3$ window or exploiting simple linear regression, a large-sized window can be used to recognize the broad-sighted neighborhoods and accurately infer the suspiciousness level for any given die. In this paper, the artificial neural networks (ANN)-based method can be proposed to solve the GDBN identification. Furthermore, two enhanced techniques can be further presented to improve the inference accuracy of the original ANN-based method by considering the variation of the time-dependent wafer patterns and the wafer-to-wafer relationship between two adjacent wafers. After applying the two enhanced techniques, the business profits can be improved in the new ANN-based method. Various experiments on two datasets clearly reveal the superiority of the proposed ANN-based method over the other existing methods. In addition to the reduction of the DPPM value, the new ANN-based method can achieve the 1.5X–2X better reduction in the cost of the return merchandise authorization (RMA). On the other hand, the experimental results show that the similar result can also be obtained in the other lower-yield products. By using the new ANN-based method, the relationships on bad dice cross wafers can be captured and the highly-accurate inference results can be simultaneously maintained. [ABSTRACT FROM AUTHOR]

High quality scholarship requires technical excellence but also connects the work to the primary references in the field. In this way, the reader advances their knowledge and gains perspective. The TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING supports these goals by recognizing the best paper chosen by the Associate Editors and reviewers. The winning paper was selected from 140 papers published by TSM in 2015. The winner is “An Algorithm of Multi-Subpopulation Parameters With Hybrid Estimation of Distribution for Semiconductor Scheduling With Constrained Waiting Time” by Hung-Kai Wang, Chen-Fu Chien, and Mitsuo Gen published in the August 2015 issue of the IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING (10.1109/TSM.2015.2439054). I congratulate the authors on their selection. [ABSTRACT FROM AUTHOR]

The rising cost of production testing for a system-on-a-chip (SoC) is one of the crucial matters to chip makers, due to long test time and costly automated-test-equipment. This paper proposes a spectral leakage-driven built-in self-test (BIST) scheme to precisely predict the nonlinearity of mixed-signal circuits in the loopback mode, thereby accomplishing cost-effectiveness (compared to previous BIST-based works). A digitally synthesized single-tone sinusoidal stimulus used for conventional harmonic testing is incoherently sampled by a device under test (DUT). The DUT output signal exhibits the correlation between the DUT harmonics and the spectral leakage introduced by the incoherent sampling. The DUT output signal is then fed to another DUT through a loopback path, so that the harmonics of a pair of DUTs are correlated with the spectral leakage on the loopback response; the magnitude of the spectral leakage is considered as a weighting factor on the harmonic magnitude of those DUTs. The correlation is quantitatively modeled as characteristic equations in , and postprocessing predicts the harmonics of the two individual DUTs, by simultaneously solving the characteristic equations using on-chip DSP core available in an SoC. Simulation and hardware measurements validated that this paper can be practically used for production testing by showing less than 0.3 and 0.6 dB of the prediction errors, respectively. [ABSTRACT FROM AUTHOR]

The IEEE Transactions on Semiconductor Manufacturing congratulates Yonghwi Kwon and Youngsoo Shin whose paper Optical Proximity Correction Using Bidirectional Recurrent Neural Network With Attention Mechanism was selected as the Best paper for 2021. The paper was selected from all the papers that appeared in 2021 by a team of Associate Editors. This paper applied recurrent neural networks to optical proximity correction for lithographic processing for integrated circuits. The challenge in determining a correction value comes from correlation: correction of one segment affects the correction value of other segments due to the optical proximity effect. This paper broke new ground by showing that Recurrent Neural Networks, which has been mainly applied to time series data, can be effectively applied to spatial data. Clearly, Machine Learning is rapidly moving from R&D into full flow manufacturing where the interplay between each aspect of a single process step has exponential increased in complexity requiring new approaches. Three additional papers were recognized with an Honorable Mention: [ABSTRACT FROM AUTHOR]

This paper investigates the Gaussian state-dependent interference channel (IC) and Z-IC, in which two receivers are corrupted respectively by two different but correlated states that are noncausally known to two transmitters but are unknown to the receivers. Three interference regimes are studied, and the capacity region boundary or the sum capacity boundary is characterized either fully or partially under various channel parameters. In particular, the impact of the correlation between states on cancellation of state and interference as well as achievability of capacity is explored with numerical illustrations. For the very strong interference regime, the capacity region is achieved by the scheme where the two transmitters implement a cooperative dirty paper coding. For the strong but not very strong interference regime, the sum-rate capacity is characterized by rate splitting, layered dirty paper coding, and successive cancellation. For the weak interference regime, the sum-rate capacity is achieved via dirty paper coding individually at two receivers as well as treating interference as noise. This paper also provides the achievable region for the state-dependent IC with each state known at its corresponding transmitter. [ABSTRACT FROM AUTHOR]

A Hybrid AC/DC microgrid (MG) can integrate distributed generation sources and distributed loads on the AC and DC side of the MG by eliminating many unnecessary power conversion devices, which is more flexible and efficient. However, to achieve reliable and economic operation of a hybrid AC/DC MG is challenging due to its complex structure. In this paper, a novel distributed event-triggered hierarchical control strategy is proposed to improve the economic operation of a hybrid AC/DC MG. For the primary control, distributed local controls of AC DGs, DC DGs, and interlinking converters (ICs) are realized by adopting the droop control method. For the secondary control, the distributed economic dispatch, distributed average bus voltage discovery, and distributed proportional power-sharing algorithms are first proposed; then, control objectives of voltage and frequency restoration and economic operation of the hybrid AC/DC MG are realized based upon the developed algorithms. Furthermore, the distributed secondary control is built upon an event-triggered mechanism developed in this paper, which can reduce the communication burden. The simulation results demonstrate the effectiveness of the proposed control strategy. [ABSTRACT FROM AUTHOR]

The article presents information about the Best Paper Award by the journal "IEEE Transactions on Semiconductor Manufacturing." The paper entitled "Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction," by Michael Orshansky, Linda Milor and Chenming Hu has been recognized as the best paper published in the 2004 issue of the journal. This paper, which appeared in the February 2004 issue, has been chosen for its development of methods to measure and analyze spatial within-chip variations, to understand the impact that these variations have on circuit speed, and to compensate for these variations.

Technology computer-aided design (TCAD) is an integral part of the development process of semiconductor technologies and devices, a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resulting devices often have an intricate 3-D structure and contain various specifically designed materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (material properties, interfaces, defects, and so on), to nanometric (quantum confinement, non-bulk properties, tunneling, ballistic transport, and so on), to full-chip dimensions (strain, heat transport, and so on), and time scales from femtoseconds (scattering, ferroelectric switching time, and so on) to seconds (trapping times, degradation, and so on). Voltages, currents, and charges have been scaled to such low levels that statistical effects and process variations have a strong impact. Devices based on new materials (e.g., 2-D crystals) and physical principles (ferroelectrics, magnetic materials, qubits, and so on) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools, and are often too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead, a TCAD tool chain is required which can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles, and the ensuing large-scale simulations and that make use of artificial intelligence for well-chosen (sub)routines to decrease the overall simulation time. This Special Issue features six invited and 18 regular papers that address these problems. [ABSTRACT FROM AUTHOR]

This paper presents an empirically grounded model, which links organizational learning to pattern-specific fixed costs in integrated device manufacturing. The approach described in this paper helps fab managers make fundamental strategic decisions concerning product design and product mix by engaging in scenario planning. Four critical aspects of managing pattern-specific fixed cost are analyzed in detail—sensitivity to time, design cost, and production volume; platform designs; process postponement solutions; and design penalties. The model suggests that designers and fabrication facilities must collaborate extensively on the design and realizations of product platforms for state-of-the-art integrated circuit products to remain economically viable. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM PUBLISHER]

This paper provides an electrical equivalent circuit of a high-resistance grounded (HRG) power supply transformer to discuss damage at a fault location so long as the fault remains a line–ground fault. Fault resistance and fault current that have an effect on damage are included in the equivalent circuit. Three-line diagrams showing fault current flows along with their vector diagrams are also included. Part II of this paper provides a similar equivalent circuit for an HRG grounded generator. This paper provides guidance to update the current edition of IEEE STD. 142 with respect to HRG systems. [ABSTRACT FROM AUTHOR]

Vertical interconnects used in monolithic 3-D integrated circuits (3-D ICs), so-called monolithic interlayer vias (MIVs), are as small as local vias. Thus, redesigning an existing 2-D IC layout in a monolithic 3-D IC generally results in shorter wire length than the 2-D IC layout. In addition, MIVs have almost negligible resistance and capacitance, so their impact on signal delay is very small. Thus, redesigning a 2-D IC layout in a monolithic 3-D IC is expected to improve its performance significantly. Some researchers designed several monolithic 3-D IC layouts and showed their timing benefits in the literature. In this paper, we present analytical models for performance (timing) benefits of multitier gate-level monolithic 3-D ICs. The analytical models we develop in this paper can be used to quickly estimate the performance benefits multitier gate-level monolithic 3-D integration provides without physically redesigning 2-D IC layouts in 3-D. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

The memristor-based memory cell design is getting renewed attention in recent years due to its high speed and low power consumption. This paper aims at designing a novel hybrid memory cell incorporating a minimum number of transistors for a rapid bidirectional write operation. The read stability is one of the key elements for high efficiency and superior performance in memory. The memory cell in this paper was designed undertaking adequate measures for maintaining the stability in successive reads without any refresh operation. Extensive simulation experiments were conducted using 32-nm predictive technology model transistors and the results demonstrate superb performance and sound stability of the proposed memory cell in terms of read/write time as well as switching power consumptions. [ABSTRACT FROM PUBLISHER]

This paper addresses the estimation and compensation of I/Q imbalance, one of the most prominent impairments found in wideband zero-intermediate frequency transceivers (TRxs). The I/Q imbalance encountered in this kind of TRx comprises not only frequency-selective gain and phase imbalance but also delay imbalance. Unless appropriate compensation is applied, the I/Q imbalance significantly degrades the performance of a communication system. This paper presents a novel compensation technique for transmitter I/Q imbalance based on built-in-self-calibration, a low cost and robust compensation technique that enables manufacturing as well as in-field calibration with low computational complexity. The method’s performance is evaluated in a TRx with 64-quadratic-amplitude modulation and 2 GHz of bandwidth implemented with real hardware. The measurements show that the proposed technique achieves an image rejection ratio greater than 35 dB in the entire 2 GHz bandwidth and an error vector magnitude lower than 3%. [ABSTRACT FROM PUBLISHER]

Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum transistor count. This paper presents two novel methods aiming the minimization of the number of devices in logic networks. The first contribution is a method for defactoring Boolean expressions able to apply the conventional factorization algorithms together with IG FinFET particularities, so improving it. The second contribution is a novel graph-based method that improves even more transistor arrangements by exploiting enhanced nonseries-parallel associations. Experimental results shown a significant reduction in the size of transistor networks delivered by the proposed methods. [ABSTRACT FROM AUTHOR]

In this paper, a novel filtering antenna based on periodic spoof surface plasmon polaritons (SSPPs) is proposed. Double-sided parallel-strip line (DSPSL) is used to realize the wideband property for the double-layer SSPPs. Filtering performance can be realized by adding via holes and ring resonators in the double-layer SSPPs. The simulated and measured results indicate the high gain of 9.38 dBi and bandwidth of 10.44% can be achieved for the antenna with via holes and ring resonators, the out-of-band rejection is over 17 dBi. Meanwhile, the gain variations are less than 1 dBi in the whole frequency band. Good agreements can be observed between the measured and simulated results, which indicate good potential applications in the communication systems and integrated circuits. [ABSTRACT FROM AUTHOR]

This paper presents two main contributions toward efficient very large scale integration circuits mapped with simple cells: 1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and 2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. An effective pattern-based algorithm to identify XORs/XNORs on and-inverter graphs is also presented. We show that efficient implementations in terms of inverter count, transistor count, area, power, and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while: 1) optimizing the number of added inverters and 2) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation, and delay up to 48%, 4%, 8%, 14%, and 16%, respectively. [ABSTRACT FROM AUTHOR]

This paper demonstrates a novel nanofabrication technology for producing high-density gated molybdenum (Mo) field-emitter array (FEA) based on modified nanosphere lithography (NSL). The arc-shaped side wall of gate apertures introduced by the conventional NSL process put obstacles in the formation of sharp cone-type emitters. In this paper, a two-method solution was employed to facilitate the realization of gate apertures with sharper cutting side wall which are beneficial for the formation of sharper gated Mo emitters. One method was softening nanosphere to enlarge the contact area between nanosphere and substrate. The other was optimizing gate film deposition conditions to dramatically reduce the diffraction effects. Due to the improvements in the geometrical shape of gated Mo emitters, a low-voltage working high-density gated Mo FEA was demonstrated in this paper. This is the first observation of remarkable electron emission from high-density gated Mo FEA fabricated using such as low-cost, high-throughput, and high-efficiency technique which is expected to substantially overcome the challenges in the traditional fabrication process and promotes the low-cost and large-area application of high-density gated field-emitter devices. In addition, the novel nanofabricating method is expected to offer a simple and scalable route which allows fabrication of many gated field-emission devices. [ABSTRACT FROM AUTHOR]

Nowadays, an increasing concern about people and environmental health and safety is spreading all over the world, and technologies such as efficient monitoring systems are furthered. In the field of air quality, filtering systems, especially based on activated carbons (ACs), are commonly used. In most cases, their state of health is not monitored, and their time of life is based on statistical and a priori evaluations. This paper proposes a novel microsensor platform for the real-time monitoring of AC filters based on the impedance measurements during gas exposition. A metrological characterization of the novel proposed instrument is provided in this paper, by comparing its output to a reference $RLC$ meter. A calibration and adjustment procedure is developed in order to analyze the device measurement capabilities and obtain correction coefficients. Experiments with different gas typologies are presented, and the analysis of filters impedance dynamics is provided. [ABSTRACT FROM AUTHOR]

The vertical interlayer communication channel plays a critical role in defining the performance of a 3-D network-on-chip (NoC). In this paper, an arbitration-free design for the shared vertical channels is proposed. The proposed vertical arbitration-free 3-D NoC is compared with other 3-D NoC architectures using traditional synthetic traffic patterns and Rentian traffic emulating applications for chip multiprocessors. The results of the analysis show comparable performance in throughput, energy, and latency compared to a symmetric 3-D NoC with savings up to $\approx { 20\%}$ in area. The proposed NoC is superior in performance to a 3-D NoC utilizing vertical arbitration with a similar area footprint. [ABSTRACT FROM AUTHOR]

For a function $f$ from $\mathbb {F}_{2}^{n}$ to $\mathbb {F}_{2}^{n}$ , the planarity of $f$ is usually measured by its differential uniformity and differential spectrum. In this paper, we propose the concept of vanishing flats, which supplies a combinatorial viewpoint on the planarity. First, the number of vanishing flats of $f$ can be regarded as a measure of the distance between $f$ and the set of almost perfect nonlinear functions. In some cases, the number of vanishing flats serves as an “intermediate” concept between differential uniformity and differential spectrum, which contains more information than differential uniformity, however less than the differential spectrum. Secondly, the set of vanishing flats forms a combinatorial configuration called partial quadruple system, since it conveys a detailed structural information about $f$. We initiate this study by considering the number of vanishing flats and the partial quadruple systems associated with monomials and Dembowski-Ostrom polynomials. In addition, we present an application of vanishing flats to the partition of a vector space into disjoint equidimensional affine spaces. We conclude the paper with several further questions and challenges. [ABSTRACT FROM AUTHOR]

This paper addresses the issue of detecting the use of information hiding at anti-copying 2D barcodes. Prior hidden information detection schemes have their roots in either heuristic-based or Machine Learning (ML). However, prior heuristics-based schemes lack a rigorous theoretical analysis. Prior ML-based information schemes lack robustness because a printed 2D barcode is very much environmentally dependent. Thus, an information hiding detection scheme trained in one environment often does not work well in another environment. In this paper, we propose two hidden information detection schemes for existing anti-copying 2D barcodes. The first scheme directly uses the pixel distance to detect the use of an information hiding scheme in a 2D barcode, referred to as the Pixel Distance Based Detection (PDBD) scheme. The second scheme first calculates the variance of raw signal and the covariance between the recovered and raw signals, and then based on the variance results, detects the use of information hiding scheme in a 2D barcode, referred to as the Pixel Variance Based Detection (PVBD) scheme. Moreover, we design advanced Illegitimately-Copying (IC) attacks to evaluate the security of two existing anti-copying 2D barcodes. We conduct extensive performance comparisons among the proposed schemes and prior schemes under different capturing devices, e.g., different scanners or camera phones. Our experimental results show that the PVBD scheme can correctly detect the existence of hidden information at both the 2LQR code and the LCAC 2D barcode. Moreover, the successful attacking probability of the proposed IC attacks achieves 0.6538 for the 2LQR code and 1 for the LCAC 2D barcode. [ABSTRACT FROM AUTHOR]

As the semiconductor manufacturing process is moving towards the 3 nm node, there is a crucial need to reduce the edge placement error (EPE) to ensure proper functioning of the integrated circuit (IC) devices. EPE is the most important metric that quantify the fidelity of fabricated patterns in multi-patterning processes, and it is the combination of overlay errors and critical dimension (CD) errors. Recent advances in machine learning have enabled many new possibilities to improve the performance and efficiency of EPE optimization techniques. In this paper, we conducted a survey of recent research work that applied machine learning/ deep learning techniques for the purposes of enhancing virtual overlay metrology, reducing overlay error, and improving mask optimization methods for EPE reduction. Thorough discussions about the objectives, datasets, input features, models, key findings, and limitations are provided. In general, the results of the review work show a great potential of machine learning techniques in aiding the improvement of EPE in the field of semiconductor manufacturing. [ABSTRACT FROM AUTHOR]

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this paper, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First, we show that multisegment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: 1) reservoir-enhanced acceleration; 2) sink-enhanced acceleration; and 3) a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this paper since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. The simulation results show that using the proposed method, we can reduce the EM lifetime of a chip from ten years down to a few hours (about ${10^{5}} \times $ acceleration) under the 150 °C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs. [ABSTRACT FROM AUTHOR]

Reliably and power efficiently securing integrated systems against advanced power analysis attacks (PAAs) is a significant design challenge in modern integrated circuits. Power masking and hiding are typical countermeasures for increasing system resilience for power attacks at the expense of the overall system performance and power efficiency. These method are, however, not able to alert the user or trigger additional protective actions in case of the attack. In this paper, a method for detecting power attacks in real-time is proposed. The proposed approach exploits statistical methods to analyze the on-chip voltage variations across an on-chip power grid and detect the attacker probe connected to the system. The problem of the full security coverage of the power grid is formulated and solved in this paper. Adjusting the density of the on-chip sensors and exploiting sparse analysis techniques is considered to simultaneously enhance the accuracy and power efficiency of the proposed solution. The proposed attack detection system is designed, simulated, and evaluated in Simulink based on IBM microprocessor benchmark data. Machine learning (ML) models are trained in Python and with scikit-learn ML library. The proposed system has been demonstrated to efficiently detect PAA within a period of time that is orders of magnitude shorter than a typical attack duration length. The system is expected to exhibit high detection accuracy and power efficiency across a wide spectrum of integrated systems. [ABSTRACT FROM AUTHOR]

Hardware non-idealities are among the main performance restrictions for upcoming wireless communication systems. Asymmetric hardware distortions (HWD) happen when the impairments of the I/Q branches are correlated or imbalanced, which in turn generate improper additive interference at the receiver side. When the interference is improper, as well as in other interference-limited scenarios, improper Gaussian signaling (IGS) has been shown to provide rate and/or power efficiency benefits. In this paper, we investigate the rate benefits of IGS in a two-user interference channel (IC) with additive asymmetric HWD when interference is treated as noise. We propose two iterative algorithms to optimize the parameters of the improper transmit signals. We first rewrite the rate region as an pseudo-signal-to-interference-plus-noise-ratio (PSINR) region and employ majorization minimization and fractional programming to find a suboptimal solution for the achievable user rates. Then, we propose a simplified algorithm based on a separate optimization of the powers and complementary variances of the users, which exhibits lower computational complexity. We show that IGS can improve the performance of the two-user IC with additive HWD. Our proposed algorithms outperform proper Gaussian signaling and competing IGS algorithms in the literature that do not consider asymmetric HWD. [ABSTRACT FROM AUTHOR]

Versatile Video Coding (VVC) is the next generation video coding standard finalized in July 2020. VVC introduces new coding tools enhancing the coding efficiency compared to its predecessor High Efficiency Video Coding (HEVC). These new tools have a significant impact on the VVC software decoder complexity estimated to 2 times HEVC decoder complexity. In particular, the transform module includes in VVC separable and non-separable transforms named Multiple Transform Selection (MTS) and Low Frequency Non-Separable Transform (LFNST) tools, respectively. In this paper, we present an area-efficient hardware architecture of the inverse transform module for a VVC decoder. The proposed design uses a total of 64 regular multipliers in a pipelined architecture targeting Application-Specific Integrated Circuit (ASIC) platforms. It consists in a multi-standard architecture that supports the transform modules of recent MPEG standards including Advanced Video Coding (AVC), HEVC and VVC. The architecture leverages all primary and secondary transforms’ optimisations including butterfly decomposition, coefficients zeroing and the inherent linear relationship between the transforms. The synthesized results show that the proposed method sustains a constant throughput of 1 sample per cycle and a constant latency for all block sizes. The proposed hardware inverse transform module operates at 600 MHz frequency enabling to decode in real-time 4K video at 30 frames per second in 4:2:2 chroma sub-sampling format. The proposed module has been integrated in an ASIC UHD decoder targeting energy-aware decoding of VVC videos on consumer devices. [ABSTRACT FROM AUTHOR]

Cloud radio access networks (C-RAN) enable a network platform for beyond the fifth generation of communication networks (B5G), which incorporates the advances in cloud computing technologies to modern radio access networks. Recently, rate splitting multiple access (RSMA), relying on multi-antenna rate splitting (RS) at the transmitter and successive interference cancellation (SIC) at the receivers, has been shown to manage the interference in multi-antenna communication networks efficiently. This paper considers applying RSMA in C-RAN. We address the practical challenge of a transmitter that only knows the statistical channel state information (CSI) of the users. To this end, the paper investigates the problem of stochastic coordinated beamforming (SCB) optimization to maximize the ergodic sum-rate (ESR) in the network. Furthermore, we propose a scalable and robust RS scheme where the number of the common streams to be decoded at each user scales linearly with the number of users, and the common stream selection only depends on the statistical CSI. The setup leads to a challenging stochastic and non-convex optimization problem. A sample average approximation (SAA) and weighted minimum mean square error (WMMSE) based algorithm is adopted to tackle the intractable stochastic non-convex optimization and guarantee convergence to a stationary point asymptotically. The numerical simulations demonstrate the efficiency of the proposed RS strategy and show a gain up to 27% in the achievable ESR compared with state-of-the-art schemes, namely treating interference as noise (TIN) and non-orthogonal multiple access (NOMA) schemes. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive study of multisection, velocity-tapered slow wave structures (SWSs) for highly efficient backward-wave oscillators (BWOs). The SWS velocity variation profiles are characterized by mathematical functions. Using particle-in-cell (PIC) simulations, the efficiencies of these SWSs are obtained along with their oscillation frequency response to variations in beam voltage. This paper is aimed at determining the optimum SWS profiles for high-efficiency BWO operation along with the corresponding tunability. The profile with the highest possible efficiency is fabricated and cold tested to experimentally determine and validate the underlying efficiency enhancement mechanisms. This resulting cold test experiment demonstrates higher order dispersion in the form of multiple secondary inflection points. PIC simulations using this SWS design predict an output power of 8.25 MW at 2.62 GHz corresponding to a peak power conversion efficiency of 70%. [ABSTRACT FROM AUTHOR]