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In order to achieve the purpose of extending the speed range and reducing power electronics devices for the permanent-magnet linear motor drive system, a half-centralized open-end winding (OEW) topology is studied for rail transit applications in this paper. In this topology, compared with the traditional OEW topology, the number of voltage-source-inverters (VSIs) can be reduced from four to three to drive two OEW movers and all these VSIs share a common dc bus voltage. In order to improve the steady-state performances, a four-vector phase model predictive voltage control (FV-PMPVC) is proposed in this paper. Due to the spatial distribution of phase voltage vector (PVV), an orthometric synthesis principle (OSP) is proposed to calculated the duration time for the vector synthesis, which reduces the computation burden and enhances the robustness. Comparing the existing control method, FV-PMPVC can get similar dynamic performances but better steady-state performances. Additionally, the half-centralized topology using FV-PMPVC can have same speed range while less VSIs are required. The effectiveness of FV-PMPVC is verified by experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a novel dual input nine-level inverter (DINLI) topology which requires only seven controllable devices. The dual inputs are un-identical DC voltage sources in the ratio 1:3. A simple control scheme is derived by appropriately modifying the phase disposition pulse width modulation technique to generate high-quality 9-level output from the DINLI topology. At any given instant, a maximum of four switches conduct out of which only a maximum of two switches operate at high frequency, bringing down the switching and conduction losses significantly and improving the overall system efficiency. The bidirectional DINLI (BDINLI) topology with reactive power capability can be realized by replacing the unidirectional devices with the controlled switches (i.e., total nine switches). In addition, the proposed DINLI topology does not require extra voltage balancing circuits which further improves the efficiency. The DINLI operation is verified through MATLAB simulations for grid-connected applications and its extension to an n-level, 3-phase application is also investigated. Experiments performed on a 1KVA laboratory prototype to validate the theoretical claims. [ABSTRACT FROM AUTHOR]

Compared with the conventional two-level dual-active-bridge (DAB) dc–dc converter, the three-level DAB converter could operate with lower voltage rated switching devices and provide more control degrees of freedom, which enhances the control flexibility. This paper proposes a modulation strategy with five control degrees of freedom. In the previous work with multiple control degrees, the optimization strategies for efficiency or inductor current minimization are investigated; however, these strategies all need detailed mode analysis and complex mathematical optimization tools to obtain the optimal duty cycles. In this paper, an optimization strategy for the root-mean-square value of the inductor current is proposed. This method extracts the fundamental and third-harmonic components from the high-frequency voltages on both sides and adjusts the amplitude of the bridge voltages by the vector diagram to obtain the optimal duty cycles. The inductor current can be reduced significantly at light loads with the proposed strategy, so the efficiency of the converter can be improved. Moreover, the optimization process does not need the detailed operation analysis of the converter, nor does it require the complex mathematical optimization tools. Finally, the performance of the three-level DAB and the optimization strategy are verified by the experimental results. [ABSTRACT FROM AUTHOR]

The emergence of applications which require high-voltage switches has created a tendency to use semiconductor device series stacks. These series stacks permit operation at blocking voltages above semiconductor elements’ nominal voltage. Insulated-gate bipolar transistors (IGBT) are currently utilized for controllability and switching speed, when these topologies are employed. The main challenge therewith is guaranteeing voltage balance between IGBTs, both when blocked and when switching transistors. Most of the methods which have been proposed to mitigate static and dynamic voltage unbalances increase transistor losses. The series stack loss-less high voltage switch (LHVS) which mitigates voltage unbalances, thus reducing switching losses, is presented in this paper. LHVS consists of a circuit, which ensures soft IGBT switching, an energy recovery circuit, and a gate delay compensation circuit. Additionally, the insulation voltage level is guaranteed to be equal between control circuit and high-voltage side of each IGBT. The operating principle of the LHVS is detailed in this paper, as is experimental validation which has been performed for three series stack modules. Static unbalances are reduced to 1%, while the differences between collector–emitter voltage curves in switching “on” do not surpass 8 ns, and switching losses are reduced by 41%, as compared to the hard-switching topology. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) are playing a pivotal role in the power sector with potential applications, such as interfacing renewable energy sources with the grid and several industrial drive applications. MLIs with a smaller number of switching devices are more promising due to their compact size, reduced cost, and higher efficiency compared with their traditional counterparts. This paper, therefore, presents a new three-phase seven-level inverter. This topology is a combination of two cascade-connected two-level voltage-source inverters (VSIs) and H-bridge cells with flying capacitors (FCs). This paper presents the operating principle and the balancing technique for the dc-link capacitors and FCs. The generation of various output voltage levels and the limitation of the sinusoidal pulsewidth modulation control for FC voltage balancing is also presented. The number of components in the proposed circuit configuration and their voltage ratings are considerably lower compared with the recently proposed topologies. The behavior of the proposed circuit configuration is first assessed with simulation studies and is then tested with a laboratory prototype. The simulation and experimental results validate the effectiveness of the proposed topology and the voltage balancing technique. [ABSTRACT FROM AUTHOR]

This paper presents a novel seven-level inverter topology for medium-voltage high-power applications. It consists of eight active switches and two inner flying capacitor (FC) units forming a similar structure as in a conventional active neutral-point-clamped (ANPC) inverter. This unique arrangement reduces the number of active and passive components. A simple modulation technique reduces cost and complexity in the control system design without compromising reactive power capability. In addition, compared to major conventional seven-level inverter topologies, such as the neutral point clamped, FC, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. This recued dc-link voltage makes the new topology appealing for various industrial applications. Experimental results from a 2.2-kVA prototype are presented to support the theoretical analysis presented in this paper. The prototype demonstrates a conversion efficiency of around 97.2% ± 1% for a wide load range. [ABSTRACT FROM AUTHOR]

This paper presents bidirectional grid-connected modular multilevel converters (MMC) with direct digital control and division-summation processes to achieve power-injection and rectification functions. A direct digital control is developed to track current references, regulate dc-bus voltage and cell voltage, and balance the upper and lower dc-bus voltages. It can accommodate wide filter-inductance variation and take care of source voltage harmonics to achieve tight current tracking and low distortion output current. Based on the power-balance principle, the commands of arm currents can be determined directly. In this paper, the MMC configuration is introduced first, and then the control laws for current tracking and voltage regulation are derived in detail. Experimental and simulated results obtained from two 50 kW MMCs operated in power-injection and rectification modes have verified the analysis and discussion. [ABSTRACT FROM AUTHOR]

This paper describes a dc-link voltage control method of a single-phase back-to-back cascaded H-bridge inverter (SBCI) for a medium-voltage motor drive system. The main advantage of the SBCI topology over the conventional regenerative cascaded H-bridge topology with a three-phase active front-end (AFE) is a simple system structure, which is composed of an input transformer, a power cell, a current sensor, etc. However, the challenging points of the SBCI are larger voltage ripple in the dc-link capacitor and imbalance of dc-link voltages of each phase. The asymmetric dc-link voltage of each power cells could cause unstable operation such as over-modulation due to the lack of the dc-link voltage of a particular phase and result in over-voltage or under-voltage faults. In this paper, the control strategy of the dc-link voltage for the SBCI that uses the negative-sequence voltage of the converter is described. The proposed control method is verified with a computer simulation whose target is a 6.6-kV–1.25-MW medium-voltage drive system. Also, through the experimental setup with the prototype SBCI whose power rating is 16.2 kVA, the dc-link voltage of each AFE has been controlled within a 0.5% error of its reference value at the full load. [ABSTRACT FROM AUTHOR]

This paper presents an isolated single-stage on-board electric vehicle charger without an intermediate DC-link. Based on an isolated current-source topology, the converter features soft-switching in semiconductors regardless of load variation for the full AC line voltage range. Moreover, it requires no external snubber or clamp circuits. The power factor correction and voltage regulation are provided by a relatively simple phase shift modulation, while the amount of circulating energy is kept at minimum. The charger is distinguished by its efficiency characteristic – the maximum is achieved in the constant power charging mode. The control method, component stresses, and design constraints of the topology are analyzed. The concept is verified using a 3 kW experimental SiC-based prototype, which reaches a peak efficiency of 96.4%. Moreover, the charger has demonstrated efficiencies above 95% with the THD of 4.1% when operating in constant power mode at the maximal power. [ABSTRACT FROM AUTHOR]

This paper presents a new single-source three-phase seven-level inverter with an inherent three-time voltage boosting capability for medium-voltage applications. The proposed topology is comprised of series connection of two switched-capacitor (SC) networks with an added half-bridge module per phase. Each of such integrated SC networks requires a single capacitor associated with three active power switches. The three-time voltage boosting feature of the proposed topology can reduce the dc-link voltage requirements by 50% in comparison to the traditional neutral point clamped (NPC), flying capacitors, active NPC (ANPC), hybrid clamped ANPC, and cascaded H-bridge topologies, and 75% to advanced ANPC topologies. It can also reduce the number of required switches and capacitors as well as their voltage stresses compared to those state-of-the-art topologies reported in the literature. By integrating “n” number of added SC networks in the proposed seven-level basic topology, the number of output voltage levels can be extended to 2n+3 per phase. A finite control set model predictive control algorithm is also derived to control the converter in both the active and reactive power exchanges modes without distorting the generated grid current quality. The capacitor voltage balancing is inherent in the proposed topology, and thus, there is no need for any additional voltage balancing circuit, which further reduces the control complexity. The performance of the proposed topology and its control algorithm are validated by several measurement results. [ABSTRACT FROM AUTHOR]

In this paper, we propose a topology-cognizant optimal power flow (OPF) paradigm with additional safety constraints for multi-terminal direct current (MTDC) grids. The resulting formulation is concerned with the optimization of controller set-points, i.e., voltage and power levels at each bus, and the switching status of transmission lines that collectively referred to as grid topology. A pair of additional safety constraints are integrated into the problem formulation to prevent voltage violations caused by power fluctuations in between two controller set-point updates. Searching for a grid topology that offers more efficient operation leads to a mixed-integer nonlinear program (MINLP) which is computationally challenging due to: i) Non-convex power flow equations, (ii) Non-convex converter loss equations, and iii) Binary variables accounting for the operational status of transmission lines. Non-convexities of power flows and converter loss equations are tackled by means of a mixed-integer second-order cone programming (MISOCP) relaxation, while the optimal switching status of transmission lines are determined via a branch-and-bound search. Numerical results for the modified IEEE 14, 30, and 57-bus systems are used to verify the merits of the proposed method. Furthermore, this method is experimentally validated using the CIGRE B4 DC grid benchmark in a real-time hardware-in-the-loop platform. [ABSTRACT FROM AUTHOR]

Conventionally, the converter of switched reluctance motor (SRM) is fed by the uncontrollable diode bridge rectifier (DBR), which leads to a low grid-side power factor (PF) and high current total harmonic distortion (THD). In this paper, an alternative solution for the grid-connected high-speed SRM drive system with improved PF is proposed. In the proposed drive system, the three-level active front end (AFE) is connected in cascade with the midpoint converter for SRM operation. A centralized strategy, which controls the AFE and SRM together, is proposed to govern the motor speed and grid-side PF by regulating the real power and reactive power of the system, respectively. Specifically, the real power, reactive power, and the voltage balancing of split capacitors are controlled by the model predictive directed power control (MP-DPC) algorithm, which significantly reduces the control complexity and guarantees the fast dynamic response. Consequently, satisfying speed regulation, high PF, low current THD, and bi-directional power-transfer capability are achieved. An idea-proofed testbench is constructed in laboratory, and the applicability of the proposed drive system is verified by a series of experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a capacitor voltage regulation method for the dual converter with a floating bridge for aerospace applications. This topology has previously been reported, but with a constrained voltage utilization factor due to the need for capacitor voltage regulations. In this paper, the effect of switching states on the voltage variation of capacitor is quantitatively modeled and an enhanced space vector modulation scheme with current feedback is proposed to achieve an active control of the floating capacitor voltages. This proposed method also allows further exploitation and utilization of converter voltage. The relationship between the allowed modulation index of dual converter and load power factor is obtained and expressed using a fitted polynomial equation. The advantages of the proposed method include boosted voltage utilization and superior performance in term of capacitor voltage balance. These advantages have been proven through simulation and experimental results on RL loads as well as with an open-end winding induction motor. The proposed modulation scheme can boost the converter voltage utilization by at least 10% while achieving full four-level operation. More importantly, the higher available voltage allows extending the constant torque region of the motor, the further beginning of field weakening operation could be postponed. [ABSTRACT FROM AUTHOR]

A trinary multilevel converter uses a few heterogeneous H-bridge submodules (SMs) to synthesize an output voltage with multiple levels. Two major limitations of this converter are that it needs multiple dc sources and it cannot operate under pulsewidth modulation (PWM). This paper addresses these limitations by adding a low-voltage H-bridge SM to this converter and proposing a new switching algorithm. The resulting PWM-based asymmetric cascaded H-bridge converter uses only one dc source and synthesizes a high-quality output voltage. This improved converter can be a potential choice for real and reactive power support in power system applications. This paper also proposes methods for stability analysis and design of this converter. Experimental case studies evaluate the performance of the proposed converter for both standalone and grid-connected modes of operation. [ABSTRACT FROM AUTHOR]

This paper presents research results of voltage gain number control methods of a power electronic resonant zero-current switching dc–dc switched-capacitor (SC) voltage multiplier (SCVM) in a topology with fault tolerance capability (FSCVM). The converters operated under the basic switching patterns are constant-voltage-gain dc–dc series-parallel resonant SC converters. However, this paper presents a method for the output voltage regulation by a special switching strategy. A variable voltage gain is made possible by selecting the number of active switching cells, using an appropriate control method. This creates a set of voltage ratio ranges. In addition, the proposed topology and method of control enable a fault-tolerant operation of the FSCVM under various failures of the device. The paper presents an analysis of the concept, simulation results and an experimental verification in a three-cell FSCVM dc–dc resonant boost converter operating at a 200-watt charge. Issues regarding the selection of components related to the problem of inrush currents that can occur during the voltage ratio increase are also analyzed in this paper, and the design for low inrush currents is demonstrated. [ABSTRACT FROM AUTHOR]

A modular multilevel converter (MMC) is regarded as a promising topology in high-voltage direct current systems. However, the MMC consists of numerous submodules (SMs) and switching devices, which lead to a considerable switching loss, and increased cost and size of the heat sink. To mitigate these issues, this paper presents a novel modulation method composed of fundamental frequency modulation (FFM) and multicarrier-based sinusoidal pulsewidth modulation schemes. The main purpose of this modulation method is the reduction of switching loss while maintaining good harmonic performance. However, the FFM scheme leads to the unbalanced capacitor voltage of each SM in the MMC. Accordingly, this paper additionally proposes the rotation method and selective voltage balancing control for SMs to ensure effective performance of the method. Simulation and experimental results verify the effectiveness and performance of the proposed modulation scheme through switching loss and spectral analyses. [ABSTRACT FROM AUTHOR]

This paper presents two capacitor voltage balancing (CVB) strategies for modular multilevel converter (MMC) applications. Both balancing schemes are based on model predictive control and are designed to efficiently solve a constrained optimal control problem, where the predicted capacitor voltage errors are included in the cost function with the demanded output voltage of a cluster being forced through an equality constraint. The first method proposed in this paper computes specific modulation indexes for each module using the explicit solution of a relaxed version of the original optimization problem. The second approach proposed in this paper reduces the complexity of the original problem by linearizing the objective function and using an optimal sorting network based on a greedy algorithm to solve this approximation. Considering the structures of both solution approaches, they are integrated into modulation schemes based on phase-shifted and level-shifted pulsewidth modulation algorithms, respectively. Experimental results obtained from a nine-cell single-phase MMC prototype demonstrate the good performance achieved with the proposed methodologies, as well as the implementation simplicity offered by the proposed CVB algorithms. [ABSTRACT FROM AUTHOR]

Nonregenerative pulsewidth-modulated (PWM) rectifiers are increasingly being considered for applications, where the power flow is unidirectional, such as power supplies for telecommunications, X-ray, the machine-side converter for wind energy conversion systems, etc. They use fewer active switches, which increase their power density and reduce cost. This paper proposes a novel reduced switch topology for a multilevel (five-level or higher) nonregenerative PWM rectifier. It uses only four controlled switches and eight diodes per phase for a five-level rectifier. Half of the diodes are naturally commutated (zero current switching) at the line frequency, which reduces switching losses. This topology has several other advantages compared to similar topologies reported in the literature, such as minimum voltage stress across the devices, elimination of transient voltage-balancing snubbers, no extra hardware for balancing the flying capacitors, the dc-link mid-point voltage, etc. In this paper, switching cycle average modeling and the carrier-based modulation strategy for this rectifier are also presented to maintain a balanced dc link and to regulate flying capacitor voltages, while achieving unity displacement factor at the rectifier input terminals. The overall performance of the rectifier is verified by experimental results. [ABSTRACT FROM AUTHOR]

This paper presents the digital implementation of a boundary controller with unipolar switching characteristic for single-phase voltage source full-bridge inverters. This paper expands the application of a second-order switching surface-based control method to unipolar switching of single-phase voltage source inverters (VSIs) using a finite-state machine. The finite-state machine has been formulated considering four different states of the inverter; positive,zero1, negative, andzero2. The second-order boundary control governs the current state of the system and provides proper switching action to keep the system within the desired reference. The control law is implemented digitally in F28m35x digital control card. A full-bridge inverter topology is used to achieve the three-level voltage switching. Various simulations and experiments were performed in a 550 VA, 120 V, 60 Hz VSI with a digitally implemented controller to verify the theoretical predictions. A high-quality voltage output was obtained for various loading conditions. The transient performance of the controller was investigated using a reference and load changes. A comparison of the implementation was made with the existing classical controllers to verify the fast-dynamic response of the system. [ABSTRACT FROM AUTHOR]

This paper presents a unified framework for the modeling, analysis, and design of load-independent Class E and Class EF inverters and rectifiers. These circuits are able to maintain zero-voltage switching and, hence, high efficiency for a wide load range without requiring tuning or use of a feedback loop, and to simultaneously achieve a constant amplitude ac voltage or current in inversion and a constant dc output voltage or current in rectification. As switching frequencies are gradually stepping into the megahertz (MHz) region with the use of wide-bandgap (WBG) devices such as GaN and SiC, switching loss, implementing fast control loops, and current sensing become a challenge, which load-independent operation is able to address, thus allowing exploitation of the high-frequency capability of WBG devices. The traditional Class E and EF topologies are first presented, and the conditions for load-independent operation are derived mathematically; then, a thorough analytical characterization of the circuit performance is carried out in terms of voltage and current stresses and the power-output capability. From this, design contours and tables are presented to enable the rapid implementation of these converters given particular power and load requirements. Three different design examples are used to showcase the capability of these converters in typical MHz power conversion applications using the design equations and methods presented in this paper. The design examples are chosen toward enabling efficient and high-power-density MHz converters for wireless power transfer (WPT) applications and dc/dc conversion. Specifically, a 150-W 13.56-MHz Class EF inverter for WPT, a 150-W 10-MHz miniature Class E boost converter, and a lightweight wirelessly powered drone using a 20-W 13.56-MHz Class E synchronous rectifier have been designed and are presented here. [ABSTRACT FROM AUTHOR]

This paper proposes generation of a 15-level (14 concentric) dodecagonal voltage space vector structure (DVSVS) for a star connected induction motor drive. The proposed multilevel DVSVS is obtained by cascading two inverters, namely a primary and secondary inverter. The primary inverter is a five-level (5L) structure formed by stacking two three-level flying capacitors with individual reduced dc sources and the secondary inverter is also a 5L structure formed by cascading two capacitor-fed cascaded H-bridges (CHB). The active power is supplied by the primary inverter, while the secondary inverter acts as switched capacitor harmonics filter, and capacitors in the secondary inverter are balanced naturally irrespective of load power factor for entire modulation index. The high-voltage dc supply fed primary inverter is operated in quasi-square wave mode, while the high frequency switching is applied to low voltage CHBs, thus, reducing the overall switching loss. The proposed scheme gives the advantages of both DVSVS and multilevel structure, thus, making it one of the solutions for battery or stacked dc-fed applications. The paper also presents the experimental results as well as comparison study with the existing topologies to support the advantages of proposed scheme. [ABSTRACT FROM AUTHOR]

High-performance cloud computing enables many key future technologies such as artificial intelligence (AI), self-driving vehicle, big data analysis, and the Internet of things (IoT), using clustered CPU and GPU servers in the datacenter. To improve the power efficiency and the infrastructure flexibility, the computing industry is adopting 54 VDC to power the servers in the open compute racks. In this paper, a new modeling technique for a soft-switched dc–dc converter is presented and suitable to guide optimal design in different applications, for example, 54 V to point of load (PoL) for the new open compute rack. To improve the model accuracy and reduce the complexity, this paper proposes a reduced-order linear differential equation (LDE) based modeling technique to discover the following: 1) the tank resonance involving the output inductor; 2) the output current ripple and its impact on power efficiency; 3) the proper on-time control for soft switching; 4) the unique bleeding mode under the heavy load; 5) the output power capability of the converter; and 6) component tolerance analysis and impact on the performance of the converter. With the power loss estimation, design guidelines are provided for a reference design and design improvement based on this new modeling technique. Using the proposed method, great accuracy can be expected in the efficiency estimation. Simulation and experimental results are provided to verify the modeling technique in a 54–1.2 V 25 A dc–dc converter prototype. [ABSTRACT FROM PUBLISHER]

To support the development of high-frequency ac microgrids in terms of compact design, high-voltage gain and low total harmonic distortion (THD), a buck–boost dual-leg-integrated step-up inverter is proposed in this paper. The inverter is formed by integrating a buck–boost converter into a conventional single-phase full-bridge inverter by sharing the upper switch and the body diode of the lower switch in both bridge-legs. Consequently, the component count is significantly reduced over the step-up inverter counterparts. In addition, to address the drawbacks of hybrid modulation methods adopted by existing dual-leg-integrated inverters, such as double-variable control, and high THD of output voltage/current at high input voltage and heavy load conditions, unipolar frequency doubling sinusoidal pulse width modulation scheme is adopted in this inverter. As a result, the modulation ratio M becomes the only control variable to regulate the output voltage/current and the control is simplified. The THD of the proposed inverter output can remain low throughout the entire input voltage range and load power range. This paper presents the topology derivation procedure, operation principle, and steady-state characteristics of the proposed inverter. To validate the effectiveness of theory, experimental results of a 400 W hardware prototype, where the output voltage frequency is at 500 Hz, are reported. [ABSTRACT FROM PUBLISHER]

In order to increase the efficiency of modern microprocessors power supplies used in data centers, the 48-V dc distribution bus is gaining growing attention. For such applications, voltage regulation modules (VRMs) are currently obtained using two-stage conversion systems with an intermediate 12-V dc bus. This paper presents an innovative single-stage approach for the 48-V VRM based on a quasi-resonant constant on-time (COT) operation. The proposed topology inherently integrates the multiphase approach, providing fast phase shedding and flat high-efficiency curves even at light load conditions. This is a unique advantage, usually not available in the two-stage approach, that is very important in server architectures, where high efficiency is required even at light load conditions. The paper analyses the circuit topology, and proposes a control architecture for fast transient response, including the current sharing capabilities, and a solution for implementing the integrated magnetics. The digital controller has been implemented in 0.16-$\mu$ m lithography together with a digital pulse-width-modulation with a 195 ps resolution, and a 40 MS/s, 7-bit ADC. Experimental results show an efficiency of 93.1% for a 250 A, 1.8 V VRM, and of 93.2% for a 102 A, 1.2-V double data rate (DDR) power supply. [ABSTRACT FROM PUBLISHER]

This paper analyzes the combination in a cascaded H-bridge multilevel inverter (CHBI) based on transformers with the different turn ratios for increasing the voltage level and proposes the switching method for achieving the output voltage distribution among H-bridge cells (HBCs). The transformers used in this paper are connected to the output of the respective HBCs, and the secondary sides of all the transformers are connected in series for generating the final output voltage. Only one of the transformers, in particular, has a different turn ratio for increasing the output voltage level. In this paper, the possible turn ratio of the special transformer with a different turn ratio is discussed in detail, and a switching method based on the level-shifted switching method for the topology used in this paper is proposed. To verify the effectiveness of the proposed method, a three-phase 21-level CHBI is experimentally tested. [ABSTRACT FROM PUBLISHER]

In applications that demand single-input dual-output (SIDO) or dual-input single-output (DISO) dc–dc converters, employing two separate single-input single-output (SISO) converters is a solution. However, the number of components is doubled, resulting in high overall cost. In order to reduce costs, this paper proposes a novel topology synthesis methodology, with which a variety of SIDO and DISO dc–dc converters with reduced components can be derived. The principle of topology synthesis states that integrated SIDO and DISO dc–dc converters can be easily developed from conventional SISO converters by replacing a diode with a basic cell inclusive of additional input/output port. The principle is effective for many SISO dc–dc converters, and as an example, topology synthesis based on buck, boost, buck–boost, Cuk, sepic, and zeta SISO converters is performed in this paper. In order to achieve better understanding of the proposed converters, the integrated SIDO Cuk converter is specifically analyzed and experimentally verified. In comparison with the conventional scheme of two separate SISO Cuk converters, good cross regulation is retained while the number of diodes, inductors, and capacitors is reduced in the proposed SIDO Cuk converter. In addition, zero-voltage-switching operation of one switch is achieved, contributing to lower switching losses. Finally, a prototype circuit with 48-V input and 156 V/1 A, 24 V/4 A outputs is built to validate the theoretical analysis. [ABSTRACT FROM PUBLISHER]

A switched-capacitor-based dual-switch dc–dc converter with a high-boost voltage gain is proposed in this paper. The proposed converter can obtain a high-voltage gain with a small duty cycle, which decreases the voltage stress and the conduction loss on the power switches. This paper presents the key waveforms, the operating principles at the continuous conduction mode and the discontinuous conduction mode, and the parameter design. Moreover, a comparison between the proposed converter and other nonisolated converters has been completed. To verify the operating principle, a 200 W prototype is constructed with an input voltage of 25–50 V and an output voltage of 200 V. The simulation and experimental results are shown. [ABSTRACT FROM PUBLISHER]

In this paper, direct torque control (DTC) of five-phase induction motor (FPIM) is implemented using three-level neutral point clamped (TL-NPC) inverter. One of the advantages of three-level inverter over two-level one for DTC operation is the low torque ripple. Also TL-NPC inverter through space vector modulation technique gives low $ dv/dt$ transition with better voltage waveform. By applying conventional lookup table for DTC, the TL-NPC inverter does not ensures lower $dv/dt$ transition. In this paper, a novel switching scheme for DTC of FPIM using TL-NPC inverter is proposed that ensures the low $ dv/dt$ transition and balancing of dc-link capacitor voltages of TL-NPC inverter. To form the lookup table for DTC operation, instead of using voltage vectors directly, virtual vectors (VVs) are utilized. Two switching states are used in one sample time to generate a VV in $\alpha \beta$ plane, which gives zero resultant voltage in $ xy$ plane. The switching strategy ensures low number of transitions to reduce the switching losses. The switching state redundancies are used in a novel way to balance the dc-link capacitor voltages without using any additional hardware. The proposed technique to balance the dc-link capacitor voltage gives lower switching frequency. The MATLAB/Simulink environment is used for the simulation and the results are validated through experiments. [ABSTRACT FROM AUTHOR]

This paper presents three unidirectional step-up ac–dc converter topologies with voltage multiplication on their outputs. The first topology is the hybrid boost rectifier and the other two are novel bridgeless structures, all based on the integration of boost rectifier and the ladder switched-capacitor (SC) cell. The new hybrid structures provide high voltage gain with low voltage stress across the switches, high-power factor, and output voltage regulation. This paper presents the principle of operation, steady-state and dynamic analysis, design methodology, and experimental verification. A different approach is also presented for the design methodology of the SC cell and for the analysis of its influence on the dynamic model. Three 1000-W prototypes with a 220-V input voltage, 800-V output voltage, and 100-kHz switching frequency were designed to corroborate the theoretical study. The best efficiency was 97.1$\%$ in the proposed bridgeless versions and the voltage stress across the switches stands around 400 V. Furthermore, a comparison between the proposed structures and previous topologies is also presented. [ABSTRACT FROM PUBLISHER]

This paper presents a hybrid seven-level converter based on T-type converter and H-bridge cascaded suitable for low-voltage and high-power-density applications. The operation principles and conduction paths are analyzed comprehensively. Voltage balance control of the floating capacitors is the key point of this paper. Mathematical expressions of capacitor voltage balance conditions are deduced based on sinusoidal pulse width modulation (SPWM). The results show that floating capacitor voltages are only balanced when the modulation index is below 0.82 under SPWM. In order to enlarge the modulation index ensuring the capacitor voltage balance, space vector modulation (SVM) is also applied to regulate floating capacitor voltages taking advantage of redundant switching vectors. Meanwhile, in SVM, there are no additional control requirements for the capacitor voltage. Taken both SPWM and SVM into consideration, the limit to the range of operation for this seven-level converter is presented, which is a function of the modulation index and the power factor. The merit of dc voltage utilization improvement in this topology is also analyzed based on simulation results. Simulations and experimental results under different modulation index and RL load are presented to verify the modulation strategies illustrated in this paper. [ABSTRACT FROM PUBLISHER]

This paper proposes and validates model predictive control as an alternative control strategy for H-bridgeneutral-point-clamped (H-NPC) converters for single-phase grid-tied string photovoltaic (PV) systems. The presented control scheme achieves good quality current waveforms with unity power factor, dc-link voltage control, and neutral-point voltage minimization. Furthermore, the predictive controller has been further enhanced by including an average device switching frequency restriction and a $dv/dt$ mitigation. The main contribution of this paper is the avoidance of the potential leakage current due to parasitic capacitance of the PV modules by using a predictive model based control technique instead of modulated schemes and eliminating high-frequency common-mode voltage components. Experimental results during steady state and dynamic operation are presented to illustrate the behavior of the H-NPC converter commanded by the proposed control scheme. [ABSTRACT FROM AUTHOR]

An extended-duty-ratio (EDR) boost converter is studied extensively in this paper for high voltage gain applications with a wide input (and/or output) voltage range. The EDR is a unique combination of an interleaved, multiphase boost converter and switched capacitor configuration that achieves high voltage gain with significantly lower switch voltage stress and switching losses compared to conventional high-gain solutions. Most of the switches in the multiphase EDR experience only a fixed fraction of the output voltage ($1/M, 2/M$ , etc., where $M$ is the number of phases). Through extensive analysis over a wide operating range, it is shown here that the EDR boost converter has inherent current sharing among the phases only in a limited range of duty ratio— $(M-1)/M \leq D \leq 1$. As the duty ratio reduces beyond this range as required in wide input voltage applications, inherent current sharing property is lost. In this paper, techniques to ensure current sharing under all operating zones without requiring current sensors are presented. Instead of having equal duty ratio for each phase, it is adjusted for each phase according to the operating region of the converter. Extensive analysis is presented to derive the required duty ratio changes for the different phases. The proposed concept is validated with experimental results from a 250 W, 3-phase EDR boost, and GaN-based hardware prototype. [ABSTRACT FROM AUTHOR]

This paper introduces a novel five-level nested neutral point piloted (NNPP) converter and analyzes the operating principle of five-level NNPP converter. This paper presents a novel space vector pulse width modulation (SVPWM) algorithm based on gh coordinate for five-level NNPP converter. First, the common-mode voltage is reduced by choosing the appropriate redundant switching states. After that, the floating-capacitor voltage balance control strategy is presented. The appropriate switch combinations of each phase are determined by the control requirements of floating-capacitor voltages respectively and the hardware mapping method of the switching states is presented. Furthermore, the neutral-point voltage balance control strategy is presented. In order to balance the dc-link capacitor voltages, the seven-segment switching sequence is selected according to the control requirements of dc-link capacitor voltages and the neutral-point voltage regulatory factor is introduced to regulate the durations of the redundant switching states in a switching cycle. Finally, the validity of the novel SVPWM algorithm with decoupling control strategies of floating-capacitor voltages and dc-link capacitor voltages is verified by the experimental results of five-level NNPP converter under steady-state and dynamic conditions. [ABSTRACT FROM AUTHOR]

This paper analyzes three different carrier-based modulation patterns applied to a three-phase high-power-factor-corrected (PFC) five-level buck+boost-type converter acting as an interface between dc distribution systems and an ac grid. The modulation is analyzed employing the space vectors theory so that the achievable performance is demonstrated. The main advantage of the analyzed modulation strategy is its simplicity, which makes it suitable for digital signal controller (DSC) implementations. This seems straightforward for voltage source converters, but is a challenge for current-multilevel converters that typically employ field-programmable gate array devices to achieve better harmonic distortion performance. This is due to modern power electronics DSCs being typically designed for other converter topologies. The power converter is constructed with two phase-shift-modulated six-switch buck-type PFC converters, paralleled by interphase transformers, and an inverting circuit. The system features: bidirectional current carrying capability; relatively low parts count; high utilization of the semiconductors; and low current and voltage ripple at its terminals. The principle of operation, detailed description, analysis of the modulation strategy, and dimensioning equations for three different power circuit realizations are described in this paper assuming the analyzed modulation patterns. The feasibility of the presented converter is demonstrated by means of a constructed hardware prototype. [ABSTRACT FROM AUTHOR]

An efficient power converter system plays a significant role in the design of battery charging systems for electric vehicles (EVs). In this paper, a new zero-voltage and zero-current switching (ZVZCS) full-bridge dc–dc converter is proposed to reduce the power conversion losses. The proposed converter incorporates a new asymmetrical pulse width modulation (APWM) gating technique for the dc–dc conversion stage in the battery charging system. The proposed dc–dc converter topology achieves zero-voltage switching (ZVS) for all the active switches and near zero-current switching (ZCS) for low-side active switches throughout the charging range of the battery. The proposed APWM technique can reduce the switching and conduction losses compared to the conventional phase-shift modulation (PSM) gating technique. The auxiliary inductance required to ensure ZVS with APWM can also be reduced compared to PSM. Analysis, design, and implementation of the proposed APWM ZVZCS full-bridge dc-dc converter are discussed in this paper. A 100-kHz 1.2-kW laboratory prototype is developed and the experimental results are presented. The results validate the analysis and performance of the proposed converter. [ABSTRACT FROM AUTHOR]

This paper proposes an effective sliding mode controller (SMC) for a grid-connected 7-level packed U-cell (PUC7) inverter. The aim is to design a simple controller that deals effectively with the complex control problem of the PUC7 inverter (multiobjective control problem). The selection of the control actions is achieved according to the system state error at every sampling time, regardless of the previous values, which makes the control technique model-independent. The control algorithm evaluates online two cost functions (one for each state error), which are derived on the basis of sliding mode theory, and it selects the optimal control input in order to satisfy the reaching conditions of the two cost functions. Compared with the existing solutions, the proposed SMC technique ensures lower average switching frequency by tuning the hysteresis bandwidth of the capacitor-voltage error. The fast implementation, needless of gains tuning, and simple design procedure are the main features of the proposed algorithm. Simulation and experimental results are presented to prove the effectiveness of the proposed technique in controlling the PUC7 inverter with high dynamic performance and robustness against disturbances and parameters mismatch. [ABSTRACT FROM AUTHOR]

The conventional three-level inverter only has voltage buck capability. The quasi-Z-source three-level T-type inverter (QZS 3LT $^2$ I) has been proposed to realize voltage buck–boost operation. In this paper, we further propose a novel modulation scheme for the QZS 3LT $^2$ I to realize voltage boosting, reduce the common-mode voltage (CMV), and control the neutral-point voltage balance simultaneously. The proposed scheme adopts a large vector, a medium vector, a small vector with low CMV magnitude, a zero vector, and a shoot-through vector to generate the output voltage. According to sector number and neutral-point voltage difference, a p-type or n-type small vector with low CMV magnitude is properly selected to balance the neutral-point voltage. Shoot-through states are inserted within zero vector to boost the dc input voltage without affecting the ac output voltage. Dwell times of basic vectors are calculated through the revised volt–second balance equation. Furthermore, a coordinate control strategy between neutral-point voltage balance and voltage boosting is proposed. Doing so, the CMV magnitude can be restricted within one-sixth of dc-link voltage and neutral-point voltage imbalance can be effectively mitigated. The effectiveness of the proposed scheme is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

A novel nine-level inverter topology for low-voltage applications is proposed in this paper. Each phase of the inverter is composed of a T-type three‐level cell and an active neutral point clamp three‐level cell. The operation principles and current conduction paths are analyzed in detail and phase-disposition sinusoidal pulsewidth modulation is used to balance voltages of flying capacitors and neutral point. The mathematical relationship between the capacitance and the desired ripple in the inverter output is established to select the intermediate capacitance value. Compared with other nine-level inverters suitable for low-voltage applications, the proposed inverter has advantages in a number of gate drivers, a number of dc sources, and efficiency. Simulation and experimental results under different settings of modulation index, power factor, output frequency, and load are presented to verify the effectiveness and performances of the proposed inverter. [ABSTRACT FROM AUTHOR]

For photovoltaic applications, the flyback microinverter with pseudo-dc-link is popular as a simple topology but brings large transformer turns ratio and thus large leakage inductance, which would deteriorate the converter efficiency. To solve this issue, based on the nonisolated pseudo-dc-link structure, this paper proposed a hybrid boost–flyback/flyback (BF/F) microinverter. This new topology is operated at the BF mode for the most segment of a half grid cycle and the F mode for the rest. During the BF mode, high voltage gain with low voltage stress is easily available in minimized transformer turns ratio. Besides, the leakage energy is recycled and the turn-off voltage spike of the main switch is clamped, as a result of a passive snubber inherently contained in this mode. Given that the BF mode is lack of step-down function, the F mode is developed to regulate the output voltage even for values lower than the input voltage. The operation and characteristic of the hybrid BF/F microinverter in boundary conduction mode are analyzed in detail, and the mathematical expression of reference current is derived theoretically to guarantee high power quality. Finally, a 240 W prototype was implemented to validate the theoretical analysis and the benefits of the proposed topology. [ABSTRACT FROM AUTHOR]

A systematic method for developing ultra-wide output voltage range power supply based on modular switched-converter principle is proposed in this paper. The basic symmetric switched-converter (SSC) module is composed of two dc–dc modules, two diodes, and one active switch. Multi-stage SSC modules are generated by symmetric cascaded connection method. By controlling the active switches in multi-stage SSC modules, the connections of all the dc–dc modules’ output ports can be changed flexibly among series, parallel, and partial–parallel–partial-series connections. Then segmented regulation can be realized and system output voltage range can be widely extended. Meanwhile, the voltage range of each dc–dc module can be narrowed and the voltage/current stress can be reduced to simplify the design, increase device utilization ratio, and improve overall efficiency. A full-bridge isolated buck–boost converter with a semiactive rectifier, which features soft-switching and wide voltage adjustment range, is adopted as the dc–dc module to realize the proposed system. Input current sharing control strategy is adopted to ensure proper power balancing in all possible operating modes. The stability of the proposed system is also explored. Simulation and experimental results are provided to verify the effectiveness and advantages of the proposed system configuration, the switched-converter principle, and the control strategies. [ABSTRACT FROM AUTHOR]

The low-frequency fluctuation over the capacitor voltages seriously limits the development of medium-voltage variable-speed drives with a modular multilevel converter (MMC). Therefore, this paper presents an effective strategy of the low-speed and start-up operation for an MMC-based motor drive. The proposed strategy properly coordinates the improved injection and the reduced average capacitor voltage with high applicability. The specific interactions between the control parameters and the system metrics are analyzed to give the detailed steps of the parameters designing. Hence, based on the derivations, the proposed method enables the low-frequency operation under the nominal load torque with decreased injected components and reduced peak capacitor voltages. What is more, two start-up strategies that, respectively, aim at different objectives for the coordinated strategy are proposed, indicating satisfying control performances for the practical applications. The injected common-mode voltage and circulating current in the proposed method are designed to have a great reduction. Thus, the unfavorable risks for the motor are evidently decreased for better stability. The reduced peak current also lessens the high stress on switching devices with desirable reliability. The simulation and experiment results of an MMC-based motor drive prototype prove the effectiveness and superiority of the proposed method. [ABSTRACT FROM AUTHOR]

The three-level full-bridge (TLFB) dc−dc converter has been widely used in high-voltage, high-power applications. In the experimental test, the neutral-point voltage deviation appears; moreover, it has also been found out that if the flying capacitors are introduced, the input capacitor voltages could realize self-balance even if no active balancing solutions are adopted. In the previous publications, the role of flying capacitors is generally considered to extend the range of soft switching; however, the self-balance ability has not been mentioned or investigated in any publications thus far. In order to fill this gap, this paper provides the detailed mode operation analysis of the TLFB converter and reveals the cause of the imbalance. In addition, the mechanism of the self-balance ability provided by the flying capacitors is explained in detail, which gives a deep insight into the converter. At last, the influence factor of the voltage error in steady state has been analyzed, and the specific expression of the voltage error is also derived. The feasibility of the theoretical analysis is verified by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes the predictive control with the discrete space-vector modulation (DSVM) for Vienna rectifier connecting to the permanent magnet synchronous generator (PMSG) of the wind turbine system (WTS). Since Vienna rectifier has the special operation principle, Vienna rectifier generates only the feasible eight voltage vectors, which can be a candidate vector for the predictive control, depending on the sign of the input currents. In the proposed predictive control, the feasible voltage vectors are extended from 8 to 19 consisting the 8 original voltage vectors and 11 virtual voltage vectors by using the DSVM for improving the current quality related to the torque ripple, vibration, and noise, and the neutral-point voltage balance with low voltage ripple is guaranteed by using the offset value calculated based on the model of two dc-link capacitors in Vienna rectifier. The scheme for reducing calculation burden is applied in selecting the candidate vector. In addition, the limited operation range for the maximum torque per ampere control of PMSG connected to Vienna rectifier is analyzed. The performance of the proposed predictive control with DSVM for Vienna rectifier with PMSGs is verified in simulation and experiment. [ABSTRACT FROM AUTHOR]