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Oxide-based thin-film transistors (TFTs) with a lateral in-plane electrode are self-assembled on paper substrates, and the electrical modulation effect of the in-plane electrode is investigated. A \SiO2-based solid-electrolyte film with high specific capacitance is used as the gate dielectric, and the operation voltage is reduced to less than 2.0 V. The threshold voltage (Vth) of such paper TFTs is tuned from -0.98 to 0.94 V by different voltage biases on the in-plane electrode. The threshold voltage shift (\Delta Vth) can be described by \Delta Vth = -(CG2/CG1)VG2, where CG2 and CG1 are the in-plane electrode and bottom-gate specific capacitance values. High electrical performance with a current on/off ratio of \6 \times \10^5 \sim \10^6, a subthreshold swing of 0.14 \sim 0.19 V/dec, and a mobility of \8.64 \sim \9.45\ \cm^2/\V\cdot \s is obtained at different in-plane electrode voltage biases. Such low-voltage paper TFTs are promising for low-cost and portable electronics. [ABSTRACT FROM PUBLISHER]

Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability. [ABSTRACT FROM AUTHOR]

We have fabricated fully transparent high performance flexible nickel-doped zinc oxide thin-film transistors (NZO TFTs) on flexible plastic substrates using magnetron sputtering. The effects of active layer thickness on the performance of NZO TFTs was investigated. We found that the channel layer thickness has a notable influence on the characteristics of NZO TFTs. The electrical characteristics of NZO TFTs reached the optimization when the active channel layer thickness was 71 nm, with a low off-current lower than 1 pA, a high on/off drain current ratio of 2.1 \times 10^9 , a high saturation mobility of 27.5 cm ^2\cdot \mathrm V^-1\cdot \mathrm s^-1 , a steeper subthreshold swing of 67 mV/decade, and a low threshold voltage of 1.88 V. It is demonstrated that NZO is a promising active channel layer materials for future transparent flexible displays. [ABSTRACT FROM AUTHOR]

Because of charge trapping in GaN HEMTs, dc characteristics of these devices are not representative of high-frequency operation. The advanced spice model GaN model presented in Part I of this paper is combined with a Shockley–Reed–Hall-based trap model, yielding a comprehensive FET model for GaN HEMTs which can accurately model GaN devices exhibiting trapping-related dispersion effects. Measurement results of the dc and pulsed output and transfer characteristics of a commercially available GaN HEMT are presented, trapping in the device is modeled, and excellent fit to the measured data is shown. This paper presents an accurate model of trapping which is validated for eight different quiescent bias points of pulse measurements, with quiescent drain voltage ranging from 5 to 20 V and quiescent gate voltage ranging from −2.8 to −3.8 V, and a large range of gate and drain voltages to which the device was pulsed in the pulse measurements and at which the device was measured in the dc measurements, with gate voltage ranging from −4 to 0.4 V and drain voltage ranging from 0 to 40 V. This paper also presents high-frequency (10 GHz) large-signal RF validation of the model for optimal complex load condition. [ABSTRACT FROM AUTHOR]

Thin-film transistors were fabricated using 45-nm thick ZnO deposited by pulsed laser deposition and 15-nm thick Al2O3 gate insulator deposited by atomic layer deposition. A 1-D model with a constant density of interface states above and below the conduction band edge is used to explain the current-voltage characteristic. This model does not create distortion of transconductance versus gate voltage at low gate voltage that can be created by exponential tail or Gaussian distributions of interface states. The “subthreshold” regime is at the top ZnO surface away from the bottom gate, but subthreshold swing is controlled by interface states at the ZnO/Al2O3 bottom interface. The observed increase in mobility with gate voltage is delayed by filling of the interface states above the conduction band edge. Interface state filling and a rapid increase in mobility with increased gate voltage produce an apparent large threshold voltage as extrapolated from a linear fit to current measured at large gate voltage. The difference between threshold voltage and turn-off voltage is an important figure of merit (FOM) that should be kept as small as possible. In this paper, FOM is 2.5 and 1.8 V for 0.1 and 6 V drain voltage, respectively. [ABSTRACT FROM PUBLISHER]

The read channel of a Flash memory cell degrades after repetitive program and erase (P/E) operations. This degradation is often modeled as a function of the number of P/E cycles. In contrast, this paper models the degradation as a function of the cumulative effect of the charge written and erased from the cell. Based on this modeling approach, this paper dynamically allocates voltage using lower voltage write thresholds at the beginning of the device lifetime and increasing the thresholds as needed to maintain the mutual information of the read channel in the face of degradation. This paper introduces the technique in an idealized setting and then removes ideal assumptions about channel knowledge and available voltage resolution to conclude with a practical scheme with performance close to that of the idealized setting. [ABSTRACT FROM PUBLISHER]

In this paper, we present a detailed investigation of the impact of fin width (${w}_{\text {fin}}$) on tri-gate AlGaN/GaN metal–oxide–semiconductor high electron mobility transistors (MOSHEMTs). As ${w}_{\text {fin}}$ is reduced, the threshold voltage (${V}_{\text {TH}}$) increases, which is due to the enhanced gate control (especially for ${w}_{\text {fin}} < {200}$ nm) thanks to the 3-D geometry of the tri-gate, and the reduced carrier concentration (${N}_{\text {s}}$) caused by a more pronounced strain relaxation and sidewall depletion, as explored using Hall and capacitance–voltage (${C}$ – ${V}$) measurements. Normally- OFF operation was achieved for ${w}_{\text {fin}}$ close to the sidewall depletion width (${w}_{\text {dep}}$) of 19.5 nm, since the fin is depleted from its two sidewalls. The impact of ${w}_{\text {fin}}$ on ON-resistance (${R} _{{{ {6{8} {\text {ON}}}}}}$) and current capability (${I} _{\text {D},\text {max}}$) was also investigated, along with the influence of the effective source injection, the trench conduction and the filling factor (FF) on these key characteristics. The degradation caused by the tri-gate fin etching could be fully recovered by increasing the FF. Finally, we show that the tri-gate can reduce gate capacitance (${C}_{\text {G}}$) and charge (${Q}_{\text {G}}$) in normally- ON MOSHEMTs, depending on the design of the tri-gate and the gate voltage (${V}_{\text {G}}$), leading to a smaller ${R}_{{{ {6{8} {\text {ON}}}}}} \cdot {Q}_{\text {G}}$ product that is beneficial for high-frequency switching applications. The results in this paper offer insights into important phenomena in tri-gate GaN devices and are fundamental for the further advance of this technology. [ABSTRACT FROM AUTHOR]

This paper deals with the repetitively pulsed spark discharges over the water surface by studying both the electrical and the spectroscopic aspects. Detailed discharge electrical parameters, vibrational and rotational temperatures, and electron density measurements for nine different conditions of input frequencies and voltages over the water surface have been reported. The objective of this paper was to find effective operating conditions and compile results for the future industrial applications. The spectroscopic characterizations such as temperatures and densities were gathered from the optical emission spectroscopy (OES). The N2 (C–B) second positive system (SPS) transition (370–382 nm) and the O triplet line (777 nm) obtained from plasma spectrum were analyzed by SpecAir software in order to get the vibrational/rotational temperatures and electron densities, respectively. The results of this work are concurred with our previous work on softening hard water using pulsed spark discharge, finding the most effective conditions practically. [ABSTRACT FROM AUTHOR]

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells. [ABSTRACT FROM AUTHOR]

This paper presents a new approach for compact modeling of aging and radiation effects for MOS transistors including process variation and environmental influences. This approach can be used in common design flows for analog integrated circuits. Moreover, the aging behavior of whole circuits can be analyzed without the need for abstractions or extrapolation. Only one common physically motivated transistor parameter is used in order to model radiation and degradation mechanisms. [ABSTRACT FROM AUTHOR]

In this response, we show that the paper by Kim et al. by our group has a different research purpose and uses different modeling processes, which was not described in the previous work by Ortiz-Conde et al. The comments issued by Ortiz-Conde et al., who claim that our paper corresponds to a particular case of their previous work, are in our opinion overgeneralized. Differences compared to Ortiz-Conde’s previous work are discussed in detail. We also explain how the problem on threshold voltage pointed out by Ortiz-Conde et al. can be solved through a semiempirical method from measured data. [ABSTRACT FROM AUTHOR]

Point-on-wave (POW) is a single-event characteristic of voltage dips, influencing the performance of sensitive equipment, such as AC contactor and wind turbines. However, definition and calculation of POW are unsolved issues. The existing definition of POW is for single-phase dips; it does not consider three-phase dips. Moreover, existing POW calculation methods are inaccurate. This paper proposes a definition of POW as a single-event characteristic for three-phase voltage dips. Then, it proposes a POW calculation method based on space vector, including POW detection and angle calculation. The proposed method is based on the ellipse characteristics during the dip-stage and non-dip stage. The proposed method does not depend on zero crossing for angle reference. To verify the performance of the proposed method, a power-system simulation model is built to generate voltage dips with different origin. Furthermore, the accuracy of the proposed method is verified by 425 sets measured voltage dips, and compared with the published methods. [ABSTRACT FROM AUTHOR]

A novel high-voltage direct current (HVdc) power supply which has no transformer or voltage multiplier circuit is presented and analyzed in this paper. This is made possible upon the diodes storage delay phenomenon. This proposed power supply is compact, lightweight, and low cost. Its basic structure includes a diode with a proper reverse recovery specification that plays the role of a step-up transformer in the conventional HVdc supplies and a high-voltage capacitor which stabilizes the output voltage. This structure has remarkable advantages over the conventional transformer-based HVdc supplies, such as compactness, a low ripple output, and a low-cost power supply. Performance of the proposed method and its accuracy are investigated in this paper. The results are verified by implementation of a 1.2-kV prototype supply. [ABSTRACT FROM AUTHOR]

This paper presents a high-voltage emission driver chiplet for inorganic micro-pixelated light-emitting-diode ($\mu $ LED) displays in a standard 0.18- $\mu \text{m}$ CMOS technology. Different from the conventional driving scheme of the active-matrix organic light-emitting-diode display, which places the scan drivers and emission drivers at the panel bezels, the CMOS driver chiplets are proposed to sit on the glass substrate among $\mu $ LEDs. The high-voltage swing buffers in the CMOS chiplet are used to drive the low-temperature poly-silicon thin-film transistors on glass backplane to enable the emission control of 300 $\mu $ LEDs. A single CMOS chiplet has 20 output channels, each offering 16M-color depth with 256 grey levels realized by an 8-bit digital-to-analog converter. The maximum channel current is 247 $\mu \text{A}$ and the TFT-gate-driving voltage is 15 V. [ABSTRACT FROM AUTHOR]

The real-time estimation of the AC power system equivalent parameters enables the grid-connected Voltage Source Converter (VSC) to achieve more effective stability control during a short-circuit fault. In this paper, a novel Thevenin Equivalent (TE) parameter estimation method based on local synchronous Phasor Measurement Units (PMUs) is proposed and applied to the Phase-Locked Loop (PLL) synchronization stability control of VSC. First, the relationship between the variation of the measured voltage and the error of the estimated impedance is strictly derived based on the rules of norm inequality. Then, according to the analysis of the upper bound of the system voltage change, a voltage threshold is proposed to select the PMU measurements to ensure the accuracy of the estimation during the large disturbance. Finally, using the estimated TE parameters, the current control instruction of VSC during the fault is calculated in real-time to ensure a synchronous and stable operation. The simulations reveal that the proposed estimation method can accurately track the TE parameters after a fault. Furthermore, the associated current control actions during a fault can ensure the PLL synchronization stability of VSC. [ABSTRACT FROM AUTHOR]

This paper investigates the fin-width ($\text{W}_{\textsf {Fin}}$) sensitivity of threshold voltage ($\text{V}_{\textsf {T}}$) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ for NC-FinFETs. Our study may provide insights for future scaling of FinFETs. [ABSTRACT FROM AUTHOR]

This paper presents the simulation-based comparison between silicon (Si) and silicon carbide (SiC) MOSFETs on the single-event burnout (SEB) performance for the first time. The safe operation areas (SOAs) regarding SEB are extracted and compared between the two structures when the heavy ions with a different linear energy transfer (LET) strike the sensitive areas of the devices. It is demonstrated that benefiting from the higher doped drift region, SiC MOSFET has a larger SEB threshold voltage than Si MOSFET at low LET range. However, it is the other way around at high LET range, which is attributed to the thicker epitaxy of Si MOSFET. The introduction of buffer layer to enhance the SEB hardness is also discussed. Results indicate that a thicker buffer layer is required for SiC MOSFET to enlarge the SOA, resulting in a more serious degradation of the specific ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$). Consequently, other hardening solutions need to be further explored to ensure the safe operation of SiC MOSFET in space applications. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

Multilevel cell (MLC) states with lower threshold voltage endure less cell damage, lower retention error, and less current consumption. Based on these characteristics, it is opportunistic to strengthen MLC flash by introducing bit-flipping that reshapes state proportions on MLC pages. In this paper, we present a holistic study of bit-flipping schemes upon MLC flash in theory and practice. Specifically, we systematically investigate effective bit-flipping schemes and propose four new schemes on manipulating MLC states. We further design a generic implementation framework, named MLC bit-flipping framework, to implement bit-flipping schemes within solid state drives controllers, nicely integrating with existing system-level optimizations to further improve overall performance. The experimental results demonstrate that our proposed bit-flipping schemes standalone can reduce up to 28% cell damages and 53% retention errors. Our circuit-level simulation manifests that the bit-flipping latency on a page is less than 4 $\mu \text{s}$ when using 8K logic gates. [ABSTRACT FROM AUTHOR]

This paper extends Johnson’s classical theory [Johnson, Proc. IRE 43, 684 (1955)] for the threshold of backward-wave oscillation (BWO) in a traveling-wave tube by considering the effects of: 1) small random variations of the circuit phase velocity along the tube axis and 2) end reflections. We find that both the BWO threshold and BWO frequency are minimally affected by random variations of the phase velocity, but we find that the oscillation threshold depends sensitively on the magnitude and phase of the composite reflection coefficients. [ABSTRACT FROM AUTHOR]

Near threshold computing (NTC) has significant role in reducing the energy consumption of modern very large scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This paper presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this paper, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture level analysis. Their experimental results show that in NTC, process variation and aging-induced SNM degradation is $2.5{\boldsymbol \times }$ higher than in the super threshold domain while SER is $8{\boldsymbol \times }$ higher. At NTC, the use of 8T instead of 6T SRAM cells can reduce the system-level SNM and SER by 14% and 22%, respectively. Besides, we observe that we can find the right balance between performance and reliability by using an appropriate cache organization at NTC which is different from the super threshold. [ABSTRACT FROM AUTHOR]

Timing analysis and timing closure are critical steps in digital circuit design. To ensure an error-free design, timing constraints are usually set-based upon the longest path delay from static timing analysis. However, a circuit could have dramatically different internal activity because of the variation of input workload. The path with the longest delay may not be active for certain input workloads, which would enable timing speculation for increased performance. This paper describes an approach to identify the greatest contributors of timing errors and mitigate those errors by replacing certain standard cells in the design. We evaluated our mitigation for several benchmark designs and demonstrated an error-free performance gain up to 37%. The entire design flow uses Synopsys electronic design automation tools and customized scripts, which can be adapted for other designs. [ABSTRACT FROM AUTHOR]

Feedback field-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has conspicuous subthreshold slope (SS) properties, advanced research for structure and performance of it is lacking. In this paper, single-gated and spacer-less silicon-on-insulator (SOI) FBFET with extremely steep switching (~1 mV/decade) characteristic is studied in various aspects; SS attribute, performance variation of scaled FBFET, the impact of structural variation, the gate margin for the device layout, and the hysteresis window. The prospect of SOI FBFET as a future candidate for CMOS logic application is investigated in detail. [ABSTRACT FROM AUTHOR]

This paper proposes amorphous indium–gallium–zinc oxide thin-film transistors (TFTs) four-transistor-two-capacitor (4T2C) pixel circuit in combination with a top-anode organic light-emitting diode (OLED) for the use in 8K4K active-matrix organic light-emitting diode displays (AM-OLEDs). The proposed pixel circuit compensates for driving TFTs threshold voltage (${V} _{\textsf {TH}}$) shifts and mobility variations, ${V} _{\textsf {DD}}$ current–resistance (${I}$ – ${R}$) drops, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ -induced rises. Both the positive and negative ${V} _{\textsf {TH}}$ of the driving TFT can be sensed by the proposed circuit. In this paper, we analyze the impact of the driving TFT compensation time for low gray levels. The current error rates are calculated when TFT mobility variations are considered. The proposed pixel circuit allows an increase in the compensation time to reduce the impact of driving TFT ${V} _{\textsf {TH}}$ and mobility variations on the performance of 4T2C pixel circuit. Conventional two-transistor-one-capacitor, five-transistor-two-capacitor, and proposed 4T2C pixel circuits are simulated and compared in this paper. The proposed pixel 4T2C circuit reduces the current error rates to below 5.79% when the ${V} _{\textsf {TH}}$ shifts of ±2 V, mobility variations of ±10%, ${V} _{\textsf {DD}}~{I}$ – ${R}$ drops of 1 V, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ rises of 1 V are all considered. We show that the proposed 4T2C pixel circuit is suitable for 8K4K AM-OLEDs. [ABSTRACT FROM AUTHOR]

A primary source of increased read time on nand flash comes from the fact that, in the presence of noise, the flash medium must be read several times using different read threshold voltages for the decoder to succeed. This paper proposes an algorithm that uses a limited number of rereads to characterize the noise distribution and recover the stored information. Both hard and soft decoding are considered. For hard decoding, this paper attempts to find a read threshold minimizing bit error rate (BER) and derives an expression for the resulting codeword error rate. For soft decoding, it shows that minimizing BER and minimizing codeword error rate are competing objectives in the presence of a limited number of allowed rereads, and proposes a tradeoff between the two. The proposed method does not require any prior knowledge about the noise distribution but can take advantage of such information when it is available. Each read threshold is chosen based on the results of previous reads, following an optimal policy derived through a dynamic programming backward recursion. The method and results are studied from the perspective of an SLC Flash memory with Gaussian noise, but this paper explains how the method could be extended to other scenarios. [ABSTRACT FROM PUBLISHER]

In this paper, the NbOx, which was regarded as a promising material based on its insulator–metal transition (IMT) effects, was applied as the switching layer of the device. The threshold switching characteristics were comprehensively investigated with particular emphasis on temperature dependence. The conduction mechanism for high-resistance state (HRS) was fitted and verified to be Schottky emission. With the increase in temperature, the fitting results demonstrated that the Schottky barrier decreased, leading to a reduction in the resistance of HRS. Furthermore, according to Fourier’s law of heat conduction, the fluctuation range of temperature was smaller, causing a narrow distribution of the threshold voltage as the operating temperature increased. In addition, the increasing temperature caused high energy of electrons, which would induce an IMT more easily, leading to a lower threshold voltage. This paper provided the promise for improving the thermal stability of selected devices. [ABSTRACT FROM AUTHOR]

The aim of this paper is the analysis of the multipactor effect in a parallel-plate waveguide when a ferrite slab, transversally magnetized by a static magnetic field parallel to the waveguide walls, is present. Employing an in-house developed code, numerical simulations are performed to predict the multipactor radio frequency voltage threshold in such a ferrite-loaded waveguide. Variations of the ferrite magnetization field strength and the ferrite slab height are analyzed. Effective electron trajectories are also shown for a better understanding of the breakdown phenomenon, finding different multipactor regimes. [ABSTRACT FROM AUTHOR]

In this paper, we propose a single probability density function for the distributions of the delay in the presence of the process variation for different regions of operation. The delay variation model is inspired by considering the analytical current models for each operating region. Based on these models, we suggest using the log-skew-normal distribution for modeling the delay variation for a wide range of supply voltages from the subthreshold to above-threshold regions. To assess the accuracy of the proposed delay distribution, the mean, standard deviation, skewness, 99th percentile, and yield of the proposed distribution are compared with those of the normal and log-normal distributions using the Monte Carlo (MC) simulations for different circuits in both bulk and FinFET technologies. The results show a higher accuracy for the proposed distribution in all regions of operation. Also, the proposed model enables us to obtain the 3 \sigma yield of the distribution using up to 3.4 times less MC simulation time. [ABSTRACT FROM PUBLISHER]

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( V\mathrm{ bs} ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive V\mathrm{ bs} due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate. [ABSTRACT FROM PUBLISHER]

Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time ( T\mathrm{RA} ), and write access time ( T\mathrm{ WA} ) are also presented. The proposed cell achieves 1.12\times /\mathrm 1.\mathrm 43\times /\mathrm 5.\mathrm 62\times improvement in T\mathrm {RA} compared to TG8T/D6T/SE8T at a penalty of 1.1\times /4.88\times in T\mathrm{ WA} compared to D6T/TG8T and 1.19\times /1.18\times in read/write power consumption compared to D6T. An improvement of 1.\mathrm 12\times /\mathrm 2.\mathrm 15\times in RSNM is observed compared to D6T/TG8T. The proposed cell consumes 5.38\times less power during hold mode and also shows 2.33\times narrower spread in hold power @ V\mathrm{ DD = 0.{\mathrm{ 4}}} V compared to D6T SRAM cell. [ABSTRACT FROM AUTHOR]

In this paper, we present a systematic procedure for the design of a channel profile of an epitaxial delta doped channel ( \textE\delta DC) MOS transistor so that the intrinsic gain ( Av ) is high and the threshold voltage ( VT ) mismatch is low. Analytical study shows that a tradeoff relation exists between low VT mismatch and high AV with respect to the thickness of the channel region. Therefore, careful selection of the design parameters is essential in order to have an optimum performance. The performance characteristics of the designed device are subsequently verified through Technology Computer Aided Design simulations. In order to demonstrate the benefits of using optimized \textE\delta DC transistor, we compare its performance with that of a reference deeply depleted channel MOS transistor. The performance improvement of using optimized \textE\delta DC transistor with respect to the chosen objectives is clearly explained. [ABSTRACT FROM AUTHOR]

In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs). We propose a mixed TFET–MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET–MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET–MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions. [ABSTRACT FROM PUBLISHER]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

This paper proposes a novel memristor-based multiplexer implemented by using NOT-material implication. The proposed design can be extended to arbitrary ${N}$ -bit inputs and the enable-port can be added to improve its structure. Furthermore, this structure can be applied in the cascade circuit and crossbar array. A novel peripheral read circuit is introduced to overcome the problem that it is difficult to read out the operation results stored in crossbar array with large scales. The feasibility and correctness of our design is verified by the HSPICE simulation results with voltage threshold adaptive memristor model. [ABSTRACT FROM AUTHOR]

In this paper, the charge-plasma structure over the source/drain region is incorporated into a dopingless junctionless transistor for obtaining the superior immunity of line edge roughness (LER). An optimized on/off current ratio is observed by using numerical simulations. It is also demonstrated that the proposed charge-plasma junctionless transistor (CP-JLT) is insensitive to the variation of LER magnitude. We further reveal the physics that LER affects the electrical characteristics of CP-JLT. Channel minimal width position variation and channel width variation are put forward to explore the impact of LER for the first time. It is observed that the LER affects the ${I}_{\text {ON}}$ of CP-JLT due to the changes of the source width caused by channel minimal width position variation, whereas the LER affects the ${I}_{\text {OFF}}$ , SS, and ${V}_{\text {th}}$ mainly through channel width variation. It is thus proved to be a helpful guide to suppress the LER variation of CP-JLT. [ABSTRACT FROM AUTHOR]

Security is one of the top considerations in hardware designs for Internet-of-Things (IoT), where embedded cryptosystems are extensively used. Traditionally, random dynamic voltage scaling technology has been shown to be very effective in improving the resistance of cryptosystems against side-channel attacks. However, in this paper we demonstrate that the resistance can be undermined by providing lower off-chip power supply voltage. In order to address this issue, we then further propose to monitor the off-chip power supply voltage, and trigger an alarm to protect valued information once the power supply voltage is lower than the expected voltage (threshold voltage). However, considering both maintenance cost of IoT devices and the environment noise on power supply voltage, we first formulated this problem as a nonzero sum game model, and the attacker and the circuit supplier (defender) are the players of this game. The analysis of the Nash equilibria in this game show interesting guideline to the defender about the choice of threshold voltage, which is based on parameters of cryptosystem including the value of information, denial-of-service cost in IoT, etc. [ABSTRACT FROM PUBLISHER]

In contrast to the conventional planar p-i-n photodiode and a metal-semiconductor-metal photodetector, the 3-D dual-gate photosensitive thin-film transistor (TFT) architectures presented here attain excellent photoresponse characteristics. Operating the device in the subthreshold regime further boosts the photoconductive gain as a result of light-induced decrease in the threshold voltage. This paper presents design considerations along with a performance comparison between 3-D photosensitive TFTs that have π- and FIN-shaped channels and conventional TFT with a planar channel. Our paper shows that the π-shaped structure tends to have a higher sensitivity while the FIN-shaped counterpart is more responsive with wider dynamic range. For both structures, a measured photoconductive gain of 104~106% is obtained with spectral responsivity ranging from near UV to near IR, and the photoresponse time in the range of tens of milliseconds. The 3-D dual-gate photosensitive TFT architecture appears to be very promising for large-area, low-level UV, visible, and IR detection applications. [ABSTRACT FROM AUTHOR]