Search

This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration-friendly vertical terminals and horizontal channel manufactured based on SOI wafer with conventional CMOS fabrication hardware. The second gate provides the capability of transistor behavior adjustment and the potential for advanced circuit designs. The results show that VeSFET can provide high I {\mathrm {eff}} to I {\mathrm {off}} ratio, low gate capacitance, high \Delta V {t}/ V { {\textit{g2s}}} , and competitive drive capability with respect to a reference FinFET of comparable dimensions. [ABSTRACT FROM PUBLISHER]

In this paper, it is shown empirically and through simulation that transistor mismatch due to random dopant fluctuation is a function of the well and halo design of the transistor, and that, contrary to conventional expectation, low-threshold transistors can have larger mismatch than higher threshold transistors. The complex dependence of mismatch on well and halo profiles suggests the need for the extension of the conventional Pelgrom approach to characterizing mismatch for a given technology and also suggests means of optimizing mismatch for analog applications. A set of screening criteria for mismatch data analysis are presented to verify that conclusions drawn from the standard deviation of a distribution may be properly applied. [ABSTRACT FROM PUBLISHER]

In contrast to the generally accepted expectation that mismatch is monotonically related to doping level for uniformly doping channels, apparently anomalous results in which short-channel low-doped devices have larger mismatch than higher doped high-threshold devices are shown. However, these results are fully explained and comprehended in the context of device design and random dopant fluctuation, and the correlation of short-channel effect with mismatch suggests yet another manner in which fully depleted undoped-body devices will offer better variation than classic scaled dopant-driven transistors, addressing a critical problem in new technology directions. [ABSTRACT FROM PUBLISHER]

Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon–germanium (SiGe) for p-type field effect transistor (pFET) at 32 nm and beyond are useful because of higher mobility and lower threshold voltage ($\text{V}_{T}$) but suffer from higher gate-induced drain leakage (GIDL) and could be a source of additional variability. In this paper, experimental results, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe pFET process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random GIDL and performance variations. This is primarily due to random dopant position fluctuations in the extension region for off-state leakage (${I}_{ \mathrm{\scriptscriptstyle OFF}} $) variability and in the halo region at the drain sidewall for $\text{V}_{T}$ variability. However, the increase in random variability without Ge PAI reduces for lower supply voltages and, thus, offers advantages of reduced GIDL with the same electrostatics, lower systematic variations, and similar ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ random variability for scaled voltages. [ABSTRACT FROM AUTHOR]

An analytical model of parasitic capacitancein inserted-oxide FinFETs (iFinFETs) is proposed. A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented. The proposed model is validated against 3-D Technology Computer-Aided Design (TCAD) simulations. Dependence of the iFinFET parasitic capacitance on device design parameters, such as the inserted-oxide thickness (Tiox) and inserted-oxide recess (Trec), is shown using the proposed model and TCAD simulations. [ABSTRACT FROM AUTHOR]

Transistor mismatch data and analysis from poly/SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (AVT) continuously scales down as technology advances. Furthermore, the AVT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing the mismatch data against electrical oxide thickness (TINV), threshold voltage (VTH), and effective work function, a direct comparison of the mismatch data from various technologies is made. The differences in nFET and pFET mismatch behaviors in both poly/SiON and HKMG technologies are discussed in detail. Correlation between transistor VTH mismatch and flicker noise variation is observed in both poly/SiON and HKMG technologies. Finally, it is quantitatively demonstrated that effective work function variation does not generate significant VTH variability in the present HKMG technology. [ABSTRACT FROM AUTHOR]