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The support for local variables in SystemVerilog assertions significantly enhances its expressive power. Handling local variables in analog and mixed-signal (AMS) extensions of assertion languages is tricky due to the dense time interpretation of AMS assertions, and has not been adequately treated in existing literature. This paper presents an approach for interpreting local variables in AMS assertions during simulation and a tool flow that works with standard mixed-mode simulators. [ABSTRACT FROM AUTHOR]

A 12-bit 104 MS/s successive approximation register analog-to-digital converter (SAR ADC) is developed for a digitally-assisted wireless transmitter system for use in cellular applications. A power-on calibration method is implemented to correct capacitor DAC mismatch and reduce capacitor size, thereby lowering the current consumption of the input buffer and reference generator. The total capacitor size is reduced to 0.6 pF, from the 3.6 pF required for 12-bit matching. The ADC analog core area is 0.003 mm2. The proposed method achieves 88 dB SFDR at 26 MHz sampling rate and 76.2 dB SFDR at 104 MHz sampling rate after calibration. The measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The ADC achieves both high speed and low power by combining several features, namely digital calibration, redundancy, asynchronous bit-cycling, monotonic switching, 25% duty-cycle sampling period, 3 dB input gain, and a fully dynamic comparator. The power consumption from 1.2 V/1.1 V supplies is 0.88 mW for a single ADC core and 6.1 mW for the entire I/Q ADC, including the reference generator and input buffers. The ADC is fabricated in 28 nm CMOS. [ABSTRACT FROM PUBLISHER]

We consider resource allocation for semi-elastic applications, such as mobile video conferencing, which require a maximum outage. We represent the performance of a session by a sigmoid utility function of the average bit rate over a time window consisting of many slots. The goal is to maximize the total expected utility of all active users. A principal challenge is the difference in timescales: The outage is measured over sessions, whereas the average bit rate is measured over a time window such as a group of pictures. We propose that these differences in timescales can be elegantly addressed by shadow prices: a price per unit average rate over each time window and a price per unit outage. We further propose that the price per unit average rate depends on combined path loss and shadowing but not on fast fading. We show that resources can be efficiently allocated if the base station chooses prices based on the total demand and if the users respond by choosing average rates. The performance of our algorithm is illustrated by simulation results. [ABSTRACT FROM PUBLISHER]

With the recent upsurge in experimental efforts toward fabrication of short-channel graphene field-effect transistors (GFETs) for analog and high-frequency RF applications—where the advantages of distinctive intrinsic properties of gapless graphene are expected to be leveraged—a critical understanding of the factors affecting both output and transfer characteristics is necessary for device optimization. Analyzing the device characteristics through ballistic electronic transport simulations within the nonequilibrium Green's function formalism, we show that a doping in the drain underlap region can significantly improve the quasi-saturation behavior in the GFET output characteristics and, hence, the output resistance and intrinsic gain. From this understanding, we provide a unified and coherent explanation for seemingly disparate phenomena—quasi-saturation and the recently reported three-terminal negative differential resistance in GFETs. We also investigate the scaling behavior of cutoff frequency and comment on some of the observed scaling trends in recent experiments. [ABSTRACT FROM AUTHOR]

We develop sub-Nyquist sampling systems for analog signals comprised of several, possibly overlapping, finite duration pulses with unknown shapes and time positions. Efficient sampling schemes when either the pulse shape or the locations of the pulses are known have been previously developed. To the best of our knowledge, stable and low-rate sampling strategies for continuous signals that are superpositions of unknown pulses without knowledge of the pulse locations have not been derived. The goal in this paper is to fill this gap. We propose a multichannel scheme based on Gabor frames that exploits the sparsity of signals in time and enables sampling multipulse signals at sub-Nyquist rates. Moreover, if the signal is additionally essentially multiband, then the sampling scheme can be adapted to lower the sampling rate without knowing the band locations. We show that, with proper preprocessing, the necessary Gabor coefficients, can be recovered from the samples using standard methods of compressed sensing. In addition, we provide error estimates on the reconstruction and analyze the proposed architecture in the presence of noise. [ABSTRACT FROM PUBLISHER]

This paper presents SANGRIA, a tool for automated globally reliable variation-aware sizing of analog integrated circuits. Its keys to efficient search are adaptive response surface modeling, and a new concept, structural homotopy. Structural homotopy embeds homotopy-style objective function tightening into the search state's structure, not dynamics. Searches at several different levels are conducted simultaneously: The Ioosest level does nominal dc simulation, and tighter levels add more analyses and {process, environmental} corners. New randomly generated designs are continually fed into the lowest (cheapest) level, always trying new regions to avoid premature convergence. For further efficiency, SANGRIA adaptively constructs response surface models, from which new candidate designs are optimally chosen according to both yield optimality on model and model prediction uncertainty. The stochastic gradient boosting models support arbitrary nonlinearities, and have linear scaling with input dimension and sample size. SANGRIA uses SPICE in the loop, supports accurate/complex statistical SPICE models, and does not make assumptions about the convexity or differentiability of the objective function. SANGRIA is demonstrated on four different analog circuits having from 10 to 50 devices and up to 444 design/process/environmental variables. [ABSTRACT FROM AUTHOR]

An analog implementation of a control structure with disturbance identification for mechanical systems is presented. This control structure is based on a discontinuous observer that estimates the state and the disturbances in the plant, improving the robustness of the closed loop system which also displays a control input free from chattering. The control structure, built with operational amplifiers, is simple, showing good performance for stabilization, regulation, and tracking objectives. The performance of the circuit is compared with a digital implementation based on a real-time data acquisition card to control a simple pendulum. In addition, the circuit performance is illustrated on an industrial 2-DOF robot. [ABSTRACT FROM AUTHOR]

A new approach is proposed for evaluating circuit robustness against Single Event Transients (SETs) through FPGA emulation. A voltage-time quantization model allows capturing circuit delays in the FPGA, including electrical masking effects. Experimental results demonstrate this approach improves SET fault injection rate by three orders of magnitude with respect to logic simulation and provides an accuracy close to analog simulation. [ABSTRACT FROM AUTHOR]

It was shown in our previous work that, in the noise-free case, the whitening-rotation (WR)-based MIMO channel estimation algorithm is subject to a signal perturbation error, justifying that the WR-based method is efficient only in the low signal-to-noise ratio (SNR) case. In this paper, a very efficient signal-perturbation-free WR-based approach is proposed for semiblind channel estimation of MIMO systems. A novel transmit scheme is developed based on the eigenvalue decomposition of the correlation matrix of the transmitted signal. The new scheme is to send a small volume of data bearing the information of the correlation matrix to the receiver for the cancellation of the signal perturbation error so as to improve the performance of the WR-based method in the case of high SNRs. Then, a perturbation analysis of the proposed WR-based semiblind method with the new transmit scheme is conducted, leading to a closed-form expression for the mean square error (MSE) of the channel estimate. Computer simulations show that the proposed approach significantly outperforms the original WR-based method as well as some other channel estimation methods for all SNR levels. [ABSTRACT FROM AUTHOR]

To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetric-feasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first linear-time-packing algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*-tree representation, we propose automatically symmetric-feasible (ASF) B*-trees to directly model the placement of a symmetry island. We then present hierarchical B*-trees (HB*-trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B*-tree or an HB*-tree is the same as that for a plain B*-tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the best-published quality and runtime efficiency for analog placement. [ABSTRACT FROM AUTHOR]

To store and retrieve large-scale video data sets effectively, the process of shot-change detection is an essential step. In this paper, we propose an automatic shot-change detection algorithm based on Visual Rhythm Spectrum. The Visual Rhythm Spectrum contains distinctive patterns or visual features for many different types of video effects. For the improvement of detection speed, the proposed algorithm is executed by using the partial data of digital compressed video. The proposed detection algorithm can be universally applied to various kinds of shot-change categories such as scene-cuts and wipes. The developed wipe detector is implemented and tested with real video sequences containing a variety of wipe types and lengths. It is shown by simulations that the proposed detection algorithm outperforms other existing approaches. [ABSTRACT FROM AUTHOR]

Part I of this paper dealt with the simulation study, using ATLAS 2D, of analog-circuit performance metrics for the dual-material-gate (DMG) silicon-on-nothing (SON) MOSFET. It was reported that, out of the several combinations in the DMG design studied, the DMG device with LM1 /L ratio as 1/2 amalga- mates the advantages of using a high metal work-function gate M1 and low metal work-function gate M2 in the most efficient manner. This paper focuses upon the effect of double-layer gate stack (DGS) (high.k/SiO2) on the single-material-gate (SMG) SON and the DMG SON MOSFETs. Improved Early voltage and reduced output conductance of the DMG SON MOSFETs are the driving forces behind the observed increase in intrinsic gain and fT-gain relationship for the DMG devices over SMG SON MOSFETs, with the DMG SON MOSFETs having LM1 /L ratio as 1/2, proving to be the best choice among various LM1/L ratios studied. A further improvement in intrinsic gain in DMG DGS SON MOSFETs comes about because of increased gate control on the channel, thus establishing design guidelines aiming at higher gain and better fT-gain relationship. [ABSTRACT FROM AUTHOR]

Part I of this paper dealt with the simulation study, using ATLAS 2D, of analog-circuit performance metrics for the dual-material-gate (DMG) silicon-on-nothing (SON) MOSFET. It was reported that, out of the several combinations in the DMG design studied, the DMG device with LM1/L ratio as 1/2 amalgamates the advantages of using a high metal work-function gate Ml and low metal work-function gate M2 in the most efficient manner. This paper focuses upon the effect of double-layer gate stack (DGS) (high-k/SiO2) on the single-material-gate (SMG) SON and the DMG SON MOSFETs. Improved Early voltage and reduced output conductance of the DMG SON MOSFETs are the driving forces behind the observed increase in intrinsic gain and fT-gain relationship for the DMG devices over SMG SON MOSFETs, with the DMG SON MOSFETs having LM1/L ratio as 1/2, proving to be the best choice among various LM1/L ratios studied. A further improvement in intrinsic gain in DMG DGS SON MOSFETs comes about because of increased gate control on the channel, thus establishing design guidelines aiming at higher gain and better fT-gain relationship. [ABSTRACT FROM AUTHOR]

This paper focuses on error-correcting codes for analog signals. Generally, error-correcting codes exhibit a threshold effect, which degrades performance at the low signal-to-noise ratio (SNR) range. We propose two error-correction alternatives based on chaotic dynamical systems, which improve threshold performance relative to previously proposed methods. The first one, which is based on principles of diversity, exhibits a very simple decoder. The second alternative, which is based on a low-density parity-check (LDPC) code, attains a significantly lower threshold. Theoretical analysis and simulations are provided. [ABSTRACT FROM AUTHOR]

A major problem in oversampling digital-to-analog converters and fractional-N frequency synthesizers, which are ubiquitous in modern communication systems, is that the noise they introduce contains spurious tones. The spurious tones are the result of digitally generated, quantized signals passing through nonlinear analog components. This paper presents a new method of digital requantization called Successive Requantization, special cases of which avoids the spurious tone generation problem. Sufficient conditions are derived that ensure certain statistical properties of the quantization noise, including the absence of spurious tones after nonlinear distortion. A practical example is presented and shown to satisfy these conditions. [ABSTRACT FROM AUTHOR]

Analog adaptive filters are an important subset of adaptive-filter theory and practice. They are preferable at high speeds when low power consumption, small integrated area, and moderate linearity are required. In this paper, an analog adaptive-disturbance canceller is presented. The canceller uses the analog least mean square (LMS) algorithm, and its structure is similar to a linear combiner. The operation of the proposed canceller is based on the decomposition of the disturbances into the in-phase and quadrature components by means of a Hilbert transformer, which is used as an analog LMS for the cancellation of each component. Finally, some experimental results, which are obtained from a low-cost discrete-component realization of the proposed canceller, are presented. The proposed structure is also suitable for very large-scale integration designs. [ABSTRACT FROM AUTHOR]

Two equalizer filter topologies and a merged equalizer/CDR circuit are described that operate at 10 Gb/s in 0.13-μm CMOS technology. Using techniques such as reverse scaling, passive peaking networks, and dual- and triple-loop adaptation, the prototypes adapt to FR4 trace lengths up to 24 inches. The equalizer/CDR circuit retimes the data with a bit error rate of 10-13 while consuming 133 mW from a 1.6-V supply. [ABSTRACT FROM AUTHOR]

In this paper, we present a low-power small-area electrical backplane equalizer using programmable analog zeros and folded active inductors. We also present a dc-offset cancellation circuit, which occupies less chip area than the traditional offset cancellation schemes. The equalizer circuit was fabricated in a 1.0-V 90-nm CMOS process. With one zero stage, the equalizer occupies 0.015-mm² chip area and dissipates 12 mW of power. At 4.25-Gb/s data rate, the equalizer provides 7.8-dB gain boost at the Nyquist frequency. Without the use of any transmitter equalization, the analog zero equalizer demonstrated error-free transmission for pseudorandom-bit-sequence-31 data patterns over 34-in lossy FR4 backplanes. [ABSTRACT FROM AUTHOR]

The local cluster neural network (LCNN) was designed for analog realization especially suited to applications in control systems. It uses clusters of sigmoidal neurons to generate basis functions that are localized in multidimensional input space. Sigmoidal neurons are well suited to analog electronic realization. In this paper, we report the results of extensive measurements that characterize the computational capabilities of the first analog very large scale integration (VLSI) realization of the LCNN. Despite manufacturing fluctuations and the inherent low precision of analog electronics, the test results suggest that it may be suitable for use in feedback control systems. [ABSTRACT FROM AUTHOR]

This paper addresses the accurate time-domain simulation of closed-loop switched circuits. It is known that for such systems, conventional analog simulation can be critical due to the presence of strongly nonlinear switching devices. In order to overcome the drawback, in this paper, an in-depth investigation of the weakness points of analog simulation is first presented. On the basis of the achieved understanding, a novel accurate and efficient simulation technique that combines conventional analog simulation with a suited event-driven management of internally controlled commutations is presented. The proposed method employs a novel algorithm for locating commutation time instants and a regionwise evaluation of critical switching devices. The method is general and can be easily inserted into analog simulator tools. [ABSTRACT FROM AUTHOR]

This paper presents a simple and low-cost analog architecture for computing 2-D discrete cosine transform (2-D DCT). The proposed circuit is aimed for low-power or very high-speed moderate image quality video compression applications. The design uses current-mode signaling and has two separate 1-D DCT kernels, thus no memory is needed for storing intermediate results. Moreover, the circuit works in continuous time. Simple current mirrors have been used to realize all the needed matrix operations and the transistors are dimensioned in such a way that current level of 20 μA is not exceeded to ensure low-power operation. A prototype chip which includes both 4-point and 8-point forward transforms has been fabricated in a 0.18-μm digital CMOS technology. The operation of the circuit is analyzed with help of measurement results obtained from test chips. [ABSTRACT FROM AUTHOR]

In this letter, a different feedback structure of the repetitive control that apparently is more appropriate for applications in power electronics is proposed. Moreover, a simple analog-circuit implementation is proposed which is suitable for high-frequency power electronics applications, where digital control is unpractical due to cost and performance of available DSPs and microcontrollers. [ABSTRACT FROM AUTHOR]

We present data showing a new total-dose-induced parasitic effect in enclosed-geometry transistors. A model for this new effect shows that the normal radiation-induced edge leakage current becomes gate controlled in ringed-source transistors. Small width-to-length (W/L) N-channel field-effect transistors (NFETs), often used in analog designs, show an additional drain current and transconductance, because the gate-controlled leakage current approaches the magnitude of the ideal channel current. [ABSTRACT FROM AUTHOR]

This work presents the design and the test results of an analog decoder for the 40-bit block length, rate ⅓, Turbo Code defined in the UMTS standard. The prototype is fully integrated in a three-metal double-poly 0.35-µm CMOS technology, and includes an I/O interface that maximizes the decoder throughput. After the successful implementation of proof-of-concept analog iterative decoders by different research groups in both bipolar and CMOS technologies, this is the first reported prototype of an analog decoder for a realistic error-correcting code. The decoder was successfully tested at the maximum data rate defined in the standard (2 Mb/s), with an overall power consumption of 10.3 mW at 3.3 V, going down to 7.6 mW with the decoder core operated at 2 V, and an extremely low energy per decoded bit and trellis state (0.85 nJ for the decoder core alone). [ABSTRACT FROM AUTHOR]

This paper discusses digital compensation for frequency-dependent transfer characteristics and implementation errors in digital PAM/continuous-phase frequency-shift keying (CPFSK) quadrature modulators. Recently, several methods have been proposed to digitally compensate for the shortcomings of the analog reconstruction filters in IQ modulators. While these methods have shown to be effective, they result in filters with long coefficients that are computationally demanding to implement on the DSP. Furthermore, the modulator needs to be taken of- fine while the precompensation filters are updated to reflect the changes in the I and Q channel characteristics. In this paper, a digital compensation method is proposed here using two adaptive finite-impulse response filters to compensate for the magnitude and phase characteristics of the analog reconstruction filters in the IQ modulator. The experimental results show that this technique is effective and lead to substantial improvement of the output envelope ripples. [ABSTRACT FROM AUTHOR]

Although several authors have proposed different devices to measure the iron loss in magnetic sheets used in the building of electrical machines, few of them take into account the real electromagnetic working context. This paper deals with the possibility of determining the iron loss and the apparent magnetic permeability from the measurement of the flux density in the air gap with the use of the Maxwell's tensor and an analog computer. We propose new methods to obtain the power loss and the magnetic permeability of magnetic samples. [ABSTRACT FROM AUTHOR]

The effect of current crowding on dc, on ac, and in particular on the noise characteristic of bipolar transistors, is studied. An equivalent circuit able to model these effects is presented. General formulations to calculate current crowding in arbitrary geometries are derived. Both rectangular and circular geometries are discussed in detail. [ABSTRACT FROM AUTHOR]

This paper, which is mostly tutorial in nature, deals with the design of CMOS microelectromechanical systems MEMS using standard microelectronic computer-aided design tools. The proposed case study is an on-chip spectrum analyzer with an electronic mixer and a mechanical filter. Based on both analytical modeling and characterization, the filter is described using an analog hardware description language. System level simulations are then performed using a recently released simulation tool that offer new possibilities regarding the analysis of multidomain, multifrequency designs. Presented results include periodic steady state determination, small-signal analysis and noise investigation. The simulations demonstrate the ability of the proposed system to identify the harmonics of a 50-Hz square-wave signal, owing to the selectivity of the mechanical filter. [ABSTRACT FROM AUTHOR]

Efficient algorithms are presented to generate approximate expressions for transfer functions and characteristics of large linear-analog circuits. The algorithms are based on a compact determinant decision diagram (DDD) representation of exact transfer functions and characteristics. Several theoretical properties of DDDs are characterized, and three algorithms, namely, based on dynamic programming, based on consecutive k-shortest path (SP), and based on incremental k-SP, are presented in this paper. We show theoretically that all three algorithms have time complexity linearly proportional to |DDD|, the number of vertices of a DDD, and that the incremental k-SP-based algorithm is fastest and the most flexible one. Experimental results confirm that the proposed algorithms are the most efficient ones reported so far, and are capable of generating thousands of dominant terms for typical analog blocks in CPU seconds on a modem computer workstation. [ABSTRACT FROM AUTHOR]

Ultra-wideband (UWB) transmissions have well-documented advantages for low-power, peer-to-peer, and multiple-access communications. Space-time coding (STC), on the other hand, has gained popularity as an effective means of boosting rates and performance. Existing UWB transmitters rely on a single antenna, while ST coders have mostly focused on digital linearly modulated transmissions. In this paper, we develop ST codes for analog (and possibly nonlinearly) modulated multiantenna UWB systems. We show that the resulting analog system is able to collect not only the spatial diversity, but also the multipath diversity inherited by the dense multipath channel, with either coherent or noncoherent reception. Simulations confirm a considerable increase in both bit-error rate performance and immunity against timing jitter, when wedding STC with UWB transmissions. [ABSTRACT FROM AUTHOR]

Focuses on the design of analog front ends (AFE) for a 1000BASE-T receiver, a local area computer network system. Characteristics of 1000BASE-T receiver; Discussion on the receiver's architecture and AFE functionality; Description of different AFE architectures; Information on results showing receiver performance with different AFE architectures.

Describes a technique for fast fault simulation of nonlinear analog circuits. Evaluation of test effectiveness in mixed-signal integrated circuits; Use of simulation latency to speed up the simulation; Newton-Raphson iterations. INSET: Previous work..

Examines the methodology for the physical design automation of array-type analog blocks. Constraints in designing an analog block; Procedural process of floorplanning, symbolic routing and technology mapping; Analysis on the efficiency of the proposed methodology in designing analog layouts.

Presents a study which discussed an analog simulation of the dynamics of a system consisting of a van der Pol oscillator coupled to a Duffing oscillator. Design of the analog simulator; Amplitude-response curves; Bifurcation and onset of chaos.

Presents information on a study which provided an overview of the VHDL-AMS hardware description language (HDL) for analog and mixed-signal applications. Foundations of VHDL-AMS; Description of the language elements and some examples; Semantics of VHDL-AMS regarding initialization and the simulation of analog and mixed-signal systems; Conclusion.

Presents a method to teach discrete-time systems analysis concepts and skills to engineering students using analog circuit simulators. Construction of the discrete-time delay elements and sampler using the PSpice circuit simulator; Simulation of the nonlinear quadratic model of chaos; Comparison between the result of the approach presented with analytical results.

Describes the integrated circuit that contains features associated with the processing of analog signals within a camcorder or a digital still camera. Difference of amplifier and bias circuits from single ended-to-differential converters; Background information about the input lamp; How the output from the data and reference channel was processed.

Examines a study conducted on sleep, by the development of a develop a low-cost circuit for real-time analog computation of the respiratory mechanical impedance. Description of the method used; Results on the studies; Discussion on the results.

Analyzes continuous-time networks for solving convex nonlinear unconstrained programming problems. Discussion on networks for optimizing objective functions of one variable; Analysis of a one-dimensional optimizer; Information on a different line search optimizer; Evidence to show that the proposed optimizer network is robust; Details on the implementation of the proposed network.

The ac Josephson effect for a current-driven Josephson junction enhanced by a non-monochromatic input signal is studied based on an analog simulation. The obtained rf-induced step-height in the current-voltage characteristic which is a measure of this effect suggest that the use of either a pulse train or a biharmonic consisting of fundamental and second harmonic sinusoidal functions is effective for the enhancement, if compared to a monochromatic signal drive. It is revealed that the individual phase locking between the rf-signal and the Josephson oscillation is much more stabilized by use of the pulse train-like signal and can be explained qualitatively by a pendulum motion, i.e., the relatively slow motion of the pendulum near the position of rest. [ABSTRACT FROM PUBLISHER]

Describes a modal reduced dynamic equivalent model which was developed for an analog type power system simulator to provide power system reductions. Application of modal reduced dynamic equivalent method (MOREM) to an analog simulator; Concepts in developing MOREM; Configuration and operation of MOREM; Verification tests and evaluation of MOREM; Conclusions.

In the paper “An analog 2-D DCT processor,” authors have presented a row-column method for computing 2-D discrete cosine transform (DCT). They have reported minimum peak signal-to-noise ratios (PSNR) 40.6 dB and 31.4 dB for 4-point and 8-point DCT, respectively. The main objective of this comment letter is to point out that those PSNR values are not correctly calculated. The actual minimum PSNR values are shown to be 24.7 dB and 22.7 dB for 4-point and 8-point DCT, respectively. Similarly, maximum PSNR values are corrected in this letter. [ABSTRACT FROM PUBLISHER]

As the semiconductor industry continues scaling devices toward smaller process nodes, maintaining acceptable yields despite process variations has become increasingly challenging. Analog and RF circuits are particularly sensitive to process variations. This article discusses the challenges of cost-effective postfabrication performance calibration in such analog and RF devices and introduces a single-test, single-tuning-step method to constrain cost and complexity while reaping the benefits of a tunable design. [ABSTRACT FROM PUBLISHER]