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In this paper, we report a hierarchical simulation study of the electromigration (EM) problem in Cu-carbon nanotube (CNT) composite interconnects. This paper is based on the investigation of the activation energy and self-heating temperature using a multiscale electrothermal simulation framework. We first investigate the electrical and thermal properties of Cu-CNT composites, including contact resistances, using the density functional theory and reactive force field approaches, respectively. The corresponding results are employed in macroscopic electrothermal simulations taking into account the self-heating phenomenon. Our simulations show that although Cu atoms have similar activation energies in both bulk Cu and Cu-CNT composites, Cu-CNT composite interconnects are more resistant to EM thanks to the large Lorenz number of the CNTs. Moreover, we found that a large and homogenous conductivity along the transport direction in interconnects is one of the most important design rules to minimize the EM. [ABSTRACT FROM AUTHOR]

In this letter, we report a quantum transport simulation study of the impact of random discrete dopants (RDDs) on Si-InAs nanowire p-type Tunnel FETs. The band-to-band tunneling is simulated using the non-equilibrium Green’s function formalism in effective mass approximation, implementing a two-band model of the imaginary dispersion. We have found that RDDs induce strong variability not only in the OFF-state but also in the ON-state current of the TFETs. Contrary to the nearly normal distribution of the RDD-induced ON-current variations in conventional CMOS transistors, the TFET’s ON-currents variations are described by a logarithmic distribution. The distributions of other figures of merit (FoM) such as threshold voltage and subthreshold swing are also reported. The variability in the FoM is analyzed by studying the correlation between the number and the position of the dopants. [ABSTRACT FROM AUTHOR]

2-D numerical simulations are used to demonstrate the Z2-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature. [ABSTRACT FROM AUTHOR]

The experimental results from 8 nm diameter silicon nanowire junctionless field-effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/ $\mu$m for 1.0 V and 2.52 mA/ \mu$m for 1.8 V gate overdrive with an off-current set at 100 nA/\mu$m. On- to off-current ratios above 10^8C. Simulations using drift-diffusion which include density-gradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength. [ABSTRACT FROM PUBLISHER]

A comprehensive statistical investigation of the increase in resistance associated with charge trapping in atomistic simulations is presented. A wide range of doping densities and mesh spacing are considered for both classical and quantum formalisms. A doping-dependent correction factor to modify the mobility model for the atomistic simulations is proposed to suppress the error related to the fictitious charge trapping. The validity of the new mobility model is tested in the statistical simulations of the transistors corresponding to 20-nm bulk CMOS and 14-nm FinFET transistors. [ABSTRACT FROM AUTHOR]

In this paper, by means of simulation, we have studied the implications of using channel doping to control the threshold voltage and the leakage current in bulk silicon FinFETs suitable for the 10-nm CMOS technology generation. The channel doping level of high-performance FinFETs designed for 100-nA/ \(\mu \) m leakage current has been increased to achieve 10 and 1-nA/ \(\mu \) m leakage currents. Ensemble Monte Carlo (EMC) simulations are used to estimate the impact of the increased doping on the transistor performance. Atomistic drift-diffusion simulations calibrated to the results of the EMC simulations are used to evaluate the impact of random discrete dopants, line edge roughness, and metal gate granularity on the statistical variability. The results of the statistical variability simulations are also used to highlight errors resulting from the use of continuous doping in the TCAD simulation of advanced CMOS technology generation FinFETs. [ABSTRACT FROM PUBLISHER]

In this paper, we compare results from atomistic and continuous simulation of decananometer scale CMOS transistors. We study the behavior of important figures of merit, including threshold voltage, subthreshold slope, OFF-current, and ON-current. We provide physical explanation for the origin of the discrepancies between the averaged values obtained from the statistical simulations and the results from the continuous doping simulation. Based on our analysis, we clearly demonstrate that there are increasing errors in the doping distributions when device TCAD simulations are calibrated using continuous doping profiles. This questions the use of continuous doping profiles in the routine calibration and TCAD-based optimization of decananometer scale CMOS transistors. [ABSTRACT FROM AUTHOR]

This paper presents a thorough numerical investigation of statistical effects associated with charge trapping dynamics and their impact on the reliability projection in decananometer MOSFETs. By means of a novel 3-D kinetic Monte Carlo TCAD reliability simulation technology, we track the time-dependent variability associated with granular charge injection and trapping into the oxide traps. We consider the interactions between the statistical variability of the virgin transistors, introduced by the discreteness of charge and granularity of matter, and the stochastic nature of the trap distribution and the trapping process itself. As a result, the path to device failure (PtDF), defined as the stochastic succession of trapping events that bring the device parameters to a predefined failure criteria, is analyzed in detail. In particular, we show that the two stochastic components determining the PtDF, namely the traps' capture time constants and threshold voltage shifts, are uncorrelated. The charge injection variability is shown to play a dominant role in determining the statistical dispersion of the reliability behavior. Furthermore, we show that the short- and long-term reliability behaviors are uncorrelated. Finally, 3-D fringing and percolative effects are shown to play an important role in determining the statistical degradation of nanoscale MOSFETs. [ABSTRACT FROM AUTHOR]

New transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance and to reduce statistical variability (SV). In this paper, the robustness of these architectures to random telegraph noise and bias temperature instability issues is investigated using comprehensive 3-D numerical simulations, and results are compared with those obtained from conventional bulk MOSFETs. Not only the impact of static trapped charges is investigated, but also the charge trapping dynamics are studied to allow device lifetime and failure rate predictions. Our results show that device-to-device variability is barely increased by progressive oxide charge trapping in bulk devices. On the contrary, oxide degradation determines the SV of SoI and FinFET devices. However, the SoI and multigate transistor architectures are shown to be significantly more robust in terms of immunity to time-dependent SV when compared with the conventional bulk device. The comparative study here presented could be of significant importance for reliability resistant CMOS circuits and systems design. [ABSTRACT FROM PUBLISHER]

Conventional bulk CMOS, which is arguably most vulnerable to statistical variability (SV), is the workhorse of the electronic industry for more than three decades. In this paper, the dependence of the SV of key figures of merit on gate geometry, temperature, and body bias in 25-nm gate-length MOSFETs, representative for the 20-nm CMOS technology generation, is systematically investigated using 3-D statistical simulations. The impact of all relevant sources of SV is taken into account. The geometry dependence of the threshold-voltage dispersion (and indeed the dispersion of other key transistor figures of merit) does not necessarily follow the Pelgrom's law due to the complex nonuniform channel doping and the interplay of different SV sources. The DIBL variation, for example, follows a log-normal distribution. The temperature significantly affects the magnitudes of threshold voltage, subthreshold slope, ON/OFF currents, and the corresponding statistical distributions. Reverse body bias increases the threshold voltage and its fluctuation, while forward body bias reduces both of them. [ABSTRACT FROM AUTHOR]

This paper investigates the limitations to the accuracy and the main issues of the spectroscopic analyses of random telegraph noise (RTN) traps in nanoscale MOSFETs. First, the impact of the major variability sources affecting decananometer MOSFET performance on both the RTN time constants and the trap depth estimation is studied as a function of the gate overdrive. Results reveal that atomistic doping and metal gate granularity broaden the statistical distribution of the RTN time constants far more than what comes from the random position of the RTN trap in the 3-D device electrostatics, contributing, in turn, to a significant reduction of the accuracy of trap spectroscopy. The accuracy is shown to improve the higher is the gate overdrive, owing to a more uniform and gate-bias-independent surface potential in the channel, with, however, the possible drawback of triggering the simultaneous trap interaction with both the channel and the gate. This simultaneous interaction is, finally, shown to critically compromise trap spectroscopy in thin-oxide devices. [ABSTRACT FROM PUBLISHER]

In this paper, using three-dimensional statistical numerical simulations, the authors study the intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness (LER), and oxide-thickness variations in realistic bulk MOSFETs scaled to 25, 18, 13, and 9 nm. The scaling is based on a 35 nm MOSFET developed by Toshiba, which has also been used for the calibration of the authors' ‘atomistic’ device simulator. Special attention is paid to the accurate resolution of the individual discrete dopants in the drift-diffusion simulations by introducing density-gradient quantum corrections for both electrons and holes. In the LER simulations, two scenarios have been adopted: In the first one, LER follows the prescriptions of the International Roadmap for Semiconductors; in the second one, LER is kept constant close to the current best values. Combined effects of the different sources of intrinsic parameter fluctuations have also been simulated in the 35 nm reference devices and the results for the standard deviation of the threshold voltage compared to the measured values. [ABSTRACT FROM AUTHOR]

We report a thorough 3-D simulation study of the correlation between multiple, trapped charges in the gate oxide of nanoscale bulk MOSFETs under bias and temperature instability (BTI). The role of complex electrostatic interactions between the trapped charges in the presence of random dopant fluctuations is evaluated, and their impact on the distribution of the threshold voltage shift and on the distribution of the number of trapped charges is analyzed. The results justify the assumptions of a Poisson distribution of the BTI-induced trapped charges and of the lack of correlation between them, when accounting for time-dependent variability in circuits. [ABSTRACT FROM PUBLISHER]