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A class-AB Miller op-amp with symmetrical and significantly enhanced slew-rate and accurately controlled output quiescent current is introduced. It can drive a wide range of resistive and capacitive loads. The output currents can be a factor 16 times higher than the total op-amp quiescent current. Power-efficient static class-AB operation is achieved by including a simple low-power auxiliary amplifier with resistive local common-mode feedback. It has the small-signal figure of merit FOM SS of 28 and 27 for R L =1MΩ and 200Ω.

Robotics initiatives are a great way to make students get involved in Science, Technology, Engineering and Math -STEM- programs and pursue STEM-related careers. However, there are still several stereotypes to be defeated when talking about women as part of the engineering activities within robotics teams. The objective of the present work is to determine the impact of women role models in robotics teams on female students’ development, performance, permanence, and pursuing STEM-related careers. The preliminary results of this educational research project show that the coach’s gender does not influence the student’s performance, but it does influence in perceiving the environment as safer, more comfortable, and inclusive; variables improve the permanence of the female students in the team and the pursuit of STEM-related careers. Supported by the preliminary results shown in this paper, we aim to increase our sample size to achieve stronger statistical conclusions by conducting this study throughout further seasons, being able to measure the impact generated in more female students that are or were members of the robotics team at Tecnologico de Monterrey, Mexico City Campus.

A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit FOMAOLDC of 174 (MV/V) MHz pF/uW and large-signal figure of merit FOMLS of 3(V/us) pF/uW. This work was supported in part by the Spanish Government Agencia Estatal de Investigación (AEI) under Grant TEC2016-80396-C2, in part by the Consejería de Economía y Conocimiento of Junta de Andalucía under Grant P18-FR-4317 (both projects received support from the Fondo Europeo de Desarrollo Regional (FEDER)), and in part by the Consejo Nacional de Ciencia y Tecnologia (CONACyT) under Grant A1-S-43214.

A fully differential and fully integrated low voltage all pass filter operated in the sub-threshold region with variable pole frequency designed in CMOS 130nm technology is presented in this paper. It has only 0.09dB passband ripple. It works with ±200mV DC supplies and dissipates 0.7µW quiescent power. The Miller multiplication effect and quasi floating gate transistors make it possible to achieve a time constant in the range of seconds without consuming excessive Si area. The proposed filter's pole frequency can be varied from 242mHz to 4.8Hz by changing the Miller amplifier's gain. Simulation results in 130nm CMOS technology validate the proposed circuit.

In this work the design and implementation of a white-cane suitable for blind people is presented. The sensing method is based on the relation distance/vibration; the closer the object, the faster is the vibration magnitude. The magnitude of this vibration is passed by four micro DC motors into the fingers of the user, indicating the proximity to the object and its localization. The vibration on the index, middle, ring, and baby fingers are used to indicate the position to the left, front, front, and left, respectively. The proximity sensors are located on a 3-D printed phantom model glasses, enabling the capability of sensing the whole environment in a 360° fashion by means of only moving the head in any direction. Stress and deformation simulations of the proposed white-cane were performed in SolidWorks. Also, the overall power consumption of the instrumentation system is only 2.15 W/h, allowing a six hours of continuous use before battery recharge. Also, the whole white-cane weighs 0.54 kg.

This paper presents the experimental evaluation of a Differential Pair with Active Loads (DPAL), designed and fabricated with a 0.5 μm CMOS process, when operated at a bias current of 1 nA and a power supply of 1 V. The objective is to verify that this circuit can properly perform analog functions while dissipating 1 nW. Therefore, experimental measurements that demonstrate its functionality, power dissipation and leakage currents are presented; the results indicate that it is possible to implement extreme low power analog circuits with this process.

In this paper we present the methodology to build a vision-based wearable system that assists blind people in navigation tasks in unknown indoor environments. The proposed system detects walkable space, obstacles and objects of interest such as doors, chairs, staircases, computers, among others, and plans a path that allows the user to reach the objectives in a safe way (purposeful navigation). The system consists of six modules: for floor segmentation, for building an occupancy grid, for obstacle avoidance, for detecting objects of interest, for path planning and for haptic feedback to the user. Considering the big amount of data that a stereo camera delivers, the fact that the person is moving in a highly dynamic environment and the need of providing immediate feedback to the user, we defined two constraints: 1. Depth and color data must be processed at real time, in a general purpose graphics processing unit GPGPU. 2. Images must be processed in a wearable computer, it means, in a light and small processing device. Moreover, we defined trade-offs between sensing, computation and system usability that allow the system fulfill these requirements appropriately. The partial results in floor segmentation and in building the occupancy 2D grid encourage us to follow developing and improving the constituent modules.

A simple technique to greatly enhance the DC open-loop gain of a Miller op-amp is introduced here. It is based on the utilization of nested regulated cascode amplifiers. It uses conventional Miller compensation and does not increase the supply voltage. The proposed scheme has a DC open-loop gain Figure of Merit FoMAOLDC=24,614kV/V.pF.MHz/µWatt. It is especially appropriate for utilization in modern deep sub-micrometer CMOS technologies with low intrinsic gain. This work was supported in part by the Spanish Ministerio Ciencia e Innovación and the FEDER funds under Grant TEC2016-80396-C2

We present a system for capturing and processing the motor state of patients with reduced mobility aimed to provide clinical feedback for the conduction of a quantitative and objective evaluation of patients. We evaluated our system with patients of a physiotherapeutic clinic. They performed a set of exercises and the system provided tools to measure position, angle and velocity between different points of the body detected with the Microsoft Kinect. We tested the coherence between the Kinect-based assessment and standardized clinical assessment. Results show that our system allows obtaining more precise data from patients with balance impairments, thus, it might be used to carry out an analysis of their motor state and to evaluate it more accurately, in comparison with traditional scales.

The systems based on silicon photomultipliers have become an excellent option to work in several fields, from astrophysics to medical applications. They can replace the traditional photomultiplier tubes due to the fact that they need much lower operational voltages (between 24 and 80 V), their price is more accessible and their high immunity to magnetic fields, simultaneously enabling near single-photon counting capability alongside nanosecond time resolutions. Moreover, their photon detection efficiency is higher than 40% at peak wavelengths (in the blue-green visible part of the spectra). This work describes the design process and first evaluation of an application specific integrated circuit for acquisition and processing of silicon photomultiplier originated analog signals, fabricated in a 180 nm commercial CMOS technology yielding information regarding signal triggering time, time over threshold, amount of charge, as well as the digitized original signal shape.

This paper presents a new architecture for a pseudo-resistor (PR) implemented with MOS transistors, working in subthreshold region, tunable from Mega $\Omega$ to Giga $\Omega$ range. The proposed PR is programmed by controlling the $V_{GS}$ of the MOS transistors with a differential pair. An ultra-low frequency bandpass filter which uses the proposed PR with adjustable highpass cut-off frequency for a tuning range of 0.28 Hz to 900 Hz was designed. The simulated total harmonic distortion is $ for an input voltage of $\mathbf{224}\ mV_{pp}$ . Simulations were performed using HSPICE Analog Design Environment and ON-SEMI 0.5 $\mu \mathbf{m}$ technology parameters which validates the feasibility of the proposed circuit.

An ultra-low-voltage low-power amplifier is introduced. The design is based on the Cherry-Hooper architecture and operates with a ±0.2V supply and ±190mV linear input range. It has an approximately constant bandwidth of 1MHz with a power consumption of 1.7µW. The low-voltage operation is achieved using floating batteries that keep the gates of all differential pairs at a constant value close to the upper rail with large input signal variations. It has a figure of merit of 2.61 MHzpF/µW for a nominal gain A=15.6.

Reported researches emphasizes that increases in pulse pressure (PP) are correlated to arterial stiffness augmentation determined by aging or systemic hypertension. These findings are supported by evidence derived from large cohort analysis performed in well-known populations such as that of the Framingham Study. In this research an analysis, performed in 2077 volunteers, being 1778 normotensives and 299 hypertensive untreated subject, is reported. Both in normotensive and hypertensive non-treated volunteers, PP showed a curvilinear change with respect to age levels and a lack of parallelism with arterial stiffness evaluated through carotid-femoral pulse wave velocity measurement.

This work presents the modeling details of a power upconverter enabled to process base band signals from a ΣΔ modulator. The modulated sequence is encoded for Ultra Wide Band (UWB) transmission using the RF blockset in Mat-lab/Simulink. The system complies with the indoor emission mask for UWB and presents a simple design consisting only of a ΣΔ modulator, an XOR chain as the encoder, a mixer and a local oscillator. The behavioral modeling analysis of the RF stages show that the proposed system exhibits high sensitivity to phase noise above −80 dBc/Hz but is resistant to other system metrics such as nonlinearities and losses.

In 4π microscopy it is commonly assumed that the point spread function is unaffected by the sample, a big assumption considering that cell studies have reported sample-induced phase changes of more than a wavelength. Here we describe a method that does away with that assumption.

In this work, a high-level design of a 2nd order discrete time SD modulator via SIMSIDES-SIMULINK and its FPAA (Anadigm AN231K04-DVLP3 development kit) implementation are presented. Experimental results prove the SIMSIDES viability for low-cost fast prototyping of SD modulators in embedded hardware, which is a handy alternative compared to more expensive and slow CMOS process realization. Experimental results include 50dB SNR, ENOB=8 and a 128 OSR.

An ultra low voltage low power AC coupled amplifier operating with supplies as low as ±0.18 V in 180 nm CMOS technology and a power dissipation of 0.15 μW is introduced. It has digitally programmable gain in the range from 1 to 15 and true constant bandwidth from 0.7 Hz to 2 kHz that is independent on gain. Experimental results from a test chip validate the proposed circuit. Additionally, simulations of the same PGA in 130 nm CMOS technology show that the proposed scheme operates with ±0.08 V supplies, total power dissipation of 0.07 μW and true constant bandwidth from 7.5 Hz to 8 kHz.

In many practical situations, it is important to know the correlation between different quantities — finding correlations helps to gain insights into various relationships and phenomena, and helps to inform analysts. Often, there is not enough empirical data to experimentally determine all possible correlations. In such cases, a natural idea is to supplement this situation with expert estimates. Expert estimates are rather crude. So, to decide whether to act based on these estimates, it is desirable to know how accurate are expert estimates. In this paper, we propose several techniques for gauging this accuracy.

Ultra low-power electronic design is the backbone methodology tool in sensor integration architectures, sensor networking, biomedical applications and wearable electronics. These implementations demand multiple supply voltage domains with different current level requirements that vary from a few microamperes to hundred of miliamperes, such task is done by voltage regulators. This work studies the lower limits of DC-DC power conversion in Buck Converters as well as its feasibility to be embedded as ultra low-power voltage regulator supply; such feasibility criteria is based on inductor and capacitor CMOS technological parameters. Also, the design of a 1.65V/250mA Buck Converter in 0.50µm standard CMOS technology is presented. The designed Buck Converter presents a 41.33% efficiency using an input voltage of 3.3V; input power consumption is 1.023W while delivered power is 0.417W.

The current work proposes an algorithm for implementing a 32-bits chaotic map; which is implemented in an 8-bits microcontroller. For the algorithm, many operations are modified. The operations consist on multiplication, accommodation, addition, and shifting; the modifications are needed because the embedded operations were originally designed for 8-bit numbers. Once the microcontroller algorithm is described, it is translated for its Matlab implementation. Matlab is used for validating the microcontroller code. Using Matlab code, several random sequences are generated and stored in a ‘txt’ file; a statistical testing suite was applied to them, and validating the proposed algorithm.

This work presents a 910MHz/2.4GHz dual-band dipole antenna for Power Harvesting and/or Sensor Network applications whose main advantage lies on its easily tunable bands. Tunability is achieved via the low and high frequency dipole separation Wgap. This separation is used to increase or decrease the S11 magnitude of the required bands. Such tunability can be used to harvest energy in environments where the electric field strength of one carrier band is dominant over the other one, or in the case when both carriers have similar electric field strength. If the environment is crowed by 820MHz-1.02GHz carries Wgap is adjusted to 1mm in order to harvest/sense only the selected band; if the environment is full of 2.24GHz - 2.52 GHz carriers Wgap is set to 7mm. When Wgap is selected to 4mm both bands can be harvested/sensed. The proposed antenna works for UHF-RFID, GSM-840MHz, 3G-UMTS, Wi-Fi and Bluetooth standards. Simulations are carried out in Advanced Design System (ADS) Momentum using commercial FR4 printed circuit board specification.

This paper presents the design of a Voltage Regulation System for UHF Passive RFID Tags which consists of a Clamp Circuit and LDO Voltage Regulator. The Clamp's current consumption is 100nA and 1μA when the voltage reaches levels of 2.6V and 3.6V, respectively. LDO Voltage Regulator is capable of supplying a load current of 4.5 μA with only a current consumption of 900nA. The LDO Voltage Regulator has an overall efficiency of 73%, provides a load regulation of 25.53mV/μA and a settling time of 4μs. The design, simulation and layout are realized using 0.50 μm technology ON-SEMI two poly - three metal.

This paper presents a compact bidirectional current mirror suitable for low voltage applications. The idea is to use complementary transistors in subthreshold which are able to set a reduced bias current through the mirror. The circuit presents a class AB operation with a THD near to 1% at 1MHz. The bandwidth is above 10MHz as shown by simulations using Spectre with 0.5μm CMOS technology parameters.

In this paper, a pulse width amplitude modulation multiplication scheme, that uses a novel flipped voltage follower (FVF) based current switch is presented. Simulations performed in Hspice with the standard AMI 0.5µm CMOS process shows a system with dynamic range of ±140 mV for both input signals with a maximum gain error of 1.1%. The circuit works with VDD = 3 V and a power consumption of 2.2 mW. The multiplier has a bandwidth of 16 kHz.

In this paper, an FPGA-based parallel architecture for the computation of myoelectric signal feature extraction, employing higher order statistics in presented. The three channels myoelectric signal is obtained directly from the user's muscles, in order to obtain prosthesis movement commands which emulate a biological elbow. The proposed architecture was realized in Very High Speed Integrated Circuit (BHSIC) by Hardware Description Language (VHDL), and functionally verified on a Xilinx board, which uses a Spartan-3 XC3S700AN FG48-4 FPGA. Experimental results are presented, and establish a maximum operation frequency of 44.570MHz.

In this paper, a new energy recovery logic based on Floating Gate transistors is presented. Floating-Gate Energy Recovery Logic (FGERL) achieves small transistor count and low voltage operation. High voltage constraint and big transistor count are major issues in adiabatic logics. Most adiabatic approaches use complex circuitry to achieve an efficient charge recovery, requiring high voltage from the power clocking circuits. Reducing transistor count reduces voltage requirement and static dissipation; less dissipating components, less power dissipated. In addition, this proposal is easy to design and implement due to its simplified architecture and single power clock scheme.

A very high frequency analog divider using Floating Gate transistors [1] is presented. The design is based on the Gilbert's cell [2–3], which is formed by a four-quadrant multiplier, and operates in voltage mode where all the transistors are in the saturation region. Simulation results in 0.5um technology show that this cell is useful for high frequency applications.

In this paper, the Birkhoff's Ergodic Theorem, mixing property of the one-dimensional maps, strong convergence criterion and Kullbak-Leibler divergence are applied in order to design chaotic analogical noise generators using MOS QT Circuits, which are governed by one-dimensional chaotic maps. In this work an analogical circuit is used, which have a structure of transistors MOS that operates in current-mode and that uses the transconductance linear principle.

In this paper a cmos current-mode analog circuit for the generation of chaotic signals is presented. This circuit is an electronic realization of the Discrete Verhulst's Logistic Equation (Logistic Map). This circuit was implemented in a 0.35µm standard cmos technology. Monte Carlo simulations and experimental measurements of the fabricated integrated circuit are presented.

CODENSA has started the evolution of the way they are managing their assets through an integrated vision that will lead them to the implementation of a smart electric network. CODENSA's Enterprise Asset Management solution will consist of a Geospatial Infrastructure Management system as the enterprise network and infrastructure asset database, Outage Management System, Field Work Inventory system, Automated Field Crews Dispatch System and Real Time Systems. The implementation of this solution will be the basis of the main goal that CODENSA is pursuing that is the smart electric network.