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We report on the performance of the quantum confined Stark effect (QCSE) in ultra-thin (~350 nm) Ge/SiGe quantum well stacks grown on Si. We demonstrate an absorption contrast $\Delta \alpha /\alpha $ of 2.1 at 1 Vpp swing in QCSE stacks grown on ultra-thin (100 nm) strain relaxed GeSi buffer layers on 300 mm Si wafers. Such ultra-thin QCSE stacks will enable future integration of highly efficient QCSE electro-absorption modulators with low optical coupling loss to passive Si waveguides in a sub-micron silicon photonics platform. [ABSTRACT FROM AUTHOR]

Co has elicited a strong interest to replace Cu for future interconnect applications in microelectronic circuits due to its potentially lower resistivity and better reliability at scaled dimensions. Here, we demonstrate Co wires with electrical cross-sectional areas as small as 34 nm2 using a simple subtractive patterning technique. Semiclassical resistivity modeling of the wire resistivity indicates that grain boundary scattering is the dominant contribution for cross-sectional areas of the order of 100 nm2, while the contribution of surface scattering increases drastically below 50 nm2. Furthermore, wafer-level reliability tests of the Co wires show the high fusing current densities and a strong resistance to thermoelectric stress demonstrating the potential for robust reliability. The resistivity and the reliability of the Co wires are comparable with those of Ru wires. [ABSTRACT FROM AUTHOR]

TCAD finite-element process simulations have been performed on Ge-channel n and pMOSFETs with embedded source/drain stressors or a strained Ge channel on a relaxed SiGe strain relaxed buffer (SRB), respectively, and compared with nanobeam diffraction strain measurements. While there is overall a good agreement between the simulated and experimental strain profiles, some deviations may occur, due to the presence of extended defects in the strain relaxed Ge buffer layers. This highlights the importance of selection of a strain-free reference in the relaxed Ge or SiGe SRB. [ABSTRACT FROM AUTHOR]

This letter reports on the implementation of high carbon content and high phosphorous content Si[sub1-χ]C[χ] layers in the source and drain regions of n-type MOSFET in a 65-nm-node integration scheme. The layers were grown using a novel epitaxial process. It is shown that by implementing stressors with χ ≈ 0.01, nMOSFET device performance is enhanced by up to 10%, driving 880 μA/μm at 1-V V[subDD]. It is also demonstrated that the successful implementation of Si[sub1-χ]C[subχ], relies on the careful choice of integration and epitaxial layer parameters. There is a clear impact of the postepitaxial implantation and thermal treatment on the retained substitutional C content ([Csubsub]). Furthermore, adding a Si capping layer on top of the Si[sub1-χ] C[subχ], greatly improves upon the stressors' stability during the downstream processing and the silicide sheet resistance. [ABSTRACT FROM AUTHOR]