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Chip-on-Wafer-on-Substrate with Si interposer (CoWoS-S) is a TSV-based multi-chip integration technology that is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate multiple chips of SoC, chiplet, and 3D stacks such as high bandwidth memory (HBM). The interposer size increases steadily over the past few years, from one full reticle size (∼830 mm2) to two reticle size (∼1700 mm2). The growth of interposer size offers more integration power to accommodate more active silicon in a package to satisfy the HPC/AI needs. In this paper, we report the new 5th generation CoWoS-S (CoWoS-S5) based on a Si interposer as large as three full reticle size (∼2500 mm2) by a novel 2-way lithography stitching approach. This will accommodate a multiple of logic chips at a total area of 1200 mm2 (with chiplets) together with eight HBM stacks. Besides the dimensional increase of the Si interposer, new features are incorporated to further enhance the electrical and thermal performances of CoWoS-S5 compared with the previous CoWoS-S portfolio. These include an integrated deep trench capacitor (iCap) for enhanced power integrity, 5 layers of sub-micron Cu interconnect with reduced sheet resistance to satisfy high speed die to die interconnect, new TSV structure interposer for both return and insertion loss reduction, and a higher thermal conductivity thermal interface material (TIM) to achieve a lower thermal resistance. Component level reliability with excellent electrical and physical results are also discussed.

One of the prominent challenges for widespread adoption of silicon photonics (SiPh) technology is the availability of an integration platform that can simultaneously meet a wide range of power, performance, and cost criteria in different applications. As a result, there is a diversity of SiPh integrated solutions proposed or demonstrated, but none is considered as a common solution. In this paper, we will first survey industry proposed photonic engine structures in monolithic and heterogeneous integration on their strengths and weaknesses. We will then propose a compact and universal PE structure - COUPE (COmpact Universal Photonic Engine) that could consolidate different requirements onto the same integration platform. COUPE has the electrical IC – photonic IC integration with the electrical interface designed to minimize the EIC-PIC coupling loss. Compared with industry proposed PE technology, COUPE can provide low insertion loss for both grating coupler (GC) and edge coupler (EC). For either GC or EC, the COUPE is a solid structure without cavities or mechanically weak parts, thus enabling low insertion loss without contamination or mechanical concerns. COUPE also has the flexibility to be integrated easily with host ASIC to form a co-package structure. The COUPE integration scheme can meet the most demanding system requirements and pave the way for SiPh-based wafer level system integration (WLSI) for high performance computing applications.

This paper demonstrates the next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications, where the SoIC technology was proposed to integrate multichips with different functionality and technology into a single SoC chip. The new DTCO includes overall die partitioning, die integration, and interconnect. These methodologies can be used for improving time-to-market and trade-off between performance and cost. In this paper, two prototypes of stacking CPU and memory dies are demonstrated with 15% performance gain and 30% average point-to-point distance reduction.

A low-temperature System-on-Integrated- Chip (LT-SoIC) technology has been successfully applied to multi-layer 3D memory cube integration, which enables high bandwidth, low power and small footprint memory for future HPC applications. In addition, using the technology, each memory layer can be thinned to required thickness to maintain total height while supporting more layer counts.Two LT-SoIC processes were presented. One is through-via reveal last and the other one is through-via reveal first. The through-via revealing of each stacked die is one of the most critical process steps. Various conditions of planarization on chip backside after the through-via revealing were studied to mitigate the corner or edge rounding issue, as it may cause poor bonding. By improving the back-side revealing process, we can achieve good bonding for multi-layer stacking, including DRAM stacking with 4-Hi/ 8-Hi/ 12-Hi, and SRAM stacking with 4-Hi, using the LT-SoIC technology.The bonding quality of the LT-SoIC is measured using I-V curve and shear stress equipment. Linear I-V curve was obtained to show it is an Ohmic contact and the bonding strength of >2.5J/m2 was measured to show good bonding force. The through-via chain resistances for 4-Hi SRAM and 4/8/12-Hi DRAM and the breakdown voltage for 8/12- Hi DRAM were measured, too. Reliable results were obtained to indicate the integrity of the through-via chains. After that, the bandwidth density and power consumption between typical 3D memory and the SoIC memory were compared. High bandwidth density and low power consumption are obtained in the SoIC memory. Clear advantages of the SoIC CoW stacking technology are realized for multi-layer memory stacking at low temperature.

A low temperature system-on-integrated-chip (SoIC) bonding and stacking technology is proposed and implemented for 3-D memory integration, such as 3-D static random access memory (SRAM) or dynamic random access memory (DRAM) cube. It extends not only 2-D pin count to 12000/mm2 but also overcomes the obstacle of the stacking height. 4-Hi, 8-Hi, and 12-Hi stacks, each with 1 base die and 4, 8, and 12 dies, respectively, are realized and demonstrated in this article. The daisy chains in the 4-Hi/8-Hi/12-Hi structures incorporating over 10 000 through silicon vias (TSVs) and bonds are tested with liner ${I}-{V}$ curves, which indicates the good bonding and stacking quality. The electrical link from base controller to top DRAM for 12-Hi and 16-Hi high bandwidth memory (HBM) structure is built up to study the bandwidth (BW) and power efficiency. Compared to $\mu $ bump technology, the BW for the 12-Hi and 16-Hi structures using SoIC bonding shows the improvement of 18% and 20%, respectively, under same pin pitch and the power efficiency has the improvement of 8% and 15%. For thermal performance, the 12-Hi and 16-Hi SoIC-bond structure is 7% and 8% better than those using $\mu $ bump technology, respectively. With this innovative SoIC bonding and stacking technology, the bond pitch is scalable to sub-micrometer and the die thickness is manageable to be thinner, which are prospected for the application of higher BW 3-D memory with tera byte (TB)/s per stack.

A logic-HBM2E power delivery system on a chip-on-wafer-on-substrate (CoWoS) platform with a deep trench capacitor (DTC) has been designed and analyzed for high performance computing (HPC) applications. The DTC integrated in the silicon interposer of the CoWoS provides the capacitance density of 300 nF/mm2 and low leakage current of

A high performance 3D dipole antenna with metal thickness >100 μm for wide bandwidth and lateral radiation is realized on InFO package. 25 % wide fractional bandwidth, from 60 to 77 GHz, has been obtained. The beamforming capability of the antenna array system with 6 dBi gain is measured in a 40 nm CMOS RFIC co-designed system.

To accommodate the exceedingly demanding power integrity (PI) requirements for the advanced artificial intelligence (AI) and high performance computing (HPC) components, high-K (HK) based deep trench capacitors (DTC) have been integrated the first time in the silicon interposer with through silicon via (TSV) and fine-pitch interconnects for chip-on-wafer-on-substrate (CoWoS) integration. A specific capacitance density (C s ) of up to 340 nF/mm2 is achieved over a large capacitor array, providing a total capacitance (C t ) of up to 68 μF per interposer die. The HK dielectric has intrinsic time-dependent dielectric breakdown (TDDB) lifetime of > 1,000 years at an operation voltage (V cc ) of 1.35V, and a normalized leakage current (I LK ) density LK & V bd tailing) were observed. The high capacitance, low leakage, large area and reliability-proven Si-interposer integrated DTC, or iCap, provides superior PI performance and therefore greatly enhances the merit of using CoWoS for the next-generation heterogeneous wafer level system integration (WLSI).

To accelerate GaN adoption, beyond-JEDEC system-level reliability should be done to prove the robustness of GaN in applications. In this paper, a new hard switching test vehicle (half-bridge RC load) was proposed & demonstrated to achieve system-like stress, flexibility of acceleration test, low system power consumption with large sample size, easy setup & control which can meet system-level reliability requirement.

This paper explores the next stage of GaN power devices with 2-level integration of peripheral low voltage active and passive devices. The 1st level consists of protection/control/driving circuits, which potentially improves the performance and overcomes the challenges to the power devices. The 2nd level integration has high-low side on-chip integration on a 100V technology platform. The challenge of channel modulation due to substrate bias sharing is effectively eliminated by the invented new scheme. The system efficiency of DC-DC buck converter using such scheme is enhanced with lower on-state resistance and good stability.

A novel 3D InFO inductor is developed to integrate with TSMC 16nm FinFET devices for high efficiency integrated voltage regulator (IVR) design. The 3D InFO inductor is designed using thick through-InFO-via (TIV) copper, where the form factor is 1.4 × 2.2 × 0.15 mm3. It performs 2.14 nH inductance at 140 MHz and 3.2 mΩ resistance at DC. The resistance of power delivery network (PDN) between inductor and load is 1.1 mu. The InFO technology provides the low resistance 3D inductor and PDN concurrently for the IVR system design to achieve a peak power efficiency of 93%.

For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V. The 4th generation FinFET transistors are optimized with device mismatch reduction by 25%∼35% and multi-Vt device options to enable low power and high performance design requirements.

For the first time, we demonstrate the smallest, fully functional 32Mb 6-T high density SRAM reported in literature with scaled bulk FinFETs for CMOS technology beyond 10nm node. Scaled FinFET devices exhibit excellent electrostatic with DIBL of

Advancing the state-of-the-art 16nm technology reported last year, an enhanced 16nm CMOS technology featuring the second generation FinFET transistors and advanced Cu/low-k interconnect is presented. Core devices are re-optimized to provide additional 15% speed boost or 30% power reduction. Device overdrive capability is also extended by 70mV through reliability enhancement. Superior 128Mb High Density (HD) SRAM Vccmin capability of 450mV is achieved with variability reduction for the first time. Metal capacitance reduction by ∼9% is realized with advanced interconnect scheme to enable dynamic power saving.

The first publication on fabrication of a 300 mm size, 50 μm ultra-thin glass interposer is presented. According to measured data and modeling analysis, merits of on-glass inductors and transmission lines outperform those of on-silicon in Q-factor, power dissipation, and power/signal integrity. Glass interposer is a promising building block technology for future hybrid mixed signal heterogeneous chip integration solution.

For the first time, we present a state-of-the-art energy-efficient 16nm technology integrated with FinFET transistors, 0.07um2 high density (HD) SRAM, Cu/low-k interconnect and high density MiM for mobile SoC and computing applications. This technology provides 2X logic density and >35% speed gain or >55% power reduction over our 28nm HK/MG planar technology. To our knowledge, this is the smallest fully functional 128Mb HD FinFET SRAM (with single fin) test-chip demonstrated with low Vccmin for 16nm node. Low leakage (SVt) FinFET transistors achieve excellent short channel control with DIBL of

A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P I on values of 1200/1100 µA/µm for I off =100nA/µm at 1V. Excellent device electrostatic control is demonstrated for gate length (L gate ) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow. This dual-WF approach provides excellent V th roll-off immunity in the short-channel regime that allows properly positioning the long-channel device V th . Enhanced 193nm immersion lithography has enabled the stringent requirements of the 22/20nm ground rules. Reliability of our advanced HK/MG stack is promising. Excellent SRAM static noise margin at 0.45V is reported.

This paper describes an autonomous eye-in-hand coordination application of security robot for services in a variety of applications. We have designed an autonomous mobile security robot called ldquoSecurity Warriorrdquo, which equipped with arms and embedded motion controller combines the non-specific environment of vision system with the robust inverse kinematics computation. In order to reduce the cost and volume, we design an embedded control system for 14 servo motor of robot arms. Besides, we combine inverse kinematics to eye-in-hand servo control robot arm to get closer target and use CCD on robot wrist to feedback target position. In order to reach and grasp the target object, we have used vision system by using particle analysis to find out centroid of region, the edge of the region and the percentage of area of a picture. This system has been integrated and experimentally demonstrated the success of target object acquisition.

We present an optimal partially-depleted silicon-on-insulator (PD-SOI) platform, which demonstrates superior performance of SOI over bulk technology. Device optimization is performed in terms of circuit switch speed and power consumption through channel and S/D engineering. Fundamental device characteristics, SRAM yields, reliability assessment, and physical IP qualification for our PD-SOI platform are all validated to demonstrate the feasibility for high performance applications. Performance comparison based on circuit simulation clearly shows the SOI advantage on area and power consumption. In addition, the strained-SOI (sSOI) technology is developed for further SOI performance enhancement.

In this paper, we have proposed, fabricated and characterized a parallel electron beam micro-column with single-stranded carbon nanotube (CNT) filed emitters. The integrated micro-column consists of a self-aligned CNT field emitter array (FEA), and a multi-layered electrostatic Si focusing lens array. In our design, the emitters, gate and electrostatic lens array are electrically isolated, and each source can be controlled individually. Electron emission performance of the fabricated CNT/Si emitter was characterized. The best turn-on fields, defined as the field required to generate an emission current of 1 nA, were approximately 6 V. When applying a gate voltage of 100 V, a 110 nA anode current is measured. It is seen that CNT/Si emitter showed low threshold voltage; however, the emission current fluctuation was high during high voltage operation.

SOI is today mainly used for high-speed CPU applications. The advantages brought by SOI are still questioned or not clearly understood and little information has been published about the comparison between bulk and SOI CMOS. First reason is that this comparison to be representative must be done for same process features such as gate length and gate oxide thickness, second reason is that designing the same circuit in both bulk and SOI requires a significant investment. 65nm CMOS bulk and SOI both developed at UMC 12" facility with same process features are compared in this paper.

Device optimization on partially-depleted silicon-on-insulator (PD-SOI) CMOS is systematically performed in terms of circuit switching speed and power consumption. The effects of several key factors, such as threshold voltage (Vth), pre-amorphization implantation (PAI), and silicon film thickness (Tsi), are fully investigated and optimized to achieve optimal ring-oscillator performance. We found that well-designed PAI improves circuit delay vs. leakage characteristics, while decreasing Tsi also reduces the propagation delay. We then present the optimized AC performance for a variety of circuits, as well as the DC performance, the SRAM characteristics, and the reliability assessment.

For the first time, 75% and 7% drive current improvement is simultaneously achieved in both N/PMOS by adopting ultimate spacer process (USP) with a single stress liner. High out-of-plane stress in the channel accounts for the simultaneously enhanced drive current in N/PMOS. A 15% speed enhancement without compromising yield and product qualification in field-programmable gate arrays (FPGA) confirms immediate manufacturing feasibility of USP. This process provides a unique approach to significantly enhance device performance for 65nm CMOS technology and beyond. Extreme current increase of 25% in NMOS and 35% in PMOS can be achieved by applying additional strain enhancement methods

The carbon-nanotube field-effect-transistors (CNTFETs) have been explored and proposed to be the promising candidates for the next generation integrated-circuit (IC) devices. The so-called Schottky barrier (SB)-FET is widely used to characterize the operation behavior of a CNTFET, and the Schottky barriers are affected by the gate fields at the metal-nanotube interfaces. By using the double-layered catalyst configuration (nickel and upper SiO 2 layer), SWNTs were in-situ grown across two catalytic pads on a substrate with a thinner thermal oxide layer above the channel and thicker ones at the two source/drain junction terminals. The uni-polar characteristics of a p-type CNTFET was consequently achieved by electrostatic engineering. The turn-off current (I off ) was significantly reduced and the turn-on current (I on ) to I off ratio was then increased up to ∼ 104. The p to n conversion was observed after several cycles of measurement in a vacuum environment presumably due to removal of adsorbed O 2 molecules. On the other hand, the hysteresis behavior of transfer characteristics was still observed, suggesting that the CNTFET could be used in non-volatile memory applications.

In this paper, high quality single-walled carbon nanotubes (SWNTs) were synthesized by multilayered metal catalysts on silicon or silicon oxide substrate using thermal chemical vapor deposition method. The roles of multilayered metal catalyst were investigated by systematically varying the combinations of multilayered structure. Scanning electron microscopy, Atomic force microscopy, Auger electron spectroscopy, and X-ray photoelectron spectroscopy were used to examine the evolution of the morphology and the oxidation state of each constituent of the multilayered structure in the thermal processes and their roles in controlling the formation of SWNTs.

The promising potential of (110) SiGe channel as next generation high performance p-MOSFETs is well demonstrated in this work. As high as 48% of drive current enhancement on SiGe channel p-MOSFETs fabricated on (110) surface have been achieved for the first time. In addition, combining with compressive stress capping layer, the (110) SiGe channel p-MOSFETs exhibits an extended 81% Idsat gain with Idsat of 850muA/mum at 100nA/mum Ioff. The 32% larger longitudinal piezoresistance coefficient compared to Si extracted from SiGe channel p-MOSFET reveals the advantage of applying strain in SiGe channel. The 3.3times hole mobility enhancement of (110) SiGe over (100) Si illustrates the advantage of this device architecture

This articles describes the preliminary design and fabrication results of micro carbon-nano-tube (CNT) column for electron-beam lithography. The column consists of gated single vertical aligned CNT electron source and one metal electrostatic lens. The CNT electron source was fabricated by combination of optical lithography, electron-beam writing and inductively coupled plasma chemical vapor deposition (ICP-CVD) growth. The simulated minimum spot size was 80 nm with one metal electrostatic lens for a 40 nm diameter CNT.

High quality of Sr/sub 0.5/Ba/sub 0.5/Nb/sub 2/O/sub 6/ (SBN50) and Pb/sub 0.95/La/sub 0.05/Ti/sub 0.9875/O/sub 3/ (PLT5) pyroelectric thin films were successfully deposited on Pt-coated silicon by Pulsed Laser Deposition Technique. In this paper, the effect of deposition conditions on the crystallinity and pyroelectricity of SBN50 and PLT thin films was systematically examined. We have found that, SBN50 films have higher dielectric constant /spl epsilon/r of 928 and larger pyroelectric effect (measured by dynamic voltage response) Rv of 1.8*10/sup 3/ V/W at 25 Hz without a poling treatment. Three different PLT films were compared and the PLT5 films possess superior pyroelectric property ( Rv of 1.2*10/sup 3/ V/W at 10 Hz) to the rest two compositions.

Carbon nanotubes (CNTs) have been considered as a prime candidate material of cold cathode emitter for field emission (FE) application. No matter whether the cathode assembly is fabricated by screen printing or in-situ chemical vapor deposition (CVD), the strict requirement of high emission uniformity on a large area display panel still remains a great challenge. There have been a large amount of publications demonstrating the ability of growing large area patterned well-aligned multi-walled carbon nanotubes with uniform diameter and height by thermal CVD. The field emission performance however was hampered due to high carbon nanotube density (> 10/sup 8/ cm/sup -2/) and low emission density (/spl sim/10/sup 4/ cm/sup -2/), which is not attributed solely to the electrical field screening effect. In this report, we used electron beam lithography (EBL) followed by metal deposition/lift-off to define the position and size of nickel catalyst and grew CNTs using inductively-coupled plasma (ICP) CVD. The EBL has been proven to be a straight forward method to define an array of catalyst metal dots with designated size and inter-distance. The ICP-CVD has been shown to grow free-standing vertically-aligned CNTs with uniform diameter and height. And then a gripper-type nano-object manipulation assembly inside a scanning electron microscope (SEM) was utilized to measure the field emission from individual carbon nanotube.

Here we investigate in situ post-treatment of carbon nanofibers in inductively coupled plasma system for field emission improvements. The nanofibers were characterized using SEM, TEM, energy dispersive spectroscopy, micro-Raman spectroscopy and various FE measurements including typical emission current density-electric field (J-E) curves, large-area uniformity of luminance, and long-time stability of emission currents. Certain structural transformations were observed and significantly enhanced FE was achieved. The mechanism of the structural transformations and the corresponding FE enhancement were also investigated.

Reducing overkills is one of the main objectives in the wafer testing process, however the major mean to prevent overkills is retest. In this paper, we formulate the problem of reducing overkills and retests as a stochastic optimization problem to determine optimal threshold values concerning the number of good dies and the number of bins in a lot and wafer to decide whether to go for a retest after a regular wafer probing. The considered stochastic optimization problem is an NP hard problem. We propose an Ordinal Optimization theory based two-level method to solve the problem for good enough threshold values to achieve lesser overkills and retests within a reasonable computational time. Applying to a case based on the true mean of bins of a real semiconductor product, the threshold values we obtained are the best among 1000 sets of randomly generated threshold values in the sense of lesser overkills under a tolerable retest rate.

Summary form only given. A novel coil design for inductively-coupled plasma (ICP) sources for ULSI processing will be presented. To widen the operation range of processing systems based on ICP high density plasma sources, the coil shape is made adjustable by varying the height of the center post connected to a planar coil. The coil is then essentially shallow-dome-shaped with its height adjustable. As the coil shape changes, the profile of the RF field also changes, which in turn changes the location where the major RF power is deposited. Ideally, one can make use of this extra knob to compensate the changes in plasma uniformity as the system parameters such as gas pressure, RF power or bias power are varied. The other feature of the new coil design is that the coil has two sets of multi-turns winding connected in parallel but 180 degree opposite azimuthally. This arrangement can improve the symmetry of the processing system in azimuth direction which has been shown to be highly dependent on the symmetry of the coil. Initial measurements for a proof-of-principle experiment show that the density profile does change with the coil shape as the gas pressure and RF power are fixed.

Summary form only given, as follows. The operation characteristics of an inductively-coupled plasma source have been measured by several different measurement techniques: Langmuir probe, 36 GHz heterodyne interferometer, optical emission spectroscopy and plasma impedance probe. The Ar plasma is generated by exciting a planar inductive coil with 13.56 MHz RF power which is coupled into the 400 mm diameter plasma chamber through a quartz window. Measurements have been made for two different size of antenna: 150 mm and 270 mm with window sizes 200 mm and 320 mm, respectively. The tip of the Langmuir probe is isolated from the bias and measurement electronics by an inductor to force the probe tip to follow the AC plasma floating potential. The 36 GHz heterodyne interferometer employs two free running Gunn oscillators and the phase change was measured by a 70 MHz quadrature mixer. The measurement results have been used to calibrate the Langmuir probe. The RF power absorbed by the plasma was measured by the plasma impedance probe placed between the antenna and matching network. Spatial variations of optical emission from the plasma for different operation conditions have also been measured by a monochrometer/CCD system with an optical fiber head.

Summary form only given. ESD protection circuits are designed to meet certain specifications such as human body model (HBM) voltage. Electrothermal circuit simulation can be of use in protection circuit design. In this work, we propose a new algorithm to evaluate transient device temperatures, such as the drain junction temperature of NMOS devices, so that the electrothermal circuit simulation can be performed accurately. Using the electrothermal circuit simulator, we can examine device heating during HBM testing.